module Wire_4 (A, B, status);
//forward =1 information goes A-> B
//status 00=relax,01=switch, 10=hold, 11=release
	input [1:0] status;
	inout B;
	input A;
	reg loaded,regg;
	wor B,A;
assign B =  (status == 2'b10) ? loaded :
	    (status == 2'b01) ?	 A     :
	     1'bz;
initial
loaded =1'bZ;

always @(posedge status[1])
	begin
		if (status[0]==0)
			begin
				loaded <= (A===1'bx)? 1'bz : A;
			end
	end
endmodule