module test_benchCW;
reg in1,in2,fault1,fault0;
wire out1, out2;


Crosswire CW (
	.in1 (in1),
	.in2 (in2),
	.out1 (out1),
	.out2 (out2),
	.fault1(fault1),
	.fault0(fault0)
	);
initial  
begin     
	in1 = 0;     
 	in2 = 0;
 	fault1 = 0;
	fault0 = 0;
end     
always
     #5 in1 = !in1;
always
     #10 in2 = !in2;
always
     #20 fault1 = !fault1;
always
     #40 fault0 = !fault0;

endmodule