//`timescale 10ns/100ps
module test_benchLBMEM;
reg al,bl,fault1,fault0,x, Zpexl,clk1,clk2,clk3,cl,xl,y,yl,Zpi;
wor Z,Zp;
reg c,d;

MajorityVoter_bi MV (
	.forward(nforward),
	.A(al),
	.B(bl),
	.Z(Z),
	.Zp(Zp),
	.fault1(fault1),
	.fault0(fault0)
	);
Wire_bi wire_1(
.A(c),
.B(xx),
.bi(Z), 
.forward(forward) )	;
//assign Z= forward? c : 1'bz;
assign nforward=(clk2 && clk1);
assign forward = ~nforward;
Wire_bi wire_2(
.A(Zpi),
.B(Zpex),
.bi(Zp), 
.forward(nforward) )	;
//assign Zp= forward? 1'bz:d;
assign a= xl;
assign b= yl;
initial  
begin     
	x =0;     
 	y =0;
 	xl=0;
 	yl=0;//try with zs
 	Zpexl=0;
 	Zpi=0;
 	al=0;
 	bl=0;
 	c=0;
	d=1;
 	fault1 = 0;
	fault0 = 0;
	clk1 <= #125 0;
	clk2=1;
	clk3=1;
end     

always

begin
     #3000 x = ~x;
end

always
     #5000 y = ~y;



always@(posedge clk1)
//violet!
	begin
		clk1 <= #1000 ~clk1;	
		Zpi<=Zpexl	;
		xl <= x;
		yl <= y;
	end
always@(negedge clk1)
	begin
		yl=1'bZ;	
		Zpi=1'bz;
		xl=1'bZ;
		clk1 <= #1000 ~clk1;
	end

always@(posedge clk2)
//blue
	begin
		cl=c;
		al=a;
		bl=b;
		clk2 <= #1250 ~clk2;
	end
	
always@(negedge clk2)
	begin
		al=1'bZ;
		bl=1'bZ;
		cl=1'bZ;
		clk2 <= #750 ~clk2;
	end
	
always@(posedge clk3)
//white
	begin
		c <= xx;
		Zpexl<=Zpex;
		clk3 <= #500 ~clk3;
	end
	
always@(negedge clk3)
	begin
		c<= 1'bz;
		Zpexl <=1'bz;
		clk3 <= #500 ~clk3;
	end
	
endmodule