`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:52:07 03/14/2011 
// Design Name: 
// Module Name:    cachedir 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module cachedir(
    input clock,
    input enable,
    input wren_a,
    input [ 7:0] address_a,
    input [28:0] data_a,
    output [ 28:0] q_a,
    input wren_b,
    input [ 7:0] address_b,
    input [28:0] data_b,
    output [28:0] q_b
    );

reg [28:0] mem1 [(2**7)-1:0];
reg [28:0] mem2 [(2**7)-1:0];
      
always @(posedge clock)
     begin
		if (enable)
         if (wren_a)
            mem1[address_a] <= data_a;
	  end

assign  q_a = mem1[address_a]; 	  

always @(posedge clock)
     begin
 	   if (enable)
         if (wren_b)
            mem2[address_b] <= data_b;
     end
assign  q_b = mem2[address_b];
endmodule