Index: trunk/Xilinx/dram.v
===================================================================
--- trunk/Xilinx/dram.v	(revision 10)
+++ trunk/Xilinx/dram.v	(revision 17)
@@ -74,5 +74,5 @@
    parameter CKE_WIDTH               = 1,       
                                        // # of memory clock enable outputs.
-   parameter CLK_WIDTH               = 2,       
+   parameter CLK_WIDTH               = 1,       
                                        // # of clock outputs.
    parameter COL_WIDTH               = 10,       
Index: trunk/Xilinx/cachedir.v
===================================================================
--- trunk/Xilinx/cachedir.v	(revision 10)
+++ trunk/Xilinx/cachedir.v	(revision 17)
@@ -23,15 +23,15 @@
     input enable,
     input wren_a,
-    input [ 7:0] address_a,
+    input [ 8:0] address_a,
     input [28:0] data_a,
     output [ 28:0] q_a,
     input wren_b,
-    input [ 7:0] address_b,
+    input [ 8:0] address_b,
     input [28:0] data_b,
     output [28:0] q_b
     );
 
-reg [28:0] mem1 [(2**7)-1:0];
-reg [28:0] mem2 [(2**7)-1:0];
+reg [28:0] mem1 [(2**8)-1:0];
+reg [28:0] mem2 [(2**8)-1:0];
       
 always @(posedge clock)