Index: trunk/sim/flash.v
===================================================================
--- trunk/sim/flash.v	(revision 12)
+++ trunk/sim/flash.v	(revision 17)
@@ -25,5 +25,5 @@
 
 // Parameters
-   parameter     addr_bits = 20;
+   parameter     addr_bits = 22;
    parameter     addr_max = (1<<addr_bits)-1;
    parameter     memfilename = "memory.hex";
Index: trunk/sim/simula.do
===================================================================
--- trunk/sim/simula.do	(revision 15)
+++ trunk/sim/simula.do	(revision 17)
@@ -32,5 +32,5 @@
 vlog  $env(XILINX)/../../verilog/src/glbl.v
 #vlog  $XILINX/../../verilog/src/glbl.v
-vlog  ../sim/*.v
+vlog  +define+DEBUG ../sim/*.v
 
 #Pass the parameters for memory model parameter file#
@@ -39,5 +39,8 @@
 #Load the design. Use required libraries.#
 
-vsim -c -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl
+
+vsim -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl
+
+#vsim -c -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl
 #vsim -c -t ps -novopt +notimingchecks work.tb_top glbl
 
Index: trunk/sim/tb_top.v
===================================================================
--- trunk/sim/tb_top.v	(revision 16)
+++ trunk/sim/tb_top.v	(revision 17)
@@ -32,8 +32,8 @@
    wire [DQS_WIDTH-1:0]         ddr2_dqs_n_sdram;
    wire [7:0]                   ddr2_dm_sdram;
-   wire      		        ddr2_clk_sdram;
-   wire           		ddr2_clk_n_sdram;
-   wire           		ddr2_address_sdram;
-   wire [2:0]         		ddr2_ba_sdram;
+   wire      		                 ddr2_clk_sdram;
+   wire           		            ddr2_clk_n_sdram;
+   wire [12:0]          		      ddr2_address_sdram;
+   wire [1:0]         		        ddr2_ba_sdram;
    wire                         ddr2_ras_n_sdram;
    wire                         ddr2_cas_n_sdram;
@@ -45,4 +45,9 @@
    wire 			 stx;
    wire 			 srx;
+   
+   wire [21:0]                    flash_addr; 
+   wire [15:0]                    flash_data;
+   
+
    
    initial begin
@@ -60,5 +65,5 @@
     //     #1000
     //     sys_reset <= 1'b0;
-         #49000
+         #100000
          $display("INFO: TBENCH: Completed simulation!");
          $finish;
@@ -101,5 +106,5 @@
 (
    .clk_in (clk_in),
-   .sysrst (sysrsti_out),
+   .sysrst (sys_rst_out),
 
    // ddr3 memory interface
@@ -110,5 +115,5 @@
    .ddr3_ck_n (ddr2_clk_n_sdram),
    .ddr3_a (ddr2_address_sdram),
-   .ddr3_ba (ddr2_ba_sdram),
+   .ddr3_ba (ddr2_ba_sdram), //FIXME
    .ddr3_ras_n (ddr2_ras_n_sdram),
    .ddr3_cas_n (ddr2_cas_n_sdram),
@@ -164,5 +169,5 @@
                       .we_n      (ddr2_we_n_sdram),
                       .dm_rdqs   (ddr2_dm_sdram[(2*(i+1))-1 : i*2]),
-                      .ba        (ddr2_ba_sdram),
+                      .ba        (ddr2_ba_sdram), //FIXME
                       .addr      (ddr2_address_sdram),
                       .dq        (ddr2_dq_sdram[(16*(i+1))-1 : i*16]),