Index: /trunk/sim/flash.v
===================================================================
--- /trunk/sim/flash.v	(revision 12)
+++ /trunk/sim/flash.v	(revision 17)
@@ -25,5 +25,5 @@
 
 // Parameters
-   parameter     addr_bits = 20;
+   parameter     addr_bits = 22;
    parameter     addr_max = (1<<addr_bits)-1;
    parameter     memfilename = "memory.hex";
Index: /trunk/sim/simula.do
===================================================================
--- /trunk/sim/simula.do	(revision 15)
+++ /trunk/sim/simula.do	(revision 17)
@@ -32,5 +32,5 @@
 vlog  $env(XILINX)/../../verilog/src/glbl.v
 #vlog  $XILINX/../../verilog/src/glbl.v
-vlog  ../sim/*.v
+vlog  +define+DEBUG ../sim/*.v
 
 #Pass the parameters for memory model parameter file#
@@ -39,5 +39,8 @@
 #Load the design. Use required libraries.#
 
-vsim -c -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl
+
+vsim -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl
+
+#vsim -c -t ps -novopt +notimingchecks -L unisims_ver -L XilinxCoreLib work.tb_top glbl
 #vsim -c -t ps -novopt +notimingchecks work.tb_top glbl
 
Index: /trunk/sim/tb_top.v
===================================================================
--- /trunk/sim/tb_top.v	(revision 16)
+++ /trunk/sim/tb_top.v	(revision 17)
@@ -32,8 +32,8 @@
    wire [DQS_WIDTH-1:0]         ddr2_dqs_n_sdram;
    wire [7:0]                   ddr2_dm_sdram;
-   wire      		        ddr2_clk_sdram;
-   wire           		ddr2_clk_n_sdram;
-   wire           		ddr2_address_sdram;
-   wire [2:0]         		ddr2_ba_sdram;
+   wire      		                 ddr2_clk_sdram;
+   wire           		            ddr2_clk_n_sdram;
+   wire [12:0]          		      ddr2_address_sdram;
+   wire [1:0]         		        ddr2_ba_sdram;
    wire                         ddr2_ras_n_sdram;
    wire                         ddr2_cas_n_sdram;
@@ -45,4 +45,9 @@
    wire 			 stx;
    wire 			 srx;
+   
+   wire [21:0]                    flash_addr; 
+   wire [15:0]                    flash_data;
+   
+
    
    initial begin
@@ -60,5 +65,5 @@
     //     #1000
     //     sys_reset <= 1'b0;
-         #49000
+         #100000
          $display("INFO: TBENCH: Completed simulation!");
          $finish;
@@ -101,5 +106,5 @@
 (
    .clk_in (clk_in),
-   .sysrst (sysrsti_out),
+   .sysrst (sys_rst_out),
 
    // ddr3 memory interface
@@ -110,5 +115,5 @@
    .ddr3_ck_n (ddr2_clk_n_sdram),
    .ddr3_a (ddr2_address_sdram),
-   .ddr3_ba (ddr2_ba_sdram),
+   .ddr3_ba (ddr2_ba_sdram), //FIXME
    .ddr3_ras_n (ddr2_ras_n_sdram),
    .ddr3_cas_n (ddr2_cas_n_sdram),
@@ -164,5 +169,5 @@
                       .we_n      (ddr2_we_n_sdram),
                       .dm_rdqs   (ddr2_dm_sdram[(2*(i+1))-1 : i*2]),
-                      .ba        (ddr2_ba_sdram),
+                      .ba        (ddr2_ba_sdram), //FIXME
                       .addr      (ddr2_address_sdram),
                       .dq        (ddr2_dq_sdram[(16*(i+1))-1 : i*16]),
Index: /trunk/os2wb/os2wb.v
===================================================================
--- /trunk/os2wb/os2wb.v	(revision 14)
+++ /trunk/os2wb/os2wb.v	(revision 17)
@@ -1231,10 +1231,10 @@
    .enable(dir_en),
    .wren_a(icache0_alloc || icache0_dealloc || icache_inval_all || cache_init),
-   .address_a({1'b0,icache_index}),
+   .address_a({2'b0,icache_index}),
    .data_a(icache_data),
    .q_a(icache0_do),
    
    .wren_b(icache1_alloc || icache1_dealloc || icache_inval_all || cache_init),
-   .address_b({1'b1,icache_index}),
+   .address_b({2'b01,icache_index}),
    .data_b(icache_data),
    .q_b(icache1_do) 
Index: /trunk/tools/dump2hex.php
===================================================================
--- /trunk/tools/dump2hex.php	(revision 17)
+++ /trunk/tools/dump2hex.php	(revision 17)
@@ -0,0 +1,35 @@
+#!/usr/bin/php -q
+<?php
+
+  // Open the stdin
+  $fp = fopen("php://stdin", "r");
+
+  // Discard first lines
+  for($i=0; $i<6; $i++) fgets($fp);
+
+  // Print only the opcodes to stdout
+  while (!feof($fp)) {
+    $line = fgets($fp);
+    /*$opcode = substr($line, 8, 8);
+    $caratteri = strlen($opcode);
+    if($caratteri != 0){
+        echo $opcode."\n";
+    }*/
+
+    $opcode = substr($line, 8, 4);
+    $caratteri = strlen($opcode);
+    if($caratteri != 0){
+        echo $opcode."\n";
+        $opcode = substr($line, 12, 4);
+        echo $opcode."\n";
+    }
+    else{
+        for($i=0; $i<1; $i++) fgets($fp);
+     } 
+    }
+
+  // Close the input file
+  fclose($fp);
+
+?>
+     
Index: /trunk/Top/W1.v
===================================================================
--- /trunk/Top/W1.v	(revision 14)
+++ /trunk/Top/W1.v	(revision 17)
@@ -33,5 +33,5 @@
    //output        ddr3_reset,
    output [12:0] ddr3_a,
-   output [ 2:0] ddr3_ba,
+   output [ 1:0] ddr3_ba,
    output        ddr3_ras_n,
    output        ddr3_cas_n,
@@ -92,4 +92,5 @@
 wire pllclk;
 wire sysclk;
+wire wb_clk_i;
 wire wb_rst_i;
 wire [35:0] CONTROL0;
@@ -100,5 +101,5 @@
 reg [31:0] cycle_count;
 
-assign flash_clk=1;
+assign flash_clk=wb_clk_i;
 assign flash_adv=0;
 assign flash_rst=!wb_rst_i;
@@ -182,5 +183,5 @@
     .m0_err_o(), 
     .m0_rty_o(), 
-    .m0_cab_i(0),
+    .m0_cab_i(1'b0),
     
     //Ethernet
@@ -197,15 +198,15 @@
     .m1_cab_i(m1_cab_i), 
 
-    .m2_dat_i(0), 
+    .m2_dat_i(64'h0000000000000000), 
     .m2_dat_o(), 
-    .m2_adr_i(0), 
-    .m2_sel_i(0), 
-    .m2_we_i(0), 
-    .m2_cyc_i(0), 
-    .m2_stb_i(0), 
+    .m2_adr_i(64'h0000000000000000), 
+    .m2_sel_i(8'h00), 
+    .m2_we_i(1'b0), 
+    .m2_cyc_i(1'b0), 
+    .m2_stb_i(1'b0), 
     .m2_ack_o(), 
     .m2_err_o(), 
     .m2_rty_o(), 
-    .m2_cab_i(0), 
+    .m2_cab_i(1'b0), 
 
     .m3_dat_i(0), 
@@ -426,5 +427,5 @@
 );
 
-WBFLASH flash (
+WBFLASH flash_inst (
     .wb_clk_i(wb_clk_i), 
     .wb_rst_i(wb_rst_i), 
@@ -477,10 +478,10 @@
     .srx_pad_i(srx), 
     .rts_pad_o(), 
-    .cts_pad_i(1), 
+    .cts_pad_i(1'b1), 
     .dtr_pad_o(), 
-    .dsr_pad_i(1), 
-    .ri_pad_i(0), 
-    .dcd_pad_i(1),
-	 .baud_o(baud_o)
+    .dsr_pad_i(1'b1), 
+    .ri_pad_i(1'b0), 
+    .dcd_pad_i(1'b1),
+    .baud_o(baud_o)
 );
 
@@ -585,5 +586,6 @@
 );
 	
-assign wb_rst_i=(!dcm_locked || !phy_init_done);
+assign wb_rst_i=(!dcm_locked ); //FIXME
+//assign wb_rst_i=(!dcm_locked || !phy_init_done); //FIXME
 	 
 //reg [223:0] ILA_DATA;
Index: /trunk/WB/wb_conbus_top.v
===================================================================
--- /trunk/WB/wb_conbus_top.v	(revision 6)
+++ /trunk/WB/wb_conbus_top.v	(revision 17)
@@ -133,8 +133,14 @@
 
 
+//parameter		s0_addr_w = 1 ;		   	// slave 0 address decode width
+//parameter		s0_addr = 1'b0;	// slave 0 address
+//parameter		s1_addr_w = 41 ;	   		// slave 1 address decode width
+//parameter		s1_addr = {40'h800000FFF0,1'b0};	// slave 1 address 
 parameter		s0_addr_w = 1 ;		   	// slave 0 address decode width
-parameter		s0_addr = 1'b0;	// slave 0 address
+parameter		s0_addr = 1'b1;	     // slave 0 address
+
 parameter		s1_addr_w = 41 ;	   		// slave 1 address decode width
-parameter		s1_addr = {40'h800000FFF0,1'b0};	// slave 1 address 
+parameter		s1_addr = {40'h0000000000,1'b0};	// slave 1 address 
+
 parameter		s2_addr_w = 56 ;  		   
 parameter		s2_addr = {56'h800000FFF0C2C1};	// slave 2 address
Index: /trunk/WB2ALTDDR3/dram_wb.v
===================================================================
--- /trunk/WB2ALTDDR3/dram_wb.v	(revision 10)
+++ /trunk/WB2ALTDDR3/dram_wb.v	(revision 17)
@@ -47,5 +47,5 @@
    //output            ddr3_reset,
    output     [12:0] ddr3_a,
-   output     [ 2:0] ddr3_ba,
+   output     [ 1:0] ddr3_ba,
    output            ddr3_ras_n,
    output            ddr3_cas_n,
@@ -64,10 +64,10 @@
 );
 
-wire [255:0] rd_data_fifo_out;
+wire [127:0] rd_data_fifo_out;
 reg  [ 23:0] rd_addr_cache;
-wire [ 71:0] wr_dout;
+wire [127:0] wr_dout;
 wire [ 31:0] cmd_out;
 reg          wb_stb_i_d;
-reg  [ 31:0] mask_data;
+reg  [ 15:0] mask_data;
 
 wire dram_ready;
@@ -83,8 +83,8 @@
     .phy_init_done(phy_init_done),
     .app_wdf_mask_data(mask_data),
-    .app_af_addr(cmd_out[25:2]),
+    .app_af_addr(cmd_out[31:1]),
     .rd_data_valid(rd_data_valid),
     .rd_data_fifo_out(rd_data_fifo_out),    
-    .app_wdf_data(wr_dout[63:0]),
+    .app_wdf_data(wr_dout[127:0]),
 	 
 	 // in dubbio
@@ -96,5 +96,5 @@
 	 .clk0_tb(),
 	 .idly_clk_200(clk200),
-	 //.rst0_tb(ddr3_reset),
+	 .rst0_tb(ddr3_reset),
     
     .ddr2_dqs(ddr3_dqs),
@@ -110,5 +110,5 @@
     .ddr2_we_n(ddr3_we_n),
     .ddr2_ba(ddr3_ba),
-	 .ddr2_a(ddr3_a),
+    .ddr2_a(ddr3_a),
     .ddr2_dm(ddr3_dm)
 //               |
@@ -178,4 +178,5 @@
 );
 */
+
 assign ddr_rst=!phy_init_done;
 
@@ -299,5 +300,5 @@
 reg rd_data_valid_stb_d3;
 reg rd_data_valid_stb_d4;
-reg [255:0] rd_data_fifo_out_d;
+reg [127:0] rd_data_fifo_out_d;
 reg wb_ack_d;
 
Index: /trunk/Xilinx/dram.v
===================================================================
--- /trunk/Xilinx/dram.v	(revision 10)
+++ /trunk/Xilinx/dram.v	(revision 17)
@@ -74,5 +74,5 @@
    parameter CKE_WIDTH               = 1,       
                                        // # of memory clock enable outputs.
-   parameter CLK_WIDTH               = 2,       
+   parameter CLK_WIDTH               = 1,       
                                        // # of clock outputs.
    parameter COL_WIDTH               = 10,       
Index: /trunk/Xilinx/cachedir.v
===================================================================
--- /trunk/Xilinx/cachedir.v	(revision 10)
+++ /trunk/Xilinx/cachedir.v	(revision 17)
@@ -23,15 +23,15 @@
     input enable,
     input wren_a,
-    input [ 7:0] address_a,
+    input [ 8:0] address_a,
     input [28:0] data_a,
     output [ 28:0] q_a,
     input wren_b,
-    input [ 7:0] address_b,
+    input [ 8:0] address_b,
     input [28:0] data_b,
     output [28:0] q_b
     );
 
-reg [28:0] mem1 [(2**7)-1:0];
-reg [28:0] mem2 [(2**7)-1:0];
+reg [28:0] mem1 [(2**8)-1:0];
+reg [28:0] mem2 [(2**8)-1:0];
       
 always @(posedge clock)