Index: /trunk/sim/sim_tb_top.v =================================================================== --- /trunk/sim/sim_tb_top.v (revision 10) +++ /trunk/sim/sim_tb_top.v (revision 22) @@ -289,5 +289,5 @@ .CS_WIDTH (CS_WIDTH), .CS_BITS (CS_BITS), - .DM_WIDTH (DM_WIDTH), + .DM_WIDTH (DM_WIDTH), .DQ_WIDTH (DQ_WIDTH), .DQ_PER_DQS (DQ_PER_DQS), @@ -318,6 +318,6 @@ .SIM_ONLY (SIM_ONLY), .RST_ACT_LOW (RST_ACT_LOW), - .CLK_TYPE (CLK_TYPE), - .DLL_FREQ_MODE (DLL_FREQ_MODE), + .CLK_TYPE (CLK_TYPE), + .DLL_FREQ_MODE (DLL_FREQ_MODE), .CLK_PERIOD (CLK_PERIOD) ) @@ -341,5 +341,5 @@ .ddr2_ba (ddr2_ba_fpga), .ddr2_a (ddr2_address_fpga), - .error (error), + //.error (error), Index: /trunk/sim/simula.do =================================================================== --- /trunk/sim/simula.do (revision 17) +++ /trunk/sim/simula.do (revision 22) @@ -45,4 +45,6 @@ #vsim -c -t ps -novopt +notimingchecks work.tb_top glbl +add wave sim:/tb_top/W1_inst/dram_wb_inst/* +#exit pause onerror {resume} Index: /trunk/sim/tb_top.v =================================================================== --- /trunk/sim/tb_top.v (revision 17) +++ /trunk/sim/tb_top.v (revision 22) @@ -14,4 +14,9 @@ localparam real TCYC_200 = 5.0; parameter RST_ACT_LOW = 1; // =1 for active low reset, =0 for active high + localparam real TPROP_DQS = 0.01; // Delay for DQS signal during Write Operation + localparam real TPROP_DQS_RD = 0.01; // Delay for DQS signal during Read Operation + localparam real TPROP_PCB_CTRL = 0.01; // Delay for Address and Ctrl signals + localparam real TPROP_PCB_DATA = 0.01; // Delay for data signal during Write operation + localparam real TPROP_PCB_DATA_RD = 0.01; // Delay for data signal during Read operation @@ -32,14 +37,31 @@ wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram; wire [7:0] ddr2_dm_sdram; - wire ddr2_clk_sdram; - wire ddr2_clk_n_sdram; - wire [12:0] ddr2_address_sdram; - wire [1:0] ddr2_ba_sdram; - wire ddr2_ras_n_sdram; - wire ddr2_cas_n_sdram; - wire ddr2_we_n_sdram; - wire [CS_WIDTH-1:0] ddr2_cs_n_sdram; - wire ddr2_cke_sdram; - wire [ODT_WIDTH-1:0] ddr2_odt_sdram; + reg [7:0] ddr2_dm_sdram_tmp; + reg ddr2_clk_sdram; + reg ddr2_clk_n_sdram; + reg [12:0] ddr2_address_sdram; + reg [1:0] ddr2_ba_sdram; + reg ddr2_ras_n_sdram; + reg ddr2_cas_n_sdram; + reg ddr2_we_n_sdram; + reg [CS_WIDTH-1:0] ddr2_cs_n_sdram; + reg ddr2_cke_sdram; + reg [ODT_WIDTH-1:0] ddr2_odt_sdram; + + wire [DQ_WIDTH-1:0] ddr2_dq_fpga; + wire [DQS_WIDTH-1:0] ddr2_dqs_fpga; + wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga; + wire [7:0] ddr2_dm_fpga; + wire ddr2_clk_fpga; + wire ddr2_clk_n_fpga; + wire [12:0] ddr2_address_fpga; + wire [1:0] ddr2_ba_fpga; + wire ddr2_ras_n_fpga; + wire ddr2_cas_n_fpga; + wire ddr2_we_n_fpga; + wire [CS_WIDTH-1:0] ddr2_cs_n_fpga; + wire ddr2_cke_fpga; + wire [ODT_WIDTH-1:0] ddr2_odt_fpga; + wire stx; @@ -57,6 +79,6 @@ // Create VCD trace file - $dumpfile("trace.vcd"); - $dumpvars(); + // $dumpfile("trace.vcd"); + // $dumpvars(); // Run the simulation @@ -65,5 +87,5 @@ // #1000 // sys_reset <= 1'b0; - #100000 + #700_000 $display("INFO: TBENCH: Completed simulation!"); $finish; @@ -109,18 +131,18 @@ // ddr3 memory interface - .ddr3_dq (ddr2_dq_sdram), - .ddr3_dqs (ddr2_dqs_n_sdram), - .ddr3_dqs_n (ddr2_dqs_n_sdram), - .ddr3_ck (ddr2_clk_sdram), - .ddr3_ck_n (ddr2_clk_n_sdram), - .ddr3_a (ddr2_address_sdram), - .ddr3_ba (ddr2_ba_sdram), //FIXME - .ddr3_ras_n (ddr2_ras_n_sdram), - .ddr3_cas_n (ddr2_cas_n_sdram), - .ddr3_we_n (ddr2_we_n_sdram), - .ddr3_cs_n (ddr2_cs_n_sdram), - .ddr3_odt (ddr2_odt_sdram), - .ddr3_ce (ddr2_cke_sdram), - .ddr3_dm (ddr2_dm_sdram), + .ddr3_dq (ddr2_dq_fpga), + .ddr3_dqs (ddr2_dqs_fpga), + .ddr3_dqs_n (ddr2_dqs_n_fpga), + .ddr3_ck (ddr2_clk_fpga), + .ddr3_ck_n (ddr2_clk_n_fpga), + .ddr3_a (ddr2_address_fpga), + .ddr3_ba (ddr2_ba_fpga), //FIXME + .ddr3_ras_n (ddr2_ras_n_fpga), + .ddr3_cas_n (ddr2_cas_n_fpga), + .ddr3_we_n (ddr2_we_n_fpga), + .ddr3_cs_n (ddr2_cs_n_fpga), + .ddr3_odt (ddr2_odt_fpga), + .ddr3_ce (ddr2_cke_fpga), + .ddr3_dm (ddr2_dm_fpga), // Console interface @@ -156,4 +178,71 @@ .flash_rst(flash_rst) ); + +//DDR2 model +// + + always @( * ) begin + ddr2_clk_sdram <= #(TPROP_PCB_CTRL) ddr2_clk_fpga; + ddr2_clk_n_sdram <= #(TPROP_PCB_CTRL) ddr2_clk_n_fpga; + ddr2_address_sdram <= #(TPROP_PCB_CTRL) ddr2_address_fpga; + ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga; + ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga; + ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga; + ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga; + ddr2_cs_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga; + ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga; + ddr2_odt_sdram <= #(TPROP_PCB_CTRL) ddr2_odt_fpga; + ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation + end + +assign ddr2_dm_sdram = ddr2_dm_sdram_tmp; + +genvar dqwd; + generate + for (dqwd = 0;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay + WireDelay # + ( + .Delay_g (TPROP_PCB_DATA), + .Delay_rd (TPROP_PCB_DATA_RD) + ) + u_delay_dq + ( + .A (ddr2_dq_fpga[dqwd]), + .B (ddr2_dq_sdram[dqwd]), + .reset (sys_rst_n) + ); + end + endgenerate + + + genvar dqswd; + generate + for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay + WireDelay # + ( + .Delay_g (TPROP_DQS), + .Delay_rd (TPROP_DQS_RD) + ) + u_delay_dqs + ( + .A (ddr2_dqs_fpga[dqswd]), + .B (ddr2_dqs_sdram[dqswd]), + .reset (sys_rst_n) + ); + + WireDelay # + ( + .Delay_g (TPROP_DQS), + .Delay_rd (TPROP_DQS_RD) + ) + u_delay_dqs_n + ( + .A (ddr2_dqs_n_fpga[dqswd]), + .B (ddr2_dqs_n_sdram[dqswd]), + .reset (sys_rst_n) + ); + end + endgenerate + // if the data width is multiple of 16 //for(j = 0; j < CS_NUM; j = j+1) begin : gen_cs Index: unk/sim/wiredly.vhd =================================================================== --- /trunk/sim/wiredly.vhd (revision 10) +++ (revision ) @@ -1,133 +1,0 @@ ---***************************************************************************** --- DISCLAIMER OF LIABILITY --- --- This file contains proprietary and confidential information of --- Xilinx, Inc. ("Xilinx"), that is distributed under a license --- from Xilinx, and may be used, copied and/or disclosed only --- pursuant to the terms of a valid license agreement with Xilinx. --- --- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION --- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER --- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT --- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, --- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx --- does not warrant that functions included in the Materials will --- meet the requirements of Licensee, or that the operation of the --- Materials will be uninterrupted or error-free, or that defects --- in the Materials will be corrected. Furthermore, Xilinx does --- not warrant or make any representations regarding use, or the --- results of the use, of the Materials in terms of correctness, --- accuracy, reliability or otherwise. --- --- Xilinx products are not designed or intended to be fail-safe, --- or for use in any application requiring fail-safe performance, --- such as life-support or safety devices or systems, Class III --- medical devices, nuclear facilities, applications related to --- the deployment of airbags, or any other applications that could --- lead to death, personal injury or severe property or --- environmental damage (individually and collectively, "critical --- applications"). Customer assumes the sole risk and liability --- of any use of Xilinx products in critical applications, --- subject only to applicable laws and regulations governing --- limitations on product liability. --- --- Copyright 2007, 2008 Xilinx, Inc. --- All rights reserved. --- --- This disclaimer and copyright notice must be retained as part --- of this file at all times. ---***************************************************************************** --- ____ ____ --- / /\/ / --- /___/ \ / Vendor : Xilinx --- \ \ \/ Version : 3.6 --- \ \ Application : MIG --- / / Filename : wiredly.vhd --- /___/ /\ Date Last Modified : $Date: 2010/06/29 12:03:42 $ --- \ \ / \ Date Created : Mon Jun 18 2007 --- \___\/\___\ --- --- Device : Virtex-5 --- Design Name : DDR2 --- Description: This module provide --- the definition of a zero ohm component (A, B). --- --- The applications of this component include: --- . Normal operation of a jumper wire (data flowing in both directions) --- --- The component consists of 2 ports: --- . Port A: One side of the pass-through switch --- . Port B: The other side of the pass-through switch - --- The model is sensitive to transactions on all ports. Once a --- transaction is detected, all other transactions are ignored --- for that simulation time (i.e. further transactions in that --- delta time are ignored). --- --- Model Limitations and Restrictions: --- Signals asserted on the ports of the error injector should not have --- transactions occuring in multiple delta times because the model --- is sensitive to transactions on port A, B ONLY ONCE during --- a simulation time. Thus, once fired, a process will --- not refire if there are multiple transactions occuring in delta times. --- This condition may occur in gate level simulations with --- ZERO delays because transactions may occur in multiple delta times. ---***************************************************************************** - -library IEEE; - use IEEE.Std_Logic_1164.all; - -entity WireDelay is - generic ( - Delay_g : time; - Delay_rd : time); - port - (A : inout Std_Logic; - B : inout Std_Logic; - reset : in Std_Logic - ); -end WireDelay; - - -architecture WireDelay_a of WireDelay is - - signal A_r : Std_Logic; - signal B_r : Std_Logic; - signal line_en : Std_Logic; - -begin - - A <= A_r; - B <= B_r; - - ABC0_Lbl: process (reset, A, B) - begin - if (reset = '0') then - line_en <= '0'; - else - if (A /= A_r) then - line_en <= '0'; - elsif (B_r /= B) then - line_en <= '1'; - else - line_en <= line_en; - end if; - end if; - - end process ABC0_Lbl; - - lnenab: process (reset, line_en, A, B) - begin - if (reset = '0') then - A_r <= 'Z'; - B_r <= 'Z'; - elsif (line_en = '1') then - A_r <= TRANSPORT B AFTER Delay_rd; - B_r <= 'Z'; - else - B_r <= TRANSPORT A AFTER Delay_g; - A_r <= 'Z'; - end if; - end process; - -end WireDelay_a; Index: unk/sim/sim.do =================================================================== --- /trunk/sim/sim.do (revision 10) +++ (revision ) @@ -1,125 +1,0 @@ -############################################################################### -## DISCLAIMER OF LIABILITY -## -## This file contains proprietary and confidential information of -## Xilinx, Inc. ("Xilinx"), that is distributed under a license -## from Xilinx, and may be used, copied and/or disclosed only -## pursuant to the terms of a valid license agreement with Xilinx. -## -## XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -## ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -## EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -## LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -## MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -## does not warrant that functions included in the Materials will -## meet the requirements of Licensee, or that the operation of the -## Materials will be uninterrupted or error-free, or that defects -## in the Materials will be corrected. Furthermore, Xilinx does -## not warrant or make any representations regarding use, or the -## results of the use, of the Materials in terms of correctness, -## accuracy, reliability or otherwise. -## -## Xilinx products are not designed or intended to be fail-safe, -## or for use in any application requiring fail-safe performance, -## such as life-support or safety devices or systems, Class III -## medical devices, nuclear facilities, applications related to -## the deployment of airbags, or any other applications that could -## lead to death, personal injury or severe property or -## environmental damage (individually and collectively, "critical -## applications"). Customer assumes the sole risk and liability -## of any use of Xilinx products in critical applications, -## subject only to applicable laws and regulations governing -## limitations on product liability. -## -## Copyright 2007, 2008 Xilinx, Inc. -## All rights reserved. -## -## This disclaimer and copyright notice must be retained as part -## of this file at all times. -############################################################################### -## ____ ____ -## / /\/ / -## /___/ \ / Vendor : Xilinx -## \ \ \/ Version : 3.6 -## \ \ Application : MIG -## / / Filename : sim.do -## /___/ /\ Date Last Modified : $Date: 2010/06/29 12:03:41 $ -## \ \ / \ Date Created : Mon May 14 2007 -## \___\/\___\ -## -##Device: Virtex-5 -##Purpose: -## Sample sim .do file to compile and simulate memory interface -## design and run the simulation for specified period of time. Display the -## waveforms that are listed with "add wave" command. -## Assumptions: -## - Simulation takes place in \sim folder of MIG output directory -##Reference: -##Revision History: -############################################################################### -vlib work - -#Map the required libraries here.# - -#Compile all modules# -vlog ../rtl/ddr2_chipscope* -vlog ../rtl/* -#Compile files in sim folder (excluding model parameter file)# -#$XILINX variable must be set -vlog $env(XILINX)/verilog/src/glbl.v -vlog ../sim/*.v - -#Pass the parameters for memory model parameter file# -vlog +incdir+. +define+x512Mb +define+sg37E +define+x16 ddr2_model.v - -#Load the design. Use required libraries.# -vsim -t ps -novopt +notimingchecks -L unisims_ver work.sim_tb_top glbl - -onerror {resume} -#Log all the objects in design. These will appear in .wlf file# -log -r /* -#View sim_tb_top signals in waveform# -add wave sim:/sim_tb_top/* - -#Change radix to Hexadecimal# -radix hex -#Supress Numeric Std package and Arith package warnings.# -#For VHDL designs we get some warnings due to unknown values on some signals at startup# -# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0# -#We may also get some Arithmetic packeage warnings because of unknown values on# -#some of the signals that are used in an Arithmetic operation.# -#In order to suppress these warnings, we use following two commands# -set NumericStdNoWarnings 1 -set StdArithNoWarnings 1 - -#Choose simulation run time by inserting a breakpoint and then run for specified # -#period. For more details, refer to Simulation Guide section of MIG user guide (UG086).# -when {/sim_tb_top/phy_init_done = 1} { -if {[when -label a_100] == ""} { -when -label a_100 { $now = 50 us } { -nowhen a_100 -report simulator control -report simulator state -if {[examine /sim_tb_top/error] == 0} { -echo "TEST PASSED" -stop -} -if {[examine /sim_tb_top/error] != 0} { -echo "TEST FAILED: DATA ERROR" -stop -} -} -} -} - -#In case calibration fails to complete, choose the run time and then stop# -when {$now = @500 us and /sim_tb_top/phy_init_done != 1} { -echo "TEST FAILED: CALIBRATION DID NOT COMPLETE" -stop -} - -echo "NOTE: Initial 200us power on period is skipped for simulation. - Change SIM_ONLY parameter in sim_tb_top file to activate this." - -run -all -stop Index: /trunk/NOR-flash/WBFLASH.v =================================================================== --- /trunk/NOR-flash/WBFLASH.v (revision 8) +++ /trunk/NOR-flash/WBFLASH.v (revision 22) @@ -155,5 +155,5 @@ assign flash_oen=((wb_cyc_i && wb_stb_i) || (wb1_cyc_i && wb1_stb_i) ? 0:1); -assign flash_wen=1; +assign flash_wen= !wb_we_i; assign flash_cen=0; Index: /trunk/os2wb/os2wb.v =================================================================== --- /trunk/os2wb/os2wb.v (revision 17) +++ /trunk/os2wb/os2wb.v (revision 22) @@ -119,6 +119,9 @@ `define PCX_REQ_CAS_COMPARE 5'b11111 -`define MEM_SIZE 64'h00000000_10000000 - +//`define MEM_SIZE 64'h00000000_10000000 //256 MB +//`define MEM_SIZE 64'h00000000_00100000 //1MB +`define MEM_SIZE 64'h00000000_00001000 //256KB + +// sal: escludo test della DRAM `define TEST_DRAM 1 `define TEST_DRAM 1 `define DEBUGGING 1 @@ -178,9 +181,10 @@ pcx_fifo pcx_fifo_inst( .clk(clk), - .rst(!rstn), + .rst(!rstn), .din({pcx_atom_1,pcx_req_1,pcx_data}), .rd_en(fifo_rd), .wr_en((pcx_req_1!=5'b00000 && pcx_data[123]) || (pcx_atom_2 && pcx_data_123_d)), .empty(pcx_fifo_empty), + .full(), .dout(pcx_data_fifo) ); @@ -209,8 +213,9 @@ if(rstn==0) begin + //$display("INFO: OS2WB: RST_DRAM at %t",$time); if(`TEST_DRAM) state<=`TEST_DRAM_1; else - state<=`INIT_DRAM_1; // DRAM initialization is mandatory! + state<=`INIT_DRAM_1; // DRAM initialization is mandatory! cpx_ready<=0; fifo_rd<=0; @@ -230,4 +235,5 @@ `TEST_DRAM_1: begin + $display("INFO: OS2WB: TEST_DRAM_1"); wb_cycle<=1; wb_strobe<=1; @@ -239,4 +245,5 @@ if(wb_ack) begin + $display("INFO: OS2WB: TEST_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr); wb_strobe<=0; if(wb_addr<`MEM_SIZE-8) @@ -258,4 +265,5 @@ `TEST_DRAM_3: begin + $display("INFO: OS2WB: TEST_DRAM_3"); wb_cycle<=1; wb_strobe<=1; @@ -266,4 +274,5 @@ if(wb_ack) begin + $display("INFO: OS2WB: TEST_DRAM_4 at %t",$time); wb_strobe<=0; if(wb_addr<`MEM_SIZE-8) @@ -274,7 +283,11 @@ state<=`TEST_DRAM_3; end + else + $display("INFO: OS2WB: TEST_DRAM_4 error in read addres %x at %t",wb_addr,$time); + end else begin + $display("INFO: OS2WB: INIT_DRAM at %t",$time); state<=`INIT_DRAM_1; wb_cycle<=0; @@ -300,4 +313,8 @@ if(wb_addr<`MEM_SIZE-8) begin + //for debug + // if (wb_addr[10:3]==8'b0) + // $display("INFO: OS2WB: INIT_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr); + // wb_addr[31:0]<=wb_addr[31:0]+8; pcx_packet_d[64+11:64+4]<=pcx_packet_d[64+11:64+4]+1; // Address for cachedir init @@ -306,4 +323,5 @@ else begin + $display("INFO: OS2WB: WAKEUP_DRAM at %t",$time); state<=`WAKEUP; wb_cycle<=0; @@ -349,4 +367,5 @@ if(`DEBUGGING) begin + $display("INFO: OS2WB: GOT_PCX_REQ"); wb_sel[1:0]<=pcx_packet[113:112]; wb_sel[2]<=1; @@ -1236,5 +1255,5 @@ .wren_b(icache1_alloc || icache1_dealloc || icache_inval_all || cache_init), - .address_b({2'b01,icache_index}), + .address_b({2'b0,icache_index}), .data_b(icache_data), .q_b(icache1_do) @@ -1245,10 +1264,10 @@ .enable(dir_en), .wren_a(icache2_alloc || icache2_dealloc || icache_inval_all || cache_init), - .address_a({1'b0,icache_index}), + .address_a({2'b0,icache_index}), .data_a(icache_data), .q_a(icache2_do), .wren_b(icache3_alloc || icache3_dealloc || icache_inval_all || cache_init), - .address_b({1'b1,icache_index}), + .address_b({2'b0,icache_index}), .data_b(icache_data), .q_b(icache3_do) Index: /trunk/os2wb/s1_top.v =================================================================== --- /trunk/os2wb/s1_top.v (revision 10) +++ /trunk/os2wb/s1_top.v (revision 22) @@ -140,10 +140,11 @@ //.spc_scanout0(spc_scanout0), //.spc_scanout1(spc_scanout1), - //.tst_ctu_mbist_done(tst_ctu_mbist_done), - //.tst_ctu_mbist_fail(tst_ctu_mbist_fail), - //.spc_efc_ifuse_data(spc_efc_ifuse_data), - //.spc_efc_dfuse_data(spc_efc_dfuse_data), - - // Wires connected to SPARC Core inputs + //sal: controllare se in sintesi questi 4 segnali danno problemi!!! + .tst_ctu_mbist_done(), + .tst_ctu_mbist_fail(), + .spc_efc_ifuse_data(), + .spc_efc_dfuse_data(), + // +// Wires connected to SPARC Core inputs .pcx_spc_grant_px(pcx_spc_grant_px), .cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2), @@ -273,5 +274,5 @@ .fp_rdy(fp_rdy!=8'h00), - .eth_int(0/*eth_irq_i*/) + .eth_int(1'b0/*eth_irq_i*/) ); @@ -295,5 +296,5 @@ .ctu_tst_short_chain(ctu_tst_short_chain), - .si(0), + .si(1'b0), .so() ); Index: /trunk/Top/W1.v =================================================================== --- /trunk/Top/W1.v (revision 17) +++ /trunk/Top/W1.v (revision 22) @@ -210,63 +210,63 @@ .m2_cab_i(1'b0), - .m3_dat_i(0), + .m3_dat_i(64'h0000000000000000), .m3_dat_o(), - .m3_adr_i(0), - .m3_sel_i(0), - .m3_we_i(0), - .m3_cyc_i(0), - .m3_stb_i(0), + .m3_adr_i(64'h0000000000000000), + .m3_sel_i(8'h00), + .m3_we_i(1'b0), + .m3_cyc_i(1'b0), + .m3_stb_i(1'b0), .m3_ack_o(), .m3_err_o(), .m3_rty_o(), - .m3_cab_i(0), - - .m4_dat_i(0), + .m3_cab_i(1'b0), + + .m4_dat_i(64'h0000000000000000), .m4_dat_o(), - .m4_adr_i(0), - .m4_sel_i(0), - .m4_we_i(0), - .m4_cyc_i(0), - .m4_stb_i(0), + .m4_adr_i(64'h0000000000000000), + .m4_sel_i(8'h00), + .m4_we_i(1'b0), + .m4_cyc_i(1'b0), + .m4_stb_i(1'b0), .m4_ack_o(), .m4_err_o(), .m4_rty_o(), - .m4_cab_i(0), - - .m5_dat_i(0), + .m4_cab_i(1'b0), + + .m5_dat_i(64'h0000000000000000), .m5_dat_o(), - .m5_adr_i(0), - .m5_sel_i(0), - .m5_we_i(0), - .m5_cyc_i(0), - .m5_stb_i(0), + .m5_adr_i(64'h0000000000000000), + .m5_sel_i(8'h00), + .m5_we_i(1'b0), + .m5_cyc_i(1'b0), + .m5_stb_i(1'b0), .m5_ack_o(), .m5_err_o(), .m5_rty_o(), - .m5_cab_i(0), - - .m6_dat_i(0), + .m5_cab_i(1'b0), + + .m6_dat_i(64'h0000000000000000), .m6_dat_o(), - .m6_adr_i(0), - .m6_sel_i(0), - .m6_we_i(0), - .m6_cyc_i(0), - .m6_stb_i(0), + .m6_adr_i(64'h0000000000000000), + .m6_sel_i(8'h00), + .m6_we_i(1'b0), + .m6_cyc_i(1'b0), + .m6_stb_i(1'b0), .m6_ack_o(), .m6_err_o(), .m6_rty_o(), - .m6_cab_i(0), - - .m7_dat_i(0), + .m6_cab_i(1'b0), + + .m7_dat_i(64'h0000000000000000), .m7_dat_o(), - .m7_adr_i(0), - .m7_sel_i(0), - .m7_we_i(0), - .m7_cyc_i(0), - .m7_stb_i(0), + .m7_adr_i(64'h0000000000000000), + .m7_sel_i(8'h00), + .m7_we_i(1'b0), + .m7_cyc_i(1'b0), + .m7_stb_i(1'b0), .m7_ack_o(), .m7_err_o(), .m7_rty_o(), - .m7_cab_i(0), + .m7_cab_i(1'b0), //DRAM @@ -279,6 +279,6 @@ .s0_stb_o(s0_stb_o), .s0_ack_i(s0_ack_i), - .s0_err_i(0), - .s0_rty_i(0), + .s0_err_i(1'b0), + .s0_rty_i(1'b0), .s0_cab_o(), @@ -335,5 +335,5 @@ .s4_cab_o(s4_cab_o), - .s5_dat_i(0), + .s5_dat_i(64'h0000000000000000), .s5_dat_o(), .s5_adr_o(), @@ -342,10 +342,10 @@ .s5_cyc_o(), .s5_stb_o(), - .s5_ack_i(0), - .s5_err_i(0), - .s5_rty_i(0), + .s5_ack_i(1'b0), + .s5_err_i(1'b0), + .s5_rty_i(1'b0), .s5_cab_o(), - .s6_dat_i(0), + .s6_dat_i(64'h0000000000000000), .s6_dat_o(), .s6_adr_o(), @@ -354,10 +354,10 @@ .s6_cyc_o(), .s6_stb_o(), - .s6_ack_i(0), - .s6_err_i(0), - .s6_rty_i(0), + .s6_ack_i(1'b0), + .s6_err_i(1'b0), + .s6_rty_i(1'b0), .s6_cab_o(), - .s7_dat_i(0), + .s7_dat_i(64'h0000000000000000), .s7_dat_o(), .s7_adr_o(), @@ -366,7 +366,7 @@ .s7_cyc_o(), .s7_stb_o(), - .s7_ack_i(0), - .s7_err_i(0), - .s7_rty_i(0), + .s7_ack_i(1'b0), + .s7_err_i(1'b0), + .s7_rty_i(1'b0), .s7_cab_o() ); Index: /trunk/WB/wb_conbus_top.v =================================================================== --- /trunk/WB/wb_conbus_top.v (revision 17) +++ /trunk/WB/wb_conbus_top.v (revision 22) @@ -133,20 +133,20 @@ -//parameter s0_addr_w = 1 ; // slave 0 address decode width -//parameter s0_addr = 1'b0; // slave 0 address -//parameter s1_addr_w = 41 ; // slave 1 address decode width -//parameter s1_addr = {40'h800000FFF0,1'b0}; // slave 1 address +// address for DDR from 0x0 to 0x7fffffff_ffffffff (64'h00000000_00000000 to 64'h7fffffff_ffffffff) parameter s0_addr_w = 1 ; // slave 0 address decode width -parameter s0_addr = 1'b1; // slave 0 address - +parameter s0_addr = 1'b0; // slave 0 address + +//address for a 32MB flash from 0x800000ff_f0800000 to 0x800000ff_f0ffffff +//Check address_w +// 32 MB --> 8 MW X32 bits --> 2^23 --> addr_w=64-23=41 parameter s1_addr_w = 41 ; // slave 1 address decode width -parameter s1_addr = {40'h0000000000,1'b0}; // slave 1 address +parameter s1_addr = {40'h800000FFF0,1'b0}; // slave 1 address parameter s2_addr_w = 56 ; -parameter s2_addr = {56'h800000FFF0C2C1}; // slave 2 address +parameter s2_addr = {56'h800000FFF0C2C1}; // slave 2 address parameter s3_addr_w = 60 ; parameter s3_addr = {60'h800000FFF0C2C00}; // slave 3 address parameter s4_addr_w = 37 ; -parameter s4_addr = {36'h800000FFF,1'b1}; // slave 4 address +parameter s4_addr = {36'h800000FFF,1'b1}; // slave 4 address parameter s5_addr_w = 60 ; parameter s5_addr = {60'h400000F00000000}; // slave 5 address Index: /trunk/WB2ALTDDR3/dram_wb.v =================================================================== --- /trunk/WB2ALTDDR3/dram_wb.v (revision 17) +++ /trunk/WB2ALTDDR3/dram_wb.v (revision 22) @@ -22,6 +22,6 @@ module dram_wb( input clk200, - input rup, - input rdn, +// input rup, +// input rdn, input wb_clk_i, @@ -64,7 +64,8 @@ ); +wire app_af_afull; wire [127:0] rd_data_fifo_out; reg [ 23:0] rd_addr_cache; -wire [127:0] wr_dout; +wire [ 71:0] wr_dout; wire [ 31:0] cmd_out; reg wb_stb_i_d; @@ -78,29 +79,36 @@ //wire [13:0] seriesterminationcontrol; -dram dram_ctrl( +dram # + ( + //synthesis traslate off + .SIM_ONLY (1) + //synthesis traslate on + ) + dram_ctrl( .sys_clk(clk200), .sys_rst_n(sysrst), // Resets all .phy_init_done(phy_init_done), + + .app_af_cmd({2'b00,!cmd_out[31]}), //command for the controller 000:write 001:read + .app_af_addr(cmd_out[30:0]), + .app_af_wren(push_tran), //write enable for address fifo + .app_wdf_wren(cmd_out[31] & push_tran), // write enable for write data fifo + .app_wdf_data({wr_dout[63:0],wr_dout[63:0]}), .app_wdf_mask_data(mask_data), - .app_af_addr(cmd_out[31:1]), + .rd_data_valid(rd_data_valid), .rd_data_fifo_out(rd_data_fifo_out), - .app_wdf_data(wr_dout[127:0]), - - // in dubbio - .app_wdf_wren(1'b1), - .app_af_wren(1'b1), - .app_af_afull(), - .app_wdf_afull(), - .app_af_cmd(), - .clk0_tb(), - .idly_clk_200(clk200), - .rst0_tb(ddr3_reset), - - .ddr2_dqs(ddr3_dqs), - .ddr2_dqs_n(ddr3_dqs_n), + + .clk0_tb(ddr_clk), + .rst0_tb(ddr3_reset), + .app_af_afull(app_af_afull), + .app_wdf_afull(), + .idly_clk_200(clk200), + .ddr2_ck(ddr3_ck), .ddr2_ck_n(ddr3_ck_n), .ddr2_dq(ddr3_dq), + .ddr2_dqs(ddr3_dqs), + .ddr2_dqs_n(ddr3_dqs_n), .ddr2_ras_n(ddr3_ras_n), .ddr2_cas_n(ddr3_cas_n), @@ -112,16 +120,7 @@ .ddr2_a(ddr3_a), .ddr2_dm(ddr3_dm) -// | -//non sostituiti\|/ -// V -// .phy_clk(ddr_clk), // User clock -// .local_ready(dram_ready), -// .local_burstbegin(push_tran), -// .local_read_req(!cmd_out[31] && push_tran), -// .local_write_req(cmd_out[31] && push_tran), -// .local_wdata({wr_dout[63:0],wr_dout[63:0],wr_dout[63:0],wr_dout[63:0]}), -// .local_size(3'b001) - ); + +assign dram_ready = phy_init_done && !app_af_afull; /* comment by sal @@ -179,5 +178,5 @@ */ -assign ddr_rst=!phy_init_done; +assign ddr_rst=!phy_init_done; /*oct_alt_oct_power_f4c oct @@ -190,9 +189,7 @@ always @( * ) - case(cmd_out[1:0]) - 2'b00:mask_data<={24'h000000,wr_dout[71:64]}; - 2'b01:mask_data<={16'h0000,wr_dout[71:64],8'h00}; - 2'b10:mask_data<={8'h00,wr_dout[71:64],16'h0000}; - 2'b11:mask_data<={wr_dout[71:64],24'h000000}; + case(cmd_out[0]) + 1'b0:mask_data<={8'h00,wr_dout[71:64]}; + 1'b1:mask_data<={wr_dout[71:64],8'h00}; endcase @@ -304,14 +301,15 @@ always @( * ) - case(wb_adr_i[4:3]) - 2'b00:wb_dat_o<=rd_data_fifo_out_d[63:0]; - 2'b01:wb_dat_o<=rd_data_fifo_out_d[127:64]; - 2'b10:wb_dat_o<=rd_data_fifo_out_d[191:128]; - 2'b11:wb_dat_o<=rd_data_fifo_out_d[255:192]; + case(wb_adr_i[3]) + 1'b0:wb_dat_o<=rd_data_fifo_out_d[63:0]; + 1'b1:wb_dat_o<=rd_data_fifo_out_d[127:64]; endcase always @(posedge wb_clk_i or posedge wb_rst_i) if(wb_rst_i) - rd_addr_cache<=24'hFFFFFF; + begin + //written<=0; + rd_addr_cache<=24'hFFFFFF; + end else begin Index: /trunk/T1-common/srams/bw_r_irf.v =================================================================== --- /trunk/T1-common/srams/bw_r_irf.v (revision 6) +++ /trunk/T1-common/srams/bw_r_irf.v (revision 22) @@ -1185,55 +1185,77 @@ .clk (clk), .q (ifu_exu_ren1_d), - .se (se)); + .se (se), + .si (), + .so ()); dff_s dff_ren2_s2d( .din (ren2_s), .clk (clk), .q (ifu_exu_ren2_d), - .se (se)); + .se (se), + .si (), + .so ()); dff_s dff_ren3_s2d( .din (ren3_s), .clk (clk), .q (ifu_exu_ren3_d), - .se (se)); + .se (se), + .si (), + .so ()); dff_s #(5) dff_rs1_s2d( .din (rs1_s[4:0]), .clk (clk), .q (ifu_exu_rs1_d[4:0]), - .se (se)); + .se (se), + .si (), + .so ()); dff_s #(5) dff_rs2_s2d( .din (rs2_s[4:0]), .clk (clk), .q (ifu_exu_rs2_d[4:0]), - .se (se)); + .se (se), + .si (), + .so ()); dff_s #(5) dff_rs3_s2d( .din (rs3_s[4:0]), .clk (clk), .q (ifu_exu_rs3_d[4:0]), - .se (se)); + .se (se), + .si (), + .so ()); dff_s #(2) dff_thr_s2d( .din (tid_s[1:0]), .clk (clk), .q (ifu_exu_thr_d[1:0]), - .se (se)); + .se (se), + .si (), + .so ()); dff_s #(2) dff_thr_g2w2( .din (tid_g[1:0]), .clk (clk), .q (ecl_irf_tid_w2[1:0]), - .se (se)); + .se (se), + .si (), + .so ()); dff_s #(2) dff_thr_m2w( .din (tid_m[1:0]), .clk (clk), .q (ecl_irf_tid_w[1:0]), - .se (se)); + .se (se), + .si (), + .so ()); dff_s #(5) dff_rd_m2w( .din (rd_m[4:0]), .clk (clk), .q (ecl_irf_rd_w[4:0]), - .se (se)); + .se (se), + .si (), + .so ()); dff_s #(5) dff_rd_g2w2( .din (rd_g[4:0]), .clk (clk), .q (ecl_irf_rd_w2[4:0]), - .se (se)); + .se (se), + .si (), + .so ()); bw_r_irf_core bw_r_irf_core( .clk (clk), Index: /trunk/T1-common/srams/bw_r_icd.v =================================================================== --- /trunk/T1-common/srams/bw_r_icd.v (revision 6) +++ /trunk/T1-common/srams/bw_r_icd.v (revision 22) @@ -191,5 +191,7 @@ .q (wrdata_f), .en ((~sehold)), - .se (se)); + .se (se), + .si (), + .so()); always @(posedge clk) begin