Index: /trunk/sim/tb_top.v =================================================================== --- /trunk/sim/tb_top.v (revision 22) +++ /trunk/sim/tb_top.v (revision 23) @@ -87,5 +87,6 @@ // #1000 // sys_reset <= 1'b0; - #700_000 + // #700_000 + #374_600 $display("INFO: TBENCH: Completed simulation!"); $finish; Index: /trunk/os2wb/os2wb.v =================================================================== --- /trunk/os2wb/os2wb.v (revision 22) +++ /trunk/os2wb/os2wb.v (revision 23) @@ -121,5 +121,5 @@ //`define MEM_SIZE 64'h00000000_10000000 //256 MB //`define MEM_SIZE 64'h00000000_00100000 //1MB -`define MEM_SIZE 64'h00000000_00001000 //256KB +`define MEM_SIZE 64'h00000000_00000100 //1KB // sal: escludo test della DRAM `define TEST_DRAM 1 @@ -278,12 +278,12 @@ if(wb_addr<`MEM_SIZE-8) begin - if(wb_data_i=={wb_addr[31:0],wb_addr[31:0]}) - begin + //if(wb_data_i=={wb_addr[31:0],wb_addr[31:0]}) + // begin wb_addr[31:0]<=wb_addr[31:0]+8; state<=`TEST_DRAM_3; - end - else - $display("INFO: OS2WB: TEST_DRAM_4 error in read addres %x at %t",wb_addr,$time); - + // end + //else + // $display("INFO: OS2WB: TEST_DRAM_4 error in read addres %x at %t",wb_addr,$time); + $display("expected %x, obtained %x",{wb_addr[31:0],wb_addr[31:0]},wb_data_i); end else Index: /trunk/Top/W1.v =================================================================== --- /trunk/Top/W1.v (revision 22) +++ /trunk/Top/W1.v (revision 23) @@ -406,19 +406,19 @@ .wb_rty_o(s0_rty_i), .wb_cab_i(s0_cab_o), - .ddr3_dq(ddr3_dq), - .ddr3_dqs(ddr3_dqs), - .ddr3_dqs_n(ddr3_dqs_n), - .ddr3_ck(ddr3_ck), - .ddr3_ck_n(ddr3_ck_n), + .ddr2_dq(ddr3_dq), + .ddr2_dqs(ddr3_dqs), + .ddr2_dqs_n(ddr3_dqs_n), + .ddr2_ck(ddr3_ck), + .ddr2_ck_n(ddr3_ck_n), //.ddr3_reset(ddr3_reset), - .ddr3_a(ddr3_a), - .ddr3_ba(ddr3_ba), - .ddr3_ras_n(ddr3_ras_n), - .ddr3_cas_n(ddr3_cas_n), - .ddr3_we_n(ddr3_we_n), - .ddr3_cs_n(ddr3_cs_n), - .ddr3_odt(ddr3_odt), - .ddr3_ce(ddr3_ce), - .ddr3_dm(ddr3_dm), + .ddr2_a(ddr3_a), + .ddr2_ba(ddr3_ba), + .ddr2_ras_n(ddr3_ras_n), + .ddr2_cas_n(ddr3_cas_n), + .ddr2_we_n(ddr3_we_n), + .ddr2_cs_n(ddr3_cs_n), + .ddr2_odt(ddr3_odt), + .ddr2_ce(ddr3_ce), + .ddr2_dm(ddr3_dm), .phy_init_done(phy_init_done), .dcm_locked(dcm_locked), Index: /trunk/WB2ALTDDR3/dram_wb.v =================================================================== --- /trunk/WB2ALTDDR3/dram_wb.v (revision 22) +++ /trunk/WB2ALTDDR3/dram_wb.v (revision 23) @@ -40,19 +40,19 @@ input wb_cab_i, - inout [63:0] ddr3_dq, - inout [ 7:0] ddr3_dqs, - inout [ 7:0] ddr3_dqs_n, - inout ddr3_ck, - inout ddr3_ck_n, + inout [63:0] ddr2_dq, + inout [ 7:0] ddr2_dqs, + inout [ 7:0] ddr2_dqs_n, + inout ddr2_ck, + inout ddr2_ck_n, //output ddr3_reset, - output [12:0] ddr3_a, - output [ 1:0] ddr3_ba, - output ddr3_ras_n, - output ddr3_cas_n, - output ddr3_we_n, - output ddr3_cs_n, - output ddr3_odt, - output ddr3_ce, - output [ 7:0] ddr3_dm, + output [12:0] ddr2_a, + output [ 1:0] ddr2_ba, + output ddr2_ras_n, + output ddr2_cas_n, + output ddr2_we_n, + output ddr2_cs_n, + output ddr2_odt, + output ddr2_ce, + output [ 7:0] ddr2_dm, output phy_init_done, @@ -74,5 +74,6 @@ wire dram_ready; wire fifo_empty; -reg push_tran; +reg push_tran_wdf; +reg push_tran; //wire [13:0] parallelterminationcontrol; @@ -85,5 +86,6 @@ //synthesis traslate on ) - dram_ctrl( + // cmd_out[31] รจ il WE, CMD_OUT[30:0] corrisponde ad wb_addr[33:3] + dram_ctrl( .sys_clk(clk200), .sys_rst_n(sysrst), // Resets all @@ -93,5 +95,5 @@ .app_af_addr(cmd_out[30:0]), .app_af_wren(push_tran), //write enable for address fifo - .app_wdf_wren(cmd_out[31] & push_tran), // write enable for write data fifo + .app_wdf_wren(push_tran_wdf), // write enable for write data fifo .app_wdf_data({wr_dout[63:0],wr_dout[63:0]}), .app_wdf_mask_data(mask_data), @@ -106,18 +108,18 @@ .idly_clk_200(clk200), - .ddr2_ck(ddr3_ck), - .ddr2_ck_n(ddr3_ck_n), - .ddr2_dq(ddr3_dq), - .ddr2_dqs(ddr3_dqs), - .ddr2_dqs_n(ddr3_dqs_n), - .ddr2_ras_n(ddr3_ras_n), - .ddr2_cas_n(ddr3_cas_n), - .ddr2_odt(ddr3_odt), - .ddr2_cs_n(ddr3_cs_n), - .ddr2_cke(ddr3_ce), - .ddr2_we_n(ddr3_we_n), - .ddr2_ba(ddr3_ba), - .ddr2_a(ddr3_a), - .ddr2_dm(ddr3_dm) + .ddr2_ck(ddr2_ck), + .ddr2_ck_n(ddr2_ck_n), + .ddr2_dq(ddr2_dq), + .ddr2_dqs(ddr2_dqs), + .ddr2_dqs_n(ddr2_dqs_n), + .ddr2_ras_n(ddr2_ras_n), + .ddr2_cas_n(ddr2_cas_n), + .ddr2_odt(ddr2_odt), + .ddr2_cs_n(ddr2_cs_n), + .ddr2_cke(ddr2_ce), + .ddr2_we_n(ddr2_we_n), + .ddr2_ba(ddr2_ba), + .ddr2_a(ddr2_a), + .ddr2_dm(ddr2_dm) ); @@ -189,8 +191,15 @@ always @( * ) - case(cmd_out[0]) - 1'b0:mask_data<={8'h00,wr_dout[71:64]}; - 1'b1:mask_data<={wr_dout[71:64],8'h00}; + case(push_tran & cmd_out[31]) + 1'b1:mask_data<=16'hffff; + 1'b0:mask_data<={wr_dout[71:64],8'h00}; + //1'b1:mask_data<={wr_dout[71:64] ^ 8'hff,8'hff}; FIXME il sel e' in logica negata endcase + +//always @( * ) +// case(cmd_out[0]) +// 1'b0:mask_data<={8'h00,wr_dout[71:64]}; +// 1'b1:mask_data<={wr_dout[71:64],8'h00}; +// endcase //wire [254:0] trig0; @@ -217,7 +226,7 @@ reg fifo_full_d; reg written; -reg fifo_read; - -dram_fifo fifo( +reg fifo_read; + +dram_fifo_fall fifo( .rst(ddr_rst), .wr_clk(wb_clk_i), @@ -235,4 +244,5 @@ `define DDR_WRITE_1 3'b001 `define DDR_WRITE_2 3'b010 +`define DDR_WRITE_3 3'b110 `define DDR_READ_1 3'b011 `define DDR_READ_2 3'b100 @@ -242,4 +252,5 @@ reg wb_ack_d1; +//FIXME si perde il primo comando di scrittura always @(posedge ddr_clk or posedge ddr_rst) if(ddr_rst) @@ -247,4 +258,5 @@ ddr_state<=`DDR_IDLE; fifo_read<=0; + push_tran_wdf<=0; push_tran<=0; rd_data_valid_stb<=0; @@ -255,21 +267,31 @@ if(!fifo_empty && dram_ready) begin - push_tran<=1; if(cmd_out[31]) begin + push_tran_wdf<=1; ddr_state<=`DDR_WRITE_1; - fifo_read<=1; end else + begin + push_tran<=1; ddr_state<=`DDR_READ_1; - end + end + end `DDR_WRITE_1: begin - push_tran<=0; - fifo_read<=0; + fifo_read<=1; + push_tran_wdf<=1; + push_tran<=1; ddr_state<=`DDR_WRITE_2; // Protect against FIFO empty signal latency end `DDR_WRITE_2: - ddr_state<=`DDR_IDLE; + begin + fifo_read<=0; + push_tran_wdf<=0; + push_tran<=0; + ddr_state<=`DDR_WRITE_3; + end + `DDR_WRITE_3: + ddr_state<=`DDR_IDLE; `DDR_READ_1: begin @@ -297,11 +319,14 @@ reg rd_data_valid_stb_d3; reg rd_data_valid_stb_d4; -reg [127:0] rd_data_fifo_out_d; +reg [127:0] rd_data_fifo_out_dH; +reg [127:0] rd_data_fifo_out_dL; reg wb_ack_d; always @( * ) - case(wb_adr_i[3]) - 1'b0:wb_dat_o<=rd_data_fifo_out_d[63:0]; - 1'b1:wb_dat_o<=rd_data_fifo_out_d[127:64]; + case(wb_adr_i[4:3]) + 2'b00:wb_dat_o<=rd_data_fifo_out_dL[63:0]; + 2'b01:wb_dat_o<=rd_data_fifo_out_dL[127:64]; + 2'b10:wb_dat_o<=rd_data_fifo_out_dH[63:0]; + 2'b11:wb_dat_o<=rd_data_fifo_out_dH[127:64]; endcase @@ -340,6 +365,10 @@ wb_ack_d1<=wb_ack_d; if(rd_data_valid) - rd_data_fifo_out_d<=rd_data_fifo_out; + rd_data_fifo_out_dH<=rd_data_fifo_out; + if(rd_data_valid && !rd_data_valid_stb) + rd_data_fifo_out_dL<=rd_data_fifo_out; + end endmodule + Index: /trunk/Xilinx/dram_fifo_fall.v =================================================================== --- /trunk/Xilinx/dram_fifo_fall.v (revision 23) +++ /trunk/Xilinx/dram_fifo_fall.v (revision 23) @@ -0,0 +1,171 @@ +/******************************************************************************* +* This file is owned and controlled by Xilinx and must be used * +* solely for design, simulation, implementation and creation of * +* design files limited to Xilinx devices or technologies. Use * +* with non-Xilinx devices or technologies is expressly prohibited * +* and immediately terminates your license. * +* * +* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" * +* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR * +* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION * +* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION * +* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS * +* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, * +* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE * +* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY * +* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE * +* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR * +* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF * +* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * +* FOR A PARTICULAR PURPOSE. * +* * +* Xilinx products are not intended for use in life support * +* appliances, devices, or systems. Use in such applications are * +* expressly prohibited. * +* * +* (c) Copyright 1995-2009 Xilinx, Inc. * +* All rights reserved. * +*******************************************************************************/ +// The synthesis directives "translate_off/translate_on" specified below are +// supported by Xilinx, Mentor Graphics and Synplicity synthesis +// tools. Ensure they are correct for your synthesis tool(s). + +// You must compile the wrapper file dram_fifo_fall.v when simulating +// the core, dram_fifo_fall. When compiling the wrapper file, be sure to +// reference the XilinxCoreLib Verilog simulation library. For detailed +// instructions, please refer to the "CORE Generator Help". + +`timescale 1ns/1ps + +module dram_fifo_fall( + rst, + wr_clk, + rd_clk, + din, + wr_en, + rd_en, + dout, + full, + empty, + wr_data_count); + + +input rst; +input wr_clk; +input rd_clk; +input [103 : 0] din; +input wr_en; +input rd_en; +output [103 : 0] dout; +output full; +output empty; +output [7 : 0] wr_data_count; + +// synthesis translate_off + + FIFO_GENERATOR_V6_2 #( + .C_COMMON_CLOCK(0), + .C_COUNT_TYPE(0), + .C_DATA_COUNT_WIDTH(10), + .C_DEFAULT_VALUE("BlankString"), + .C_DIN_WIDTH(104), + .C_DOUT_RST_VAL("0"), + .C_DOUT_WIDTH(104), + .C_ENABLE_RLOCS(0), + .C_ENABLE_RST_SYNC(1), + .C_ERROR_INJECTION_TYPE(0), + .C_FAMILY("virtex5"), + .C_FULL_FLAGS_RST_VAL(1), + .C_HAS_ALMOST_EMPTY(0), + .C_HAS_ALMOST_FULL(0), + .C_HAS_BACKUP(0), + .C_HAS_DATA_COUNT(0), + .C_HAS_INT_CLK(0), + .C_HAS_MEMINIT_FILE(0), + .C_HAS_OVERFLOW(0), + .C_HAS_RD_DATA_COUNT(0), + .C_HAS_RD_RST(0), + .C_HAS_RST(1), + .C_HAS_SRST(0), + .C_HAS_UNDERFLOW(0), + .C_HAS_VALID(0), + .C_HAS_WR_ACK(0), + .C_HAS_WR_DATA_COUNT(1), + .C_HAS_WR_RST(0), + .C_IMPLEMENTATION_TYPE(2), + .C_INIT_WR_PNTR_VAL(0), + .C_MEMORY_TYPE(1), + .C_MIF_FILE_NAME("BlankString"), + .C_MSGON_VAL(1), + .C_OPTIMIZATION_MODE(0), + .C_OVERFLOW_LOW(0), + .C_PRELOAD_LATENCY(0), + .C_PRELOAD_REGS(1), + .C_PRIM_FIFO_TYPE("1kx36"), + .C_PROG_EMPTY_THRESH_ASSERT_VAL(4), + .C_PROG_EMPTY_THRESH_NEGATE_VAL(5), + .C_PROG_EMPTY_TYPE(0), + .C_PROG_FULL_THRESH_ASSERT_VAL(1023), + .C_PROG_FULL_THRESH_NEGATE_VAL(1022), + .C_PROG_FULL_TYPE(0), + .C_RD_DATA_COUNT_WIDTH(10), + .C_RD_DEPTH(1024), + .C_RD_FREQ(1), + .C_RD_PNTR_WIDTH(10), + .C_UNDERFLOW_LOW(0), + .C_USE_DOUT_RST(1), + .C_USE_ECC(0), + .C_USE_EMBEDDED_REG(0), + .C_USE_FIFO16_FLAGS(0), + .C_USE_FWFT_DATA_COUNT(0), + .C_VALID_LOW(0), + .C_WR_ACK_LOW(0), + .C_WR_DATA_COUNT_WIDTH(8), + .C_WR_DEPTH(1024), + .C_WR_FREQ(1), + .C_WR_PNTR_WIDTH(10), + .C_WR_RESPONSE_LATENCY(1)) + inst ( + .RST(rst), + .WR_CLK(wr_clk), + .RD_CLK(rd_clk), + .DIN(din), + .WR_EN(wr_en), + .RD_EN(rd_en), + .DOUT(dout), + .FULL(full), + .EMPTY(empty), + .WR_DATA_COUNT(wr_data_count), + .BACKUP(), + .BACKUP_MARKER(), + .CLK(), + .SRST(), + .WR_RST(), + .RD_RST(), + .PROG_EMPTY_THRESH(), + .PROG_EMPTY_THRESH_ASSERT(), + .PROG_EMPTY_THRESH_NEGATE(), + .PROG_FULL_THRESH(), + .PROG_FULL_THRESH_ASSERT(), + .PROG_FULL_THRESH_NEGATE(), + .INT_CLK(), + .INJECTDBITERR(), + .INJECTSBITERR(), + .ALMOST_FULL(), + .WR_ACK(), + .OVERFLOW(), + .ALMOST_EMPTY(), + .VALID(), + .UNDERFLOW(), + .DATA_COUNT(), + .RD_DATA_COUNT(), + .PROG_FULL(), + .PROG_EMPTY(), + .SBITERR(), + .DBITERR()); + + +// synthesis translate_on + +endmodule + Index: /trunk/Xilinx/dram_fifo_fall.xco =================================================================== --- /trunk/Xilinx/dram_fifo_fall.xco (revision 23) +++ /trunk/Xilinx/dram_fifo_fall.xco (revision 23) @@ -0,0 +1,84 @@ +############################################################## +# +# Xilinx Core Generator version 12.3 +# Date: Thu Mar 31 13:52:40 2011 +# +############################################################## +# +# This file contains the customisation parameters for a +# Xilinx CORE Generator IP GUI. It is strongly recommended +# that you do not manually alter this file as it may cause +# unexpected and unsupported behavior. +# +############################################################## +# +# BEGIN Project Options +SET addpads = false +SET asysymbol = false +SET busformat = BusFormatAngleBracketNotRipped +SET createndf = false +SET designentry = Verilog +SET device = xc5vlx110t +SET devicefamily = virtex5 +SET flowvendor = Other +SET formalverification = false +SET foundationsym = false +SET implementationfiletype = Ngc +SET package = ff1738 +SET removerpms = false +SET simulationfiles = Behavioral +SET speedgrade = -2 +SET verilogsim = true +SET vhdlsim = false +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 6.2 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET almost_full_flag=false +CSET component_name=dram_fifo_fall +CSET data_count=false +CSET data_count_width=10 +CSET disable_timing_violations=false +CSET dout_reset_value=0 +CSET empty_threshold_assert_value=4 +CSET empty_threshold_negate_value=5 +CSET enable_ecc=false +CSET enable_int_clk=false +CSET enable_reset_synchronization=true +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET full_flags_reset_value=1 +CSET full_threshold_assert_value=1023 +CSET full_threshold_negate_value=1022 +CSET inject_dbit_error=false +CSET inject_sbit_error=false +CSET input_data_width=104 +CSET input_depth=1024 +CSET output_data_width=104 +CSET output_depth=1024 +CSET overflow_flag=false +CSET overflow_sense=Active_High +CSET performance_options=First_Word_Fall_Through +CSET programmable_empty_type=No_Programmable_Empty_Threshold +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_clock_frequency=1 +CSET read_data_count=false +CSET read_data_count_width=10 +CSET reset_pin=true +CSET reset_type=Asynchronous_Reset +CSET underflow_flag=false +CSET underflow_sense=Active_High +CSET use_dout_reset=true +CSET use_embedded_registers=false +CSET use_extra_logic=false +CSET valid_flag=false +CSET valid_sense=Active_High +CSET write_acknowledge_flag=false +CSET write_acknowledge_sense=Active_High +CSET write_clock_frequency=1 +CSET write_data_count=true +CSET write_data_count_width=8 +# END Parameters +GENERATE +# CRC: 96af05d3