Index: trunk/os2wb/os2wb.v
===================================================================
--- trunk/os2wb/os2wb.v	(revision 23)
+++ trunk/os2wb/os2wb.v	(revision 26)
@@ -24,7 +24,8 @@
     
     // Core interface 
-    input      [  4:0] pcx_req,
+    input      [  4:0] pcx_req, 
     input              pcx_atom,
-    input      [123:0] pcx_data,
+    input      [123:0] pcx_data, 
+    
     output reg [  4:0] pcx_grant,
     output reg         cpx_ready,
@@ -235,5 +236,5 @@
          `TEST_DRAM_1:
             begin
-               $display("INFO: OS2WB: TEST_DRAM_1");
+               //$display("INFO: OS2WB: TEST_DRAM_1");
                wb_cycle<=1;
                wb_strobe<=1;
@@ -245,5 +246,5 @@
             if(wb_ack)
                begin
-               $display("INFO: OS2WB: TEST_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr);
+               //$display("INFO: OS2WB: TEST_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr);
                   wb_strobe<=0;
                   if(wb_addr<`MEM_SIZE-8)
@@ -265,5 +266,5 @@
          `TEST_DRAM_3:
             begin
-               $display("INFO: OS2WB: TEST_DRAM_3");
+               //$display("INFO: OS2WB: TEST_DRAM_3");
                wb_cycle<=1;
                wb_strobe<=1;
@@ -274,5 +275,5 @@
             if(wb_ack)
                begin
-                  $display("INFO: OS2WB: TEST_DRAM_4 at %t",$time);
+                 // $display("INFO: OS2WB: TEST_DRAM_4 at %t",$time);
                   wb_strobe<=0;
                   if(wb_addr<`MEM_SIZE-8)
@@ -284,10 +285,9 @@
                         //   end
 			//else 
-			//      $display("INFO: OS2WB: TEST_DRAM_4 error in read addres %x at %t",wb_addr,$time);
-			      $display("expected %x, obtained  %x",{wb_addr[31:0],wb_addr[31:0]},wb_data_i);
+			//   $display("expected %x, obtained  %x",{wb_addr[31:0],wb_addr[31:0]},wb_data_i);
                      end
                   else
                      begin
-                        $display("INFO: OS2WB: INIT_DRAM at %t",$time);
+                        //$display("INFO: OS2WB: INIT_DRAM at %t",$time);
                         state<=`INIT_DRAM_1;
                         wb_cycle<=0;
@@ -323,5 +323,5 @@
                   else
                      begin
-                        $display("INFO: OS2WB: WAKEUP_DRAM at %t",$time);
+                        //$display("INFO: OS2WB: WAKEUP_DRAM at %t",$time);
                         state<=`WAKEUP;
                         wb_cycle<=0;
@@ -393,4 +393,5 @@
          `PCX_REQ_2ND:
             begin
+               $display("INFO: OS2WB: GOT_PCX_REQ_2ND");
                pcx_packet_2nd<=pcx_packet; //Latch second packet for atomics
                if(`DEBUGGING)
@@ -407,4 +408,5 @@
                if(pcx_packet_d[111]==1'b1) // Invalidate request
                   begin
+                     $display("INFO: OS2WB: INVALIDATE");
                      cpx_packet_1[144]<=1;     // Valid
                      cpx_packet_1[143:140]<=4'b0100; // Invalidate reply is Store ACK
@@ -423,12 +425,19 @@
                   if(pcx_packet_d[122:118]!=5'b01001) // Not INT
                      begin
+                        $display("INFO: OS2WB: PCX_REQ_STEP1");
                         wb_cycle<=1'b1;
                         wb_strobe<=1'b1;
                         if((pcx_packet_d[122:118]==5'b00000 && !pcx_req_d[4]) || pcx_packet_d[122:118]==5'b00010 || pcx_packet_d[122:118]==5'b00100 || pcx_packet_d[122:118]==5'b00110)
+                           begin 
+			    $display("INFO: OS2WB: load/streadload ecc");
                            wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+4],4'b0000}; //DRAM load/streamload, CAS and SWAP always use DRAM and load first 
-                        else
+                           end 
+			else
                            if(pcx_packet_d[122:118]==5'b10000 && !pcx_req_d[4])
+                           begin
+			      $display("INFO: OS2WB: ifill");
                               wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+5],5'b00000}; //DRAM ifill
-                           else
+                           end
+			   else
                               if(pcx_packet_d[64+39:64+28]==12'hFFF && pcx_packet_d[64+27:64+24]!=4'b0) // flash remap FFF1->FFF8
                                  wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+3]+37'h0000E00000,3'b000};
@@ -446,4 +455,5 @@
                   5'b00000://Load
                      begin
+                        $display("INFO: OS2WB: PCX_REQ_STEP1, Load");
                         wb_we<=0;
                         if(!pcx_packet_d[110] && !pcx_packet_d[117])
@@ -492,4 +502,5 @@
                   5'b00001://Store
                      begin
+                        $display("INFO: OS2WB: PCX_REQ_STEP1, Store");
                         wb_we<=1;
                         case({icache_hit,dcache0_hit})
@@ -538,4 +549,5 @@
                   5'b00010://CAS
                      begin
+                        $display("INFO: OS2WB: PCX_REQ_STEP1, CAS");
                         wb_we<=0; //Load first
                         case({icache_hit,dcache0_hit})
@@ -555,4 +567,5 @@
                   5'b00100://STRLOAD
                      begin
+                        $display("INFO: OS2WB: PCX_REQ_STEP1, STRLOAD");
                         wb_we<=0;
                         wb_sel<=8'b11111111; // Stream loads are always 128 bit
@@ -560,4 +573,5 @@
                   5'b00101://STRSTORE
                      begin
+                        $display("INFO: OS2WB: PCX_REQ_STEP1, STRSTORE");
                         wb_we<=1;
                         case({icache_hit,dcache0_hit})
@@ -606,4 +620,5 @@
                   5'b00110://SWAP/LDSTUB
                      begin
+                        $display("INFO: OS2WB: PCX_REQ_STEP1, SWAP/LDSTUB");
                         case({icache_hit,dcache0_hit})
                            8'b00000000:;
@@ -622,14 +637,18 @@
                      end
                   5'b01001://INT
-                     if(pcx_packet_d[117]) // Flush
+                     begin
+                        $display("INFO: OS2WB: PCX_REQ_STEP1, INT");
+			if(pcx_packet_d[117]) // Flush
                         cpx_packet_1<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],3'b0,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer
-                     else // Tread-to-thread interrupt
+			else // Tread-to-thread interrupt
                         cpx_packet_1<={9'h170,pcx_packet_d[113:112],52'h0,pcx_packet_d[17:0],46'h0,pcx_packet_d[17:0]}; 
-                  //5'b01010: FP1 - processed by separate state
-                  //5'b01011: FP2 - processed by separate state
-                  //5'b01101: FWDREQ - not implemented
-                  //5'b01110: FWDREPL - not implemented
-                  5'b10000://IFILL
-                     begin
+				//5'b01010: FP1 - processed by separate state
+				//5'b01011: FP2 - processed by separate state
+				//5'b01101: FWDREQ - not implemented
+				//5'b01110: FWDREPL - not implemented
+                     end
+		  5'b10000://IFILL
+                     begin
+                        $display("INFO: OS2WB: PCX_REQ_STEP1, IFILL");
                         wb_we<=0;
                         if(!pcx_req_d[4]) // not I/O access
@@ -668,6 +687,7 @@
                if(wb_ack)
                   begin
+                     $display("INFO: OS2WB: PCX_REQ_STEP1_1 wb_addr = %x",wb_addr);
                      cpx_packet_1[144]<=1;     // Valid
-                     cpx_packet_1[139]<=(pcx_packet_d[122:118]==5'b00000) || (pcx_packet_d[122:118]==5'b10000) ? 1:0;     // L2 always miss on load and ifill
+                     cpx_packet_1[139]<=(pcx_packet_d[122:118]==5'b00000) || (pcx_packet_d[122:118]==5'b10000) ? 1:0; // L2 always miss on load and ifill
                      cpx_packet_1[138:137]<=0; // Error
                      cpx_packet_1[136]<=pcx_packet_d[117] || (pcx_packet_d[122:118]==5'b00001) ? 1:0; // Non-cacheble is set on store too
@@ -821,4 +841,6 @@
                         5'b10000://IFILL
                            begin
+                              $display("INFO: OS2WB: PCX_REQ_STEP1_1, IFILL, wb_addr = %x wb_data_i= %x",wb_addr, wb_data_i);
+                              $display("INFO: OS2WB: PCX_REQ_STEP1_1, IFILL, cpx_packet_1 = %x %x",wb_data_i,wb_data_i);
                               cpx_packet_1[143:140]<=4'b0001; // Type
                               cpx_packet_2[143:140]<=4'b0001; // Type
@@ -1073,4 +1095,5 @@
          `CPX_READY_1:
             begin
+               $display("INFO: OS2WB: CPX_READY_1");
                cpx_ready<=1;
                cpx_packet<=cpx_packet_1;
@@ -1087,4 +1110,5 @@
          `CPX_READY_2:
             begin
+               $display("INFO: OS2WB: CPX_READY_2");
                cpx_ready<=1;
                cpx_packet<=cpx_packet_2;
@@ -1093,4 +1117,5 @@
          `PCX_UNKNOWN:
             begin
+               $display("INFO: OS2WB: PCX_UNKNOWN");
                wb_sel<=8'b10100101; // Illegal eye-catching value for debugging
                state<=`PCX_IDLE;
@@ -1250,10 +1275,10 @@
    .enable(dir_en),
    .wren_a(icache0_alloc || icache0_dealloc || icache_inval_all || cache_init),
-   .address_a({2'b0,icache_index}),
+   .address_a({2'b00,icache_index}),
    .data_a(icache_data),
    .q_a(icache0_do),
    
    .wren_b(icache1_alloc || icache1_dealloc || icache_inval_all || cache_init),
-   .address_b({2'b0,icache_index}),
+   .address_b({2'b01,icache_index}),
    .data_b(icache_data),
    .q_b(icache1_do) 
@@ -1264,10 +1289,10 @@
    .enable(dir_en),
    .wren_a(icache2_alloc || icache2_dealloc || icache_inval_all || cache_init),
-   .address_a({2'b0,icache_index}),
+   .address_a({2'b00,icache_index}),
    .data_a(icache_data),
    .q_a(icache2_do),
    
    .wren_b(icache3_alloc || icache3_dealloc || icache_inval_all || cache_init),
-   .address_b({2'b0,icache_index}),
+   .address_b({2'b01,icache_index}),
    .data_b(icache_data),
    .q_b(icache3_do)