Index: /trunk/sim/flash.v =================================================================== --- /trunk/sim/flash.v (revision 21) +++ /trunk/sim/flash.v (revision 26) @@ -42,17 +42,22 @@ $readmemh(memfilename, mem); $display("INFO: MEMH %m: Memory initialization completed"); + //for(i=0; i<=1023; i=i+1) $display("mem_i = %x",mem[i]) ; end `endif assign flash_data = !flash_oen ? data :16'hzzzz; - always @(posedge flash_clk) begin // Read cycle if (!flash_oen & flash_wen) - data <= mem[flash_addr]; + begin + //$display("INFO: flash: read from address %x data %x",flash_addr, mem[flash_addr]); + data <= mem[flash_addr]; + end else // Write cycle - if (flash_oen & !flash_wen) mem[flash_addr] <= flash_data; -end + if (flash_oen & !flash_wen) + $display("INFO: flash: write to address %x data %x (now disabled)",flash_addr,flash_data); + //mem[flash_addr] <= flash_data; FIXME: errouneous spourious writes in flash + end endmodule Index: /trunk/sim/simula.do =================================================================== --- /trunk/sim/simula.do (revision 22) +++ /trunk/sim/simula.do (revision 26) @@ -1,4 +1,7 @@ #start with: vsim -c -do simula.do +set DEFINE +define+DEBUG+FPGA_SYN +#+FPGA_NEW_IRF +set INCLUDEDIR +incdir+../T1-common/include/ vlib work @@ -7,24 +10,24 @@ #Compile all modules# -vlog +incdir+../T1-common/include/ ../T1-common/common/*.v -vlog +incdir+../T1-common/include/ ../Top/*.v -vlog +incdir+../OC-UART +incdir+../T1-common/include/ ../OC-UART/*.v -vlog +incdir+../T1-common/include/ ../NOR-flash/*.v -vlog +incdir+../T1-common/include/ ../os2wb/*.v -vlog +incdir+../T1-common/include/ ../T1-common/m1/*.V -vlog +define+FPGA_SYN +incdir+../T1-common/include/ ../T1-common/srams/*.v -vlog +incdir+../T1-common/include/ ../T1-common/u1/*.V -vlog +incdir+../T1-common/include/ ../T1-FPU/*.v -vlog +incdir+../T1-common/include/ +incdir+../WB ../WB/*.v -vlog +incdir+../T1-common/include/ ../WB2ALTDDR3/*.v -vlog +incdir+../T1-common/include/ ../Xilinx/*.v -vlog +incdir+../T1-common/include/ ../T1-CPU/exu/*.v -vlog +incdir+../T1-common/include/ ../T1-CPU/ffu/*.v -vlog +incdir+../T1-common/include/ ../T1-CPU/ifu/*.v -vlog +incdir+../T1-common/include/ ../T1-CPU/lsu/*.v -vlog +incdir+../T1-common/include/ ../T1-CPU/mul/*.v -vlog +incdir+../T1-common/include/ ../T1-CPU/rtl/*.v -vlog +incdir+../T1-common/include/ ../T1-CPU/spu/*.v -vlog +incdir+../T1-common/include/ ../T1-CPU/tlu/*.v +vlog $DEFINE $INCLUDEDIR ../T1-common/common/*.v +vlog $DEFINE $INCLUDEDIR ../Top/*.v +vlog $DEFINE +incdir+../OC-UART $INCLUDEDIR ../OC-UART/*.v +vlog $DEFINE $INCLUDEDIR ../NOR-flash/*.v +vlog $DEFINE $INCLUDEDIR ../os2wb/*.v +vlog $DEFINE $INCLUDEDIR ../T1-common/m1/*.V +vlog $DEFINE $INCLUDEDIR ../T1-common/srams/*.v +vlog $DEFINE $INCLUDEDIR ../T1-common/u1/*.V +vlog $DEFINE $INCLUDEDIR/ ../T1-FPU/*.v +vlog $DEFINE $INCLUDEDIR +incdir+../WB ../WB/*.v +vlog $DEFINE $INCLUDEDIR ../WB2ALTDDR3/*.v +vlog $DEFINE $INCLUDEDIR ../Xilinx/*.v +vlog $DEFINE $INCLUDEDIR ../T1-CPU/exu/*.v +vlog $DEFINE $INCLUDEDIR ../T1-CPU/ffu/*.v +vlog $DEFINE $INCLUDEDIR ../T1-CPU/ifu/*.v +vlog $DEFINE $INCLUDEDIR ../T1-CPU/lsu/*.v +vlog $DEFINE $INCLUDEDIR ../T1-CPU/mul/*.v +vlog $DEFINE $INCLUDEDIR ../T1-CPU/rtl/*.v +vlog $DEFINE $INCLUDEDIR ../T1-CPU/spu/*.v +vlog $DEFINE $INCLUDEDIR ../T1-CPU/tlu/*.v #Compile files in sim folder (excluding model parameter file)# Index: /trunk/sw/hello.c =================================================================== --- /trunk/sw/hello.c (revision 20) +++ /trunk/sw/hello.c (revision 26) @@ -2,4 +2,5 @@ int main() { + asm("mov 0x00, %fp \n"); register unsigned long* address; address = (unsigned long*)0x0000CAC0; Index: /trunk/sw/hello.dump =================================================================== --- /trunk/sw/hello.dump (revision 19) +++ /trunk/sw/hello.dump (revision 26) @@ -6,22 +6,18 @@ 0000000000000000
: - 0: 9d e3 bf 40 save %sp, -192, %sp - 4: 82 10 23 2b mov 0x32b, %g1 - 8: 83 28 70 06 sllx %g1, 6, %g1 - c: c2 77 a7 f7 stx %g1, [ %fp + 0x7f7 ] - 10: c2 5f a7 f7 ldx [ %fp + 0x7f7 ], %g1 - 14: 05 30 68 30 sethi %hi(0xc1a0c000), %g2 - 18: 84 10 a1 a0 or %g2, 0x1a0, %g2 ! c1a0c1a0 - 1c: c4 70 40 00 stx %g2, [ %g1 ] - 20: 82 10 23 2b mov 0x32b, %g1 - 24: 83 28 70 06 sllx %g1, 6, %g1 - 28: c2 77 a7 f7 stx %g1, [ %fp + 0x7f7 ] - 2c: c2 5f a7 f7 ldx [ %fp + 0x7f7 ], %g1 - 30: 05 3e ae 84 sethi %hi(0xfaba1000), %g2 - 34: 84 10 a2 10 or %g2, 0x210, %g2 ! faba1210 - 38: c4 70 40 00 stx %g2, [ %g1 ] - 3c: 82 10 20 00 clr %g1 - 40: 83 38 60 00 sra %g1, 0, %g1 - 44: b0 10 00 01 mov %g1, %i0 - 48: 81 cf e0 08 rett %i7 + 8 - 4c: 01 00 00 00 nop + 4: bc 10 20 00 clr %fp + 8: 82 10 23 2b mov 0x32b, %g1 + c: a1 28 70 06 sllx %g1, 6, %l0 + 10: 03 30 68 30 sethi %hi(0xc1a0c000), %g1 + 14: 82 10 61 a0 or %g1, 0x1a0, %g1 ! c1a0c1a0 + 18: c2 74 00 00 stx %g1, [ %l0 ] + 1c: 82 10 23 2b mov 0x32b, %g1 + 20: a1 28 70 06 sllx %g1, 6, %l0 + 24: 03 3e ae 84 sethi %hi(0xfaba1000), %g1 + 28: 82 10 62 10 or %g1, 0x210, %g1 ! faba1210 + 2c: c2 74 00 00 stx %g1, [ %l0 ] + 30: 82 10 20 00 clr %g1 + 34: 83 38 60 00 sra %g1, 0, %g1 + 38: b0 10 00 01 mov %g1, %i0 + 3c: 81 cf e0 08 rett %i7 + 8 + 40: 01 00 00 00 nop Index: /trunk/os2wb/os2wb.v =================================================================== --- /trunk/os2wb/os2wb.v (revision 23) +++ /trunk/os2wb/os2wb.v (revision 26) @@ -24,7 +24,8 @@ // Core interface - input [ 4:0] pcx_req, + input [ 4:0] pcx_req, input pcx_atom, - input [123:0] pcx_data, + input [123:0] pcx_data, + output reg [ 4:0] pcx_grant, output reg cpx_ready, @@ -235,5 +236,5 @@ `TEST_DRAM_1: begin - $display("INFO: OS2WB: TEST_DRAM_1"); + //$display("INFO: OS2WB: TEST_DRAM_1"); wb_cycle<=1; wb_strobe<=1; @@ -245,5 +246,5 @@ if(wb_ack) begin - $display("INFO: OS2WB: TEST_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr); + //$display("INFO: OS2WB: TEST_DRAM_2 at time %d with wb_addr=%x",$time,wb_addr); wb_strobe<=0; if(wb_addr<`MEM_SIZE-8) @@ -265,5 +266,5 @@ `TEST_DRAM_3: begin - $display("INFO: OS2WB: TEST_DRAM_3"); + //$display("INFO: OS2WB: TEST_DRAM_3"); wb_cycle<=1; wb_strobe<=1; @@ -274,5 +275,5 @@ if(wb_ack) begin - $display("INFO: OS2WB: TEST_DRAM_4 at %t",$time); + // $display("INFO: OS2WB: TEST_DRAM_4 at %t",$time); wb_strobe<=0; if(wb_addr<`MEM_SIZE-8) @@ -284,10 +285,9 @@ // end //else - // $display("INFO: OS2WB: TEST_DRAM_4 error in read addres %x at %t",wb_addr,$time); - $display("expected %x, obtained %x",{wb_addr[31:0],wb_addr[31:0]},wb_data_i); + // $display("expected %x, obtained %x",{wb_addr[31:0],wb_addr[31:0]},wb_data_i); end else begin - $display("INFO: OS2WB: INIT_DRAM at %t",$time); + //$display("INFO: OS2WB: INIT_DRAM at %t",$time); state<=`INIT_DRAM_1; wb_cycle<=0; @@ -323,5 +323,5 @@ else begin - $display("INFO: OS2WB: WAKEUP_DRAM at %t",$time); + //$display("INFO: OS2WB: WAKEUP_DRAM at %t",$time); state<=`WAKEUP; wb_cycle<=0; @@ -393,4 +393,5 @@ `PCX_REQ_2ND: begin + $display("INFO: OS2WB: GOT_PCX_REQ_2ND"); pcx_packet_2nd<=pcx_packet; //Latch second packet for atomics if(`DEBUGGING) @@ -407,4 +408,5 @@ if(pcx_packet_d[111]==1'b1) // Invalidate request begin + $display("INFO: OS2WB: INVALIDATE"); cpx_packet_1[144]<=1; // Valid cpx_packet_1[143:140]<=4'b0100; // Invalidate reply is Store ACK @@ -423,12 +425,19 @@ if(pcx_packet_d[122:118]!=5'b01001) // Not INT begin + $display("INFO: OS2WB: PCX_REQ_STEP1"); wb_cycle<=1'b1; wb_strobe<=1'b1; if((pcx_packet_d[122:118]==5'b00000 && !pcx_req_d[4]) || pcx_packet_d[122:118]==5'b00010 || pcx_packet_d[122:118]==5'b00100 || pcx_packet_d[122:118]==5'b00110) + begin + $display("INFO: OS2WB: load/streadload ecc"); wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+4],4'b0000}; //DRAM load/streamload, CAS and SWAP always use DRAM and load first - else + end + else if(pcx_packet_d[122:118]==5'b10000 && !pcx_req_d[4]) + begin + $display("INFO: OS2WB: ifill"); wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+5],5'b00000}; //DRAM ifill - else + end + else if(pcx_packet_d[64+39:64+28]==12'hFFF && pcx_packet_d[64+27:64+24]!=4'b0) // flash remap FFF1->FFF8 wb_addr<={pcx_req_d,19'b0,pcx_packet_d[103:64+3]+37'h0000E00000,3'b000}; @@ -446,4 +455,5 @@ 5'b00000://Load begin + $display("INFO: OS2WB: PCX_REQ_STEP1, Load"); wb_we<=0; if(!pcx_packet_d[110] && !pcx_packet_d[117]) @@ -492,4 +502,5 @@ 5'b00001://Store begin + $display("INFO: OS2WB: PCX_REQ_STEP1, Store"); wb_we<=1; case({icache_hit,dcache0_hit}) @@ -538,4 +549,5 @@ 5'b00010://CAS begin + $display("INFO: OS2WB: PCX_REQ_STEP1, CAS"); wb_we<=0; //Load first case({icache_hit,dcache0_hit}) @@ -555,4 +567,5 @@ 5'b00100://STRLOAD begin + $display("INFO: OS2WB: PCX_REQ_STEP1, STRLOAD"); wb_we<=0; wb_sel<=8'b11111111; // Stream loads are always 128 bit @@ -560,4 +573,5 @@ 5'b00101://STRSTORE begin + $display("INFO: OS2WB: PCX_REQ_STEP1, STRSTORE"); wb_we<=1; case({icache_hit,dcache0_hit}) @@ -606,4 +620,5 @@ 5'b00110://SWAP/LDSTUB begin + $display("INFO: OS2WB: PCX_REQ_STEP1, SWAP/LDSTUB"); case({icache_hit,dcache0_hit}) 8'b00000000:; @@ -622,14 +637,18 @@ end 5'b01001://INT - if(pcx_packet_d[117]) // Flush + begin + $display("INFO: OS2WB: PCX_REQ_STEP1, INT"); + if(pcx_packet_d[117]) // Flush cpx_packet_1<={9'h171,pcx_packet_d[113:112],11'h0,pcx_packet_d[64+5:64+4],3'b0,pcx_packet_d[64+11:64+6],30'h0,pcx_packet_d[17:0],46'b0,pcx_packet_d[17:0]}; //FLUSH instruction answer - else // Tread-to-thread interrupt + else // Tread-to-thread interrupt cpx_packet_1<={9'h170,pcx_packet_d[113:112],52'h0,pcx_packet_d[17:0],46'h0,pcx_packet_d[17:0]}; - //5'b01010: FP1 - processed by separate state - //5'b01011: FP2 - processed by separate state - //5'b01101: FWDREQ - not implemented - //5'b01110: FWDREPL - not implemented - 5'b10000://IFILL - begin + //5'b01010: FP1 - processed by separate state + //5'b01011: FP2 - processed by separate state + //5'b01101: FWDREQ - not implemented + //5'b01110: FWDREPL - not implemented + end + 5'b10000://IFILL + begin + $display("INFO: OS2WB: PCX_REQ_STEP1, IFILL"); wb_we<=0; if(!pcx_req_d[4]) // not I/O access @@ -668,6 +687,7 @@ if(wb_ack) begin + $display("INFO: OS2WB: PCX_REQ_STEP1_1 wb_addr = %x",wb_addr); cpx_packet_1[144]<=1; // Valid - cpx_packet_1[139]<=(pcx_packet_d[122:118]==5'b00000) || (pcx_packet_d[122:118]==5'b10000) ? 1:0; // L2 always miss on load and ifill + cpx_packet_1[139]<=(pcx_packet_d[122:118]==5'b00000) || (pcx_packet_d[122:118]==5'b10000) ? 1:0; // L2 always miss on load and ifill cpx_packet_1[138:137]<=0; // Error cpx_packet_1[136]<=pcx_packet_d[117] || (pcx_packet_d[122:118]==5'b00001) ? 1:0; // Non-cacheble is set on store too @@ -821,4 +841,6 @@ 5'b10000://IFILL begin + $display("INFO: OS2WB: PCX_REQ_STEP1_1, IFILL, wb_addr = %x wb_data_i= %x",wb_addr, wb_data_i); + $display("INFO: OS2WB: PCX_REQ_STEP1_1, IFILL, cpx_packet_1 = %x %x",wb_data_i,wb_data_i); cpx_packet_1[143:140]<=4'b0001; // Type cpx_packet_2[143:140]<=4'b0001; // Type @@ -1073,4 +1095,5 @@ `CPX_READY_1: begin + $display("INFO: OS2WB: CPX_READY_1"); cpx_ready<=1; cpx_packet<=cpx_packet_1; @@ -1087,4 +1110,5 @@ `CPX_READY_2: begin + $display("INFO: OS2WB: CPX_READY_2"); cpx_ready<=1; cpx_packet<=cpx_packet_2; @@ -1093,4 +1117,5 @@ `PCX_UNKNOWN: begin + $display("INFO: OS2WB: PCX_UNKNOWN"); wb_sel<=8'b10100101; // Illegal eye-catching value for debugging state<=`PCX_IDLE; @@ -1250,10 +1275,10 @@ .enable(dir_en), .wren_a(icache0_alloc || icache0_dealloc || icache_inval_all || cache_init), - .address_a({2'b0,icache_index}), + .address_a({2'b00,icache_index}), .data_a(icache_data), .q_a(icache0_do), .wren_b(icache1_alloc || icache1_dealloc || icache_inval_all || cache_init), - .address_b({2'b0,icache_index}), + .address_b({2'b01,icache_index}), .data_b(icache_data), .q_b(icache1_do) @@ -1264,10 +1289,10 @@ .enable(dir_en), .wren_a(icache2_alloc || icache2_dealloc || icache_inval_all || cache_init), - .address_a({2'b0,icache_index}), + .address_a({2'b00,icache_index}), .data_a(icache_data), .q_a(icache2_do), .wren_b(icache3_alloc || icache3_dealloc || icache_inval_all || cache_init), - .address_b({2'b0,icache_index}), + .address_b({2'b01,icache_index}), .data_b(icache_data), .q_b(icache3_do) Index: /trunk/tools/dump2hex.php =================================================================== --- /trunk/tools/dump2hex.php (revision 25) +++ /trunk/tools/dump2hex.php (revision 26) @@ -6,24 +6,39 @@ // Discard first lines - for($i=0; $i<7; $i++) fgets($fp); + for($i=0; $i<8; $i++) fgets($fp); + // instruction start at address 10h + //echo "@ 10\n"; + echo "// inserisco 16 ff per partire da 10h e scrivo op4,op3,op2,op1 \n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; + echo "ffff\n"; // Print only the opcodes to stdout while (!feof($fp)) { $line = fgets($fp); - /*$opcode = substr($line, 8, 8); - $caratteri = strlen($opcode); + $opcode1 = substr($line, 6, 2); + $opcode2 = substr($line, 9, 2); + $opcode3 = substr($line, 12, 2); + $opcode4 = substr($line, 15, 2); + $caratteri = strlen($opcode1); if($caratteri != 0){ - echo $opcode."\n"; - }*/ - - $opcode = substr($line, 6, 2); - $opcode2 = substr($line, 9, 2); - $caratteri = strlen($opcode); - if($caratteri != 0){ - echo $opcode.$opcode2; + echo $opcode2.$opcode1; + //echo $opcode1.$opcode2; echo "\t //".$line; - $opcode = substr($line, 12, 2); - $opcode2 = substr($line, 15, 2); - echo $opcode.$opcode2."\n"; + echo $opcode4.$opcode3."\n"; + //echo $opcode3.$opcode4."\n"; } else{ Index: /trunk/WB/wb_conbus_top.v =================================================================== --- /trunk/WB/wb_conbus_top.v (revision 22) +++ /trunk/WB/wb_conbus_top.v (revision 26) @@ -137,5 +137,6 @@ parameter s0_addr = 1'b0; // slave 0 address -//address for a 32MB flash from 0x800000ff_f0800000 to 0x800000ff_f0ffffff +//PCX request on 800000ff_f0000020 +//address for a 32MB flash from 0x800000ff_f0000000 to 0x800000ff_f07fffff //Check address_w // 32 MB --> 8 MW X32 bits --> 2^23 --> addr_w=64-23=41 Index: /trunk/T1-CPU/exu/sparc_exu.v =================================================================== --- /trunk/T1-CPU/exu/sparc_exu.v (revision 6) +++ /trunk/T1-CPU/exu/sparc_exu.v (revision 26) @@ -595,45 +595,45 @@ assign syndrome[3]=ifu_exu_ren3_s_d && (irf_byp_rs3h_data_d_l_ref!=irf_byp_rs3h_data_d_l_fpga); -assign ILA_DATA[1:0]=ifu_exu_tid_s2; -assign ILA_DATA[6:2]=ifu_exu_rs1_s; -assign ILA_DATA[11:7]=ifu_exu_rs2_s; -assign ILA_DATA[16:12]=ifu_exu_rs3_s; -assign ILA_DATA[17]=ifu_exu_ren1_s; -assign ILA_DATA[18]=ifu_exu_ren2_s; -assign ILA_DATA[19]=ifu_exu_ren3_s; -assign ILA_DATA[20]=ecl_irf_wen_w; -assign ILA_DATA[21]=ecl_irf_wen_w2; -assign ILA_DATA[26:22]=ecl_irf_rd_m_d; -assign ILA_DATA[31:27]=ecl_irf_rd_g_d; -assign ILA_DATA[103:32]=byp_irf_rd_data_w; -assign ILA_DATA[175:104]=byp_irf_rd_data_w2; -assign ILA_DATA[177:176]=ecl_irf_tid_m; -assign ILA_DATA[179:178]=ecl_irf_tid_g; -assign ILA_DATA[182:180]=rml_irf_old_lo_cwp_e; -assign ILA_DATA[185:183]=rml_irf_new_lo_cwp_e; -assign ILA_DATA[187:186]=rml_irf_old_e_cwp_e; -assign ILA_DATA[189:188]=rml_irf_new_e_cwp_e; -assign ILA_DATA[190]=rml_irf_swap_even_e; -assign ILA_DATA[191]=rml_irf_swap_odd_e; -assign ILA_DATA[192]=rml_irf_swap_local_e; -assign ILA_DATA[193]=rml_irf_kill_restore_w; -assign ILA_DATA[195:194]=rml_irf_cwpswap_tid_e; -assign ILA_DATA[197:196]=rml_irf_old_agp; -assign ILA_DATA[199:198]=rml_irf_new_agp; -assign ILA_DATA[200]=rml_irf_swap_global; -assign ILA_DATA[202:201]=rml_irf_global_tid; -assign ILA_DATA[274:203]=irf_byp_rs1_data_d_l_ref; -assign ILA_DATA[346:275]=irf_byp_rs2_data_d_l_ref; -assign ILA_DATA[418:347]=irf_byp_rs3_data_d_l_ref; -assign ILA_DATA[450:419]=irf_byp_rs3h_data_d_l_ref; -assign ILA_DATA[522:451]=irf_byp_rs1_data_d_l_fpga; -assign ILA_DATA[594:523]=irf_byp_rs2_data_d_l_fpga; -assign ILA_DATA[666:595]=irf_byp_rs3_data_d_l_fpga; -assign ILA_DATA[698:667]=irf_byp_rs3h_data_d_l_fpga; -assign ILA_DATA[702:699]=syndrome;// && read_known0; -assign ILA_DATA[705:703]=current_cwp[2:0]; -assign ILA_DATA[706]=0; -assign ILA_DATA[737:707]={cnt[14:0],err_cnt}; -assign ILA_DATA[738]=rml_irf_swap_local_e && (current_window!=rml_irf_old_lo_cwp_e); +//assign ILA_DATA[1:0]=ifu_exu_tid_s2; +//assign ILA_DATA[6:2]=ifu_exu_rs1_s; +//assign ILA_DATA[11:7]=ifu_exu_rs2_s; +//assign ILA_DATA[16:12]=ifu_exu_rs3_s; +//assign ILA_DATA[17]=ifu_exu_ren1_s; +//assign ILA_DATA[18]=ifu_exu_ren2_s; +//assign ILA_DATA[19]=ifu_exu_ren3_s; +//assign ILA_DATA[20]=ecl_irf_wen_w; +//assign ILA_DATA[21]=ecl_irf_wen_w2; +//assign ILA_DATA[26:22]=ecl_irf_rd_m_d; +//assign ILA_DATA[31:27]=ecl_irf_rd_g_d; +//assign ILA_DATA[103:32]=byp_irf_rd_data_w; +//assign ILA_DATA[175:104]=byp_irf_rd_data_w2; +//assign ILA_DATA[177:176]=ecl_irf_tid_m; +//assign ILA_DATA[179:178]=ecl_irf_tid_g; +//assign ILA_DATA[182:180]=rml_irf_old_lo_cwp_e; +//assign ILA_DATA[185:183]=rml_irf_new_lo_cwp_e; +//assign ILA_DATA[187:186]=rml_irf_old_e_cwp_e; +//assign ILA_DATA[189:188]=rml_irf_new_e_cwp_e; +//assign ILA_DATA[190]=rml_irf_swap_even_e; +//assign ILA_DATA[191]=rml_irf_swap_odd_e; +//assign ILA_DATA[192]=rml_irf_swap_local_e; +//assign ILA_DATA[193]=rml_irf_kill_restore_w; +//assign ILA_DATA[195:194]=rml_irf_cwpswap_tid_e; +//assign ILA_DATA[197:196]=rml_irf_old_agp; +//assign ILA_DATA[199:198]=rml_irf_new_agp; +//assign ILA_DATA[200]=rml_irf_swap_global; +//assign ILA_DATA[202:201]=rml_irf_global_tid; +//assign ILA_DATA[274:203]=irf_byp_rs1_data_d_l_ref; +//assign ILA_DATA[346:275]=irf_byp_rs2_data_d_l_ref; +//assign ILA_DATA[418:347]=irf_byp_rs3_data_d_l_ref; +//assign ILA_DATA[450:419]=irf_byp_rs3h_data_d_l_ref; +//assign ILA_DATA[522:451]=irf_byp_rs1_data_d_l_fpga; +//assign ILA_DATA[594:523]=irf_byp_rs2_data_d_l_fpga; +//assign ILA_DATA[666:595]=irf_byp_rs3_data_d_l_fpga; +//assign ILA_DATA[698:667]=irf_byp_rs3h_data_d_l_fpga; +//assign ILA_DATA[702:699]=syndrome;// && read_known0; +//assign ILA_DATA[705:703]=current_cwp[2:0]; +//assign ILA_DATA[706]=0; +//assign ILA_DATA[737:707]={cnt[14:0],err_cnt}; +//assign ILA_DATA[738]=rml_irf_swap_local_e && (current_window!=rml_irf_old_lo_cwp_e); //assign ILA_DATA[699]=(irf_byp_rs1_data_d_l_fpga!=irf_byp_rs1_data_d_l_fpga_d) && (irf_byp_rs1_data_d_l==irf_byp_rs1_data_d_l_d); //assign ILA_DATA[700]=(irf_byp_rs2_data_d_l_fpga!=irf_byp_rs2_data_d_l_fpga_d) && (irf_byp_rs2_data_d_l==irf_byp_rs2_data_d_l_d); @@ -645,5 +645,5 @@ bw_r_irf_fpga1 irf( - .current_cwp(current_cwp), + .current_cwp(current_cwp[11:0]), .so (short_scan0_1), .si (short_si0), Index: /trunk/T1-CPU/exu/sparc_exu_alu.v =================================================================== --- /trunk/T1-CPU/exu/sparc_exu_alu.v (revision 6) +++ /trunk/T1-CPU/exu/sparc_exu_alu.v (revision 26) @@ -106,5 +106,5 @@ // Zero comparison for exu_ifu_regz_e - sparc_exu_aluzcmp64 regzcmp(.in(byp_alu_rcc_data_e[63:0]), .zero64(exu_ifu_regz_e)); + sparc_exu_aluzcmp64 regzcmp(.in(byp_alu_rcc_data_e[63:0]), .zero64(exu_ifu_regz_e),.zero32()); assign exu_ifu_regn_e = byp_alu_rcc_data_e[63]; Index: /trunk/T1-common/srams/bw_r_irf.v =================================================================== --- /trunk/T1-common/srams/bw_r_irf.v (revision 22) +++ /trunk/T1-common/srams/bw_r_irf.v (revision 26) @@ -1362,5 +1362,8 @@ new_agp_d2[1:0] <= new_agp_d1[1:0]; end -/* + +// synthesis traslate off +`ifdef DEBUG + always @(posedge clk) begin if (wr_en) begin @@ -1385,5 +1388,8 @@ end end -*/ + +// synthesis traslate on +`endif + endmodule Index: /trunk/Xilinx/cachedir.v =================================================================== --- /trunk/Xilinx/cachedir.v (revision 17) +++ /trunk/Xilinx/cachedir.v (revision 26) @@ -37,5 +37,5 @@ always @(posedge clock) begin - if (enable) + if (enable) if (wren_a) mem1[address_a] <= data_a; @@ -46,5 +46,5 @@ always @(posedge clock) begin - if (enable) + if (enable) if (wren_b) mem2[address_b] <= data_b;