Index: trunk/sim/simula.do
===================================================================
--- trunk/sim/simula.do	(revision 26)
+++ trunk/sim/simula.do	(revision 27)
@@ -2,4 +2,5 @@
 
 set DEFINE +define+DEBUG+FPGA_SYN
+#+FPGA_SYN_NO_SPU
 #+FPGA_NEW_IRF
 set INCLUDEDIR +incdir+../T1-common/include/
Index: trunk/NOR-flash/WBFLASH.v
===================================================================
--- trunk/NOR-flash/WBFLASH.v	(revision 22)
+++ trunk/NOR-flash/WBFLASH.v	(revision 27)
@@ -58,4 +58,6 @@
 assign wb_err_o=0;
 assign wb_rty_o=0;
+assign wb1_err_o=0;
+assign wb1_rty_o=0;
 
 reg  [1:0] wordcnt;
@@ -70,4 +72,6 @@
    if(wb_rst_i)
       begin
+         wb_ack_o<=0;
+         wb1_ack_o<=0;
          cache_addr<=64'b0;
          cache_addr1<=64'b0;
Index: trunk/sw/hello2.c
===================================================================
--- trunk/sw/hello2.c	(revision 27)
+++ trunk/sw/hello2.c	(revision 27)
@@ -0,0 +1,30 @@
+// Sample program that writes two words at a predefined address
+ 
+int main() {
+  asm("mov 0x10, %g1 \n");
+  asm("mov 0x20, %l1 \n");
+  asm("stx  %l1, [ %g1 ] \n");
+  asm(" nop \n");
+  asm("stx  %l1, [ %g1  +0x40 ] \n");
+  asm(" nop \n");
+  asm("ldx [ %g1 ], %l1 \n");
+  asm(" nop \n");
+  asm("ldx  [ %g1 ] , %l1\n");
+  asm(" nop \n");
+  asm("ldx  [ %g1 ] , %l1\n");
+  asm("ldx  [ %g1 ] , %l1\n");
+  asm("stx  %l1, [ %g1 ] \n");
+  asm(" nop \n");
+  asm("stx  %l1, [ %g1 +0x40 ] \n");
+  asm(" nop \n");
+  asm("stx  %l1, [ %g1 +0x60 ] \n");
+  asm(" nop \n");
+  asm("stx  %l1, [ %g1 +0x80 ] \n");
+  asm(" nop \n");
+  register unsigned long* address;
+  address = (unsigned long*)0x0000CAC0;
+  (*address) = 0xC1A0C1A0;  // First store
+  address = (unsigned long*)0x0000CAC0;
+  (*address) = 0xFABA1210;  // Second store
+  return 0;
+}
Index: trunk/os2wb/os2wb.v
===================================================================
--- trunk/os2wb/os2wb.v	(revision 26)
+++ trunk/os2wb/os2wb.v	(revision 27)
@@ -125,5 +125,5 @@
 
 // sal: escludo test della DRAM `define TEST_DRAM        1
-`define TEST_DRAM        1
+`define TEST_DRAM        0
 `define DEBUGGING        1
 
@@ -344,6 +344,8 @@
                cpx_ready<=0;
                cpx_two_packet<=0;
-               inval_vect0[3]<=0;
-               inval_vect1[3]<=0;
+               //inval_vect0[3]<=0;
+               //inval_vect1[3]<=0;
+               inval_vect0<=0;
+               inval_vect1<=0;
                multi_hit<=0;
                multi_hit1<=0;
Index: trunk/Top/W1.v
===================================================================
--- trunk/Top/W1.v	(revision 24)
+++ trunk/Top/W1.v	(revision 27)
@@ -304,7 +304,10 @@
     .s2_cyc_o(s2_cyc_o), 
     .s2_stb_o(s2_stb_o), 
-    .s2_ack_i(s2_ack_i), 
-    .s2_err_i(s2_err_i), 
-    .s2_rty_i(s2_rty_i), 
+    .s2_ack_i(1'b0), 
+    .s2_err_i(1'b0), 
+    .s2_rty_i(1'b0), 
+    //.s2_ack_i(s2_ack_i), 
+    //.s2_err_i(s2_err_i), 
+    //.s2_rty_i(s2_rty_i), 
     .s2_cab_o(s2_cab_o), 
 
@@ -318,7 +321,7 @@
     .s3_stb_o(s3_stb_o), 
     .s3_ack_i(s3_ack_i), 
-    .s3_err_i(s3_err_i), 
-    .s3_rty_i(s3_rty_i), 
-    .s3_cab_o(s3_cab_o), 
+    .s3_err_i(1'b0), 
+    .s3_rty_i(1'b0), 
+    .s3_cab_o(), 
 
     //Second flash interface for fff8xxxxxx ram disk addressing
Index: trunk/T1-common/srams/bw_r_scm.v
===================================================================
--- trunk/T1-common/srams/bw_r_scm.v	(revision 6)
+++ trunk/T1-common/srams/bw_r_scm.v	(revision 27)
@@ -294,5 +294,5 @@
 
 // tolgo stb_ramc_d dalla sensitivity list...
-always @( byte_overlap or ramc_entry,cam_tag or cam_bmask or ptag_hit or byte_match)
+always @( byte_overlap or ramc_entry,cam_tag or cam_bmask or ptag_hit or byte_match or stb_ramc_d)
   begin
 	for (l=0;l<NUMENTRIES;l=l+1)
Index: trunk/Xilinx/cachedir.v
===================================================================
--- trunk/Xilinx/cachedir.v	(revision 26)
+++ trunk/Xilinx/cachedir.v	(revision 27)
@@ -48,6 +48,6 @@
 	if (enable)
          if (wren_b)
-            mem2[address_b] <= data_b;
+            mem1[address_b] <= data_b;
      end
-assign  q_b = mem2[address_b];
+assign  q_b = mem1[address_b];
 endmodule