Index: /trunk/synplicity/proj_1.prj
===================================================================
--- /trunk/synplicity/proj_1.prj	(revision 10)
+++ /trunk/synplicity/proj_1.prj	(revision 28)
@@ -116,4 +116,5 @@
 add_file -verilog "../WB2ALTDDR3/dram_wb.v"
 add_file -verilog "../Xilinx/cachedir.v"
+add_file -verilog "../Xilinx/dram_fifo_fall.v"
 add_file -verilog "../Xilinx/dram_fifo.v"
 add_file -verilog "../Xilinx/pcx_fifo.v"
Index: /trunk/synplicity/rev_1/run_ise.tcl
===================================================================
--- /trunk/synplicity/rev_1/run_ise.tcl	(revision 10)
+++ /trunk/synplicity/rev_1/run_ise.tcl	(revision 28)
@@ -9,7 +9,7 @@
 set TopModule	"W1"
 set EdifFile	"W1.edf"
-if {![file exists $DesignName.xise]} {
+if {![file exists $DesignName.ise]} {
 
-project new $DesignName.xise
+project new $DesignName.ise
 
 project set family $FamilyName
@@ -33,5 +33,5 @@
 file delete -force $DesignName\_xdb
 
-project open $DesignName.xise
+project open $DesignName.ise
 
 process run "Implement Design" -force rerun_all