Index: trunk/sw/uart.h
===================================================================
--- trunk/sw/uart.h	(revision 32)
+++ trunk/sw/uart.h	(revision 32)
@@ -0,0 +1,137 @@
+#ifndef _UART_H_
+#define _UART_H_
+void uart_init(char);
+void uart_putc(char, char);
+void uart_puts(char, char*);
+void uart_putc_noblock(char, char);
+char uart_getc(char);
+int uart_check_for_char(char);
+void uart_rxint_enable(char);
+void uart_rxint_disable(char);
+void uart_txint_enable(char);
+void uart_txint_disable(char);
+char uart_get_iir(char);
+char uart_get_lsr(char);
+char uart_get_msr(char);
+
+#define DEFAULT_UART 0 /* Default UART to use */
+
+
+#define UART_RX		0	/* In:  Receive buffer (DLAB=0) */
+#define UART_TX		0	/* Out: Transmit buffer (DLAB=0) */
+#define UART_DLL	0	/* Out: Divisor Latch Low (DLAB=1) */
+#define UART_DLM	1	/* Out: Divisor Latch High (DLAB=1) */
+#define UART_IER	1	/* Out: Interrupt Enable Register */
+#define UART_IIR	2	/* In:  Interrupt ID Register */
+#define UART_FCR	2	/* Out: FIFO Control Register */
+#define UART_EFR	2	/* I/O: Extended Features Register */
+/* (DLAB=1, 16C660 only) */
+#define UART_LCR	3	/* Out: Line Control Register */
+#define UART_MCR	4	/* Out: Modem Control Register */
+#define UART_LSR	5	/* In:  Line Status Register */
+#define UART_MSR	6	/* In:  Modem Status Register */
+#define UART_SCR	7	/* I/O: Scratch Register */
+
+/*
+ * These are the definitions for the FIFO Control Register
+ * (16650 only)
+ */
+#define UART_FCR_ENABLE_FIFO	0x01 /* Enable the FIFO */
+#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
+#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
+#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
+#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
+#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
+#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
+#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
+#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
+/* 16650 redefinitions */
+#define UART_FCR6_R_TRIGGER_8	0x00 /* Mask for receive trigger set at 1 */
+#define UART_FCR6_R_TRIGGER_16	0x40 /* Mask for receive trigger set at 4 */
+#define UART_FCR6_R_TRIGGER_24  0x80 /* Mask for receive trigger set at 8 */
+#define UART_FCR6_R_TRIGGER_28	0xC0 /* Mask for receive trigger set at 14 */
+#define UART_FCR6_T_TRIGGER_16	0x00 /* Mask for transmit trigger set at 16 */
+#define UART_FCR6_T_TRIGGER_8	0x10 /* Mask for transmit trigger set at 8 */
+#define UART_FCR6_T_TRIGGER_24  0x20 /* Mask for transmit trigger set at 24 */
+#define UART_FCR6_T_TRIGGER_30	0x30 /* Mask for transmit trigger set at 30 */
+
+/*
+ * These are the definitions for the Line Control Register
+ * 
+ * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 
+ * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
+ */
+#define UART_LCR_DLAB	0x80	/* Divisor latch access bit */
+#define UART_LCR_SBC	0x40	/* Set break control */
+#define UART_LCR_SPAR	0x20	/* Stick parity (?) */
+#define UART_LCR_EPAR	0x10	/* Even parity select */
+#define UART_LCR_PARITY	0x08	/* Parity Enable */
+#define UART_LCR_STOP	0x04	/* Stop bits: 0=1 stop bit, 1= 2 stop bits */
+#define UART_LCR_WLEN5  0x00	/* Wordlength: 5 bits */
+#define UART_LCR_WLEN6  0x01	/* Wordlength: 6 bits */
+#define UART_LCR_WLEN7  0x02	/* Wordlength: 7 bits */
+#define UART_LCR_WLEN8  0x03	/* Wordlength: 8 bits */
+
+/*
+ * These are the definitions for the Line Status Register
+ */
+#define UART_LSR_TEMT	0x40	/* Transmitter empty */
+#define UART_LSR_THRE	0x20	/* Transmit-hold-register empty */
+#define UART_LSR_BI	0x10	/* Break interrupt indicator */
+#define UART_LSR_FE	0x08	/* Frame error indicator */
+#define UART_LSR_PE	0x04	/* Parity error indicator */
+#define UART_LSR_OE	0x02	/* Overrun error indicator */
+#define UART_LSR_DR	0x01	/* Receiver data ready */
+
+/*
+ * These are the definitions for the Interrupt Identification Register
+ */
+#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
+#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
+
+#define UART_IIR_MSI	0x00	/* Modem status interrupt */
+#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
+#define UART_IIR_TOI	0x0c	/* Receive time out interrupt */
+#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
+#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
+
+/*
+ * These are the definitions for the Interrupt Enable Register
+ */
+#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
+#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
+#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
+#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
+
+/*
+ * These are the definitions for the Modem Control Register
+ */
+#define UART_MCR_LOOP	0x10	/* Enable loopback test mode */
+#define UART_MCR_OUT2	0x08	/* Out2 complement */
+#define UART_MCR_OUT1	0x04	/* Out1 complement */
+#define UART_MCR_RTS	0x02	/* RTS complement */
+#define UART_MCR_DTR	0x01	/* DTR complement */
+
+/*
+ * These are the definitions for the Modem Status Register
+ */
+#define UART_MSR_DCD	0x80	/* Data Carrier Detect */
+#define UART_MSR_RI	0x40	/* Ring Indicator */
+#define UART_MSR_DSR	0x20	/* Data Set Ready */
+#define UART_MSR_CTS	0x10	/* Clear to Send */
+#define UART_MSR_DDCD	0x08	/* Delta DCD */
+#define UART_MSR_TERI	0x04	/* Trailing edge ring indicator */
+#define UART_MSR_DDSR	0x02	/* Delta DSR */
+#define UART_MSR_DCTS	0x01	/* Delta CTS */
+#define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */
+
+/*
+ * These are the definitions for the Extended Features Register
+ * (StarTech 16C660 only, when DLAB=1)
+ */
+#define UART_EFR_CTS	0x80	/* CTS flow control */
+#define UART_EFR_RTS	0x40	/* RTS flow control */
+#define UART_EFR_SCD	0x20	/* Special character detect */
+#define UART_EFR_ENI	0x10	/* Enhanced Interrupt */
+
+#endif // __UART_H_
Index: trunk/sw/linker.lds
===================================================================
--- trunk/sw/linker.lds	(revision 32)
+++ trunk/sw/linker.lds	(revision 32)
@@ -0,0 +1,11 @@
+/* linker script for XOPENSPARC */
+ 
+OUTPUT_FORMAT("elf64-sparc")
+ENTRY(main)
+
+
+SECTIONS { 
+  .text 0x00000020 : { *(.text) }
+  .data : { *(.data) } 
+  .bss :  { *(.bss)  *(COMMON) } 
+} 
Index: trunk/sw/uart.c
===================================================================
--- trunk/sw/uart.c	(revision 32)
+++ trunk/sw/uart.c	(revision 32)
@@ -0,0 +1,157 @@
+#include "uart.h"
+
+const int UART_BASE_ADR[1] = {0};
+const int UART_BAUDS[1] = {0};
+const int IN_CLK =50000000;
+
+#define REG8(add) *((volatile unsigned char *)(add))
+
+#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
+
+#define WAIT_FOR_XMITR(core)			\
+do { \
+lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
+} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
+
+#define WAIT_FOR_THRE(core)			\
+do { \
+lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
+} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
+
+#define CHECK_FOR_CHAR(core) (REG8(UART_BASE_ADR[core] + UART_LSR) & UART_LSR_DR)
+
+#define WAIT_FOR_CHAR(core)			\
+do { \
+lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
+} while ((lsr & UART_LSR_DR) != UART_LSR_DR)
+
+#define UART_TX_BUFF_LEN 32
+#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
+
+char tx_buff[UART_TX_BUFF_LEN];
+volatile int tx_level, rx_level;
+
+void main() __attribute__((noreturn));
+void main() 
+{
+	asm("mov 0x00, %sp\n");
+	asm("mov 0x00, %fp\n");
+	uart_init(0);
+	for(;;) { 
+		uart_puts(0,"XOpenSparc is alive \n"); 
+	} 
+        //return;
+}
+
+void uart_init(char core)
+{
+	long allone=0xffffffffffffffff;
+	int divisor;
+	float float_divisor;
+	
+	/* Reset receiver and transmiter */
+	REG8( UART_FCR ) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
+	
+	/* Disable all interrupts */
+	REG8(UART_BASE_ADR[core] + UART_IER) = 0x00;
+	
+	/* Set 8 bit char, 1 stop bit, no parity */
+	REG8(UART_BASE_ADR[core] + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
+	
+	/* Set baud rate */
+	float_divisor = (float) IN_CLK/(16 * UART_BAUDS[core]);
+	float_divisor += 0.50f; // Ensure round up
+	divisor = (int) float_divisor;
+	
+	REG8(UART_BASE_ADR[core] + UART_LCR) |= UART_LCR_DLAB;
+	REG8(UART_BASE_ADR[core] + UART_DLL) = divisor & 0x000000ff;
+	REG8(UART_BASE_ADR[core] + UART_DLM) = (divisor >> 8) & 0x000000ff;
+	REG8(UART_BASE_ADR[core] + UART_LCR) &= ~(UART_LCR_DLAB);
+	
+	return;
+}
+
+void uart_putc(char core, char c)
+{
+	unsigned char lsr;
+	
+	WAIT_FOR_THRE(core);
+	REG8(UART_BASE_ADR[core] + UART_TX) = c;
+	if(c == '\n') {
+		WAIT_FOR_THRE(core);
+		REG8(UART_BASE_ADR[core] + UART_TX) = '\r';
+	}
+	WAIT_FOR_XMITR(core);
+}
+
+void uart_puts (char core, char *s) { 
+	// loop until *s != NULL 
+	while (*s) { 
+		uart_putc(core,*s); 
+		s++; 
+	} 
+}
+
+
+
+// Only used when we know THRE is empty, typically in interrupt
+/*void uart_putc_noblock(char core, char c)
+{
+	REG8(UART_BASE_ADR[core] + UART_TX) = c;
+}
+
+
+char uart_getc(char core)
+{
+	unsigned char lsr;
+	char c;
+	
+	WAIT_FOR_CHAR(core);
+	c = REG8(UART_BASE_ADR[core] + UART_RX);
+	return c;
+}
+
+int uart_check_for_char(char core)
+{
+	return CHECK_FOR_CHAR(core);
+}
+
+void uart_rxint_enable(char core)
+{
+	REG8(UART_BASE_ADR[core] + UART_IER) |= UART_IER_RDI;
+}
+
+void uart_rxint_disable(char core)
+{
+	REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_RDI);
+}
+
+void uart_txint_enable(char core)
+{
+	REG8(UART_BASE_ADR[core] + UART_IER) |= UART_IER_THRI;
+}
+
+void uart_txint_disable(char core)
+{
+	REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_THRI);
+}
+
+char uart_get_iir(char core)
+{
+	return REG8(UART_BASE_ADR[core] + UART_IIR);
+}
+
+
+char uart_get_lsr(char core)
+{
+	return REG8(UART_BASE_ADR[core] + UART_LSR);
+}
+
+
+char uart_get_msr(char core)
+{
+	return REG8(UART_BASE_ADR[core] + UART_MSR);
+}
+*/
+
+