Index: trunk/synplicity/proj_1.prj
===================================================================
--- trunk/synplicity/proj_1.prj	(revision 6)
+++ trunk/synplicity/proj_1.prj	(revision 8)
@@ -4,4 +4,5 @@
 
 #project files
+add_file -verilog "../trunk/T1-common/include/xst_defines.h"
 add_file -verilog "../trunk/Top/W1.v"
 add_file -verilog "../trunk/OC-UART/raminfr.v"
@@ -279,11 +280,15 @@
 set_option -project_relative_includes 1
 set_option -enable_nfilter 0
-set_option -hdl_define -set "FPGA FPGA_SYN"
 set_option -include_path /home/sal/Desktop/sparc64soc/trunk/T1-common/include/
+
+#pr_1 attributes
+set_option -job pr_1 -add par
+set_option -job pr_1 -option enable_run 1
+set_option -job pr_1 -option run_backannotation 0
 
 #device options
 set_option -technology Virtex5
-set_option -part XC5VLX20T
-set_option -package FF323
+set_option -part XC5VLX110T
+set_option -package FF1136
 set_option -speed_grade -1
 set_option -part_companion ""