Index: trunk/synplicity/rev_1/W1.ucf =================================================================== --- trunk/synplicity/rev_1/W1.ucf (revision 9) +++ trunk/synplicity/rev_1/W1.ucf (revision 9) @@ -0,0 +1,184 @@ +########################## segnali globali + +NET CLK_IN LOC="K19"; # Bank 3, Vcco=2.5V, No DCI +#### reset รจ negato !!! +NET SYSRST LOC="E9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors + +########################## segnali per FLASH +NET FLASH_ADDR<0> LOC="K12"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<1> LOC="K13"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<2> LOC="H23"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<3> LOC="G23"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<4> LOC="H12"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<5> LOC="J12"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<6> LOC="K22"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<7> LOC="K23"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<8> LOC="K14"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<9> LOC="L14"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<10> LOC="H22"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<11> LOC="G22"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<12> LOC="J15"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<13> LOC="K16"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<14> LOC="K21"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<15> LOC="J22"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<16> LOC="L16"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<17> LOC="L15"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<18> LOC="L20"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<19> LOC="L21"; # Bank 1, Vcco=3.3V +NET FLASH_ADDR<20> LOC="AE23"; # Bank 2, Vcco=3.3V +NET FLASH_ADDR<21> LOC="AE22"; # Bank 2, Vcco=3.3V +NET FLASH_DATA<0> LOC="AD19"; # Bank 2, Vcco=3.3V +NET FLASH_DATA<1> LOC="AE19"; # Bank 2, Vcco=3.3V +NET FLASH_DATA<2> LOC="AE17"; # Bank 2, Vcco=3.3V +NET FLASH_DATA<3> LOC="AF16"; # Bank 2, Vcco=3.3V +NET FLASH_DATA<4> LOC="AD20"; # Bank 2, Vcco=3.3V +NET FLASH_DATA<5> LOC="AE21"; # Bank 2, Vcco=3.3V +NET FLASH_DATA<6> LOC="AE16"; # Bank 2, Vcco=3.3V +NET FLASH_DATA<7> LOC="AF15"; # Bank 2, Vcco=3.3V +NET FLASH_DATA<8> LOC="AH13"; # Bank 4, Vcco=3.3V, No DCI +NET FLASH_DATA<9> LOC="AH14"; # Bank 4, Vcco=3.3V, No DCI +NET FLASH_DATA<10> LOC="AH19"; # Bank 4, Vcco=3.3V, No DCI +NET FLASH_DATA<11> LOC="AH20"; # Bank 4, Vcco=3.3V, No DCI +NET FLASH_DATA<12> LOC="AG13"; # Bank 4, Vcco=3.3V, No DCI +NET FLASH_DATA<13> LOC="AH12"; # Bank 4, Vcco=3.3V, No DCI +NET FLASH_DATA<14> LOC="AH22"; # Bank 4, Vcco=3.3V, No DCI +NET FLASH_DATA<15> LOC="AG22"; # Bank 4, Vcco=3.3V, No DCI +NET FLASH_WEN LOC="AF20"; # Bank 2, Vcco=3.3V +NET FLASH_CEN LOC="AE14"; # Bank 2, Vcco=3.3V +NET FLASH_CLK LOC="N9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors +NET FLASH_OEN LOC="AF14"; # Bank 2, Vcco=3.3V +#### FLASH_ADV e flash reset sono negati !!! +NET FLASH_ADV LOC="F13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors +NET FLASH_RST LOC="AG17"; # Bank 4, Vcco=3.3V, No DCI + + +########################## segnali per porta seriale +NET SRX LOC="AG15"; # Bank 4, Vcco=3.3V, No DCI +NET STX LOC="AG20"; # Bank 4, Vcco=3.3V, No DCI +## mancano i segnali flash_rev +#NET FPGA_SERIAL2_RX LOC="G10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors +#NET FPGA_SERIAL2_TX LOC="F10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors +########################## + + +##################segnali per DDR +# +### manca phy_init_done +NET DDR3_CE LOC="T28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +#NET DDR3_CKE1 LOC="U30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_CK_N LOC="AJ29"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_CK LOC="AK29"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +#NET DDR3_CLK1_N LOC="F28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +#NET DDR3_CLK1_P LOC="E28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_CS_N LOC="L29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +#NET DDR3_CS1_B LOC="J29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_ODT LOC="F31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +#NET DDR2_ODT<1> LOC="F30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<0> LOC="L30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<1> LOC="M30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<2> LOC="N29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<3> LOC="P29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<4> LOC="K31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<5> LOC="L31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<6> LOC="P31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<7> LOC="P30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<8> LOC="M31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<9> LOC="R28"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<10> LOC="J31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<11> LOC="R29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_A<12> LOC="T31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +# NET DDR3_A13 LOC="H29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_BA<0> LOC="G31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_BA<1> LOC="J30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_BA<2> LOC="R31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_CAS_N LOC="E31"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_RAS_N LOC="H30"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_WE_N LOC="K29"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<0> LOC="AF30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<1> LOC="AK31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<2> LOC="AF31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<3> LOC="AD30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<4> LOC="AJ30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<5> LOC="AF29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<6> LOC="AD29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<7> LOC="AE29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<8> LOC="AH27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<9> LOC="AF28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<10> LOC="AH28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<11> LOC="AA28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<12> LOC="AG25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<13> LOC="AJ26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<14> LOC="AG28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<15> LOC="AB28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<16> LOC="AC28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<17> LOC="AB25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<18> LOC="AC27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<19> LOC="AA26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<20> LOC="AB26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<21> LOC="AA24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<22> LOC="AB27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<23> LOC="AA25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<24> LOC="AC29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<25> LOC="AB30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<26> LOC="W31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<27> LOC="V30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<28> LOC="AC30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<29> LOC="W29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<30> LOC="V27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<31> LOC="W27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<32> LOC="V29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<33> LOC="Y27"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<34> LOC="Y26"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<35> LOC="W24"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<36> LOC="V28"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<37> LOC="W25"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<38> LOC="W26"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<39> LOC="V24"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<40> LOC="R24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<41> LOC="P25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<42> LOC="N24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<43> LOC="P26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<44> LOC="T24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<45> LOC="N25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<46> LOC="P27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<47> LOC="N28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<48> LOC="M28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<49> LOC="L28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<50> LOC="F25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<51> LOC="H25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<52> LOC="K27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<53> LOC="K28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<54> LOC="H24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<55> LOC="G26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<56> LOC="G25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<57> LOC="M26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<58> LOC="J24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<59> LOC="L26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<60> LOC="J27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<61> LOC="M25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<62> LOC="L25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQ<63> LOC="L24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DM<0> LOC="AJ31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DM<1> LOC="AE28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DM<2> LOC="Y24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DM<3> LOC="Y31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DM<4> LOC="V25"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DM<5> LOC="P24"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DM<6> LOC="F26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DM<7> LOC="J25"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS_N<0> LOC="AA30"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS<0> LOC="AA29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS_N<1> LOC="AK27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS<1> LOC="AK28"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS_N<2> LOC="AJ27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS<2> LOC="AK26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS_N<3> LOC="AA31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS<3> LOC="AB31"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS_N<4> LOC="Y29"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS<4> LOC="Y28"; # Bank 17, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS_N<5> LOC="E27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS<5> LOC="E26"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS_N<6> LOC="G28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS<6> LOC="H28"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS_N<7> LOC="H27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors +NET DDR3_DQS<7> LOC="G27"; # Bank 19, Vcco=1.8V, DCI using 49.9 ohm resistors Index: trunk/synplicity/rev_1/run_xise.tcl =================================================================== --- trunk/synplicity/rev_1/run_xise.tcl (revision 9) +++ trunk/synplicity/rev_1/run_xise.tcl (revision 9) @@ -0,0 +1,41 @@ +######################### +### DEFINE VARIABLES ### +######################### +set DesignName "W1" +set FamilyName "VIRTEX5" +set DeviceName "XC5VLX110T" +set PackageName "FF1136" +set SpeedGrade "-1" +set TopModule "W1" +set EdifFile "W1.edf" +if {![file exists $DesignName.xise]} { + +project new $DesignName.xise + +project set family $FamilyName +project set device $DeviceName +project set package $PackageName +project set speed $SpeedGrade + +xfile add W1.ucf +#xfile add $EdifFile +#if {[file exists synplicity.ucf]} { +# xfile add synplicity.ucf +#} + +project set "Netlist Translation Type" "Timestamp" +project set "Other NGDBuild Command Line Options" "-verbose" +project set "Generate Detailed MAP Report" TRUE + +project close +} + + +file delete -force $DesignName\_xdb + +project open $DesignName.ise + +process run "Implement Design" -force rerun_all + +project close +