xilinx.com CoreGen coregen 1.0 pcx_fifo 32 No_Programmable_Full_Threshold 130 0 false 1 1 No_Programmable_Empty_Threshold 32 false false Active_High 6 Active_High 130 31 6 false false false true Common_Clock_Block_RAM 4 false false true Active_High 1 30 false false Asynchronous_Reset 6 true false false false Active_High 5 false First_Word_Fall_Through true false coregen ./ ./tmp/ ./tmp/_cg xc5vlx110t virtex5 ff1136 -3 BusFormatAngleBracketNotRipped Verilog true Foundation_ISE false false false Ngc false Behavioral VHDL_and_Verilog false implementation_netlist_generator ./fifo_generator_readme.txt txt Tue Apr 05 16:20:07 GMT 2011 0x406DA7B6 ./fifo_generator_ug175.pdf pdf Tue Apr 05 16:20:07 GMT 2011 0x6AAA9CA5 ./pcx_fifo.asy asy Tue Apr 05 16:19:33 GMT 2011 0x892196C5 ./pcx_fifo.ngc ngc Tue Apr 05 16:20:14 GMT 2011 0xB3A039FD ./pcx_fifo.sym asy unknown Tue Apr 05 16:20:07 GMT 2011 0xA77B7FBA ./pcx_fifo.v verilog Tue Apr 05 16:20:07 GMT 2011 0x8CE9DF06 ./pcx_fifo.veo veo Tue Apr 05 16:20:07 GMT 2011 0xCDE28FCE ./pcx_fifo.vhd vhdl Tue Apr 05 16:20:07 GMT 2011 0x4900B0F2 ./pcx_fifo.vho vho Tue Apr 05 16:20:07 GMT 2011 0x87B95DAF instantiation_template_generator xco_generator ./pcx_fifo.xco xco Tue Apr 05 16:20:20 GMT 2011 0xF28E8321 xmdf_generator ./pcx_fifo_xmdf.tcl tclXmdf tcl Tue Apr 05 16:20:21 GMT 2011 0x64A4148B ise_generator ./_xmsgs/pn_parser.xmsgs ignore unknown Tue Apr 05 16:20:23 GMT 2011 0x8FDD154B ./pcx_fifo.gise ignore gise Tue Apr 05 16:20:23 GMT 2011 0xF51F1E4A ./pcx_fifo.xise ignore xise Tue Apr 05 16:20:23 GMT 2011 0x21D80DCE deliver_readme_generator flist_generator ./pcx_fifo_flist.txt ignore txtFlist txt Tue Apr 05 16:20:24 GMT 2011 0xEB9DAAF6 dram_fifo_fall 1024 No_Programmable_Full_Threshold 104 0 false 1 1 No_Programmable_Empty_Threshold 1024 false false Active_High 10 Active_High 104 1023 8 false false false true Independent_Clocks_Block_RAM 4 false false false Active_High 1 1022 false false Asynchronous_Reset 10 true false true false Active_High 5 false First_Word_Fall_Through true false coregen ./ ./tmp/ ./tmp/_cg xc5vlx110t virtex5 ff1738 -2 BusFormatAngleBracketNotRipped Verilog false Other false false false Ngc false Behavioral Verilog false implementation_netlist_generator ./dram_fifo_fall.ngc ngc Tue Apr 05 16:27:13 GMT 2011 0xDAB9FEED ./dram_fifo_fall.v verilog Tue Apr 05 16:27:06 GMT 2011 0x9E906AAF ./dram_fifo_fall.veo veo Tue Apr 05 16:27:06 GMT 2011 0x9E5C30F0 ./fifo_generator_readme.txt txt Tue Apr 05 16:27:06 GMT 2011 0x406DA7B6 ./fifo_generator_ug175.pdf pdf Tue Apr 05 16:27:06 GMT 2011 0x6AAA9CA5 instantiation_template_generator xco_generator ./dram_fifo_fall.xco xco Tue Apr 05 16:27:20 GMT 2011 0x9DCBEFE1 xmdf_generator ./dram_fifo_fall_xmdf.tcl tclXmdf tcl Tue Apr 05 16:27:20 GMT 2011 0x641BC3B2 ise_generator ./_xmsgs/pn_parser.xmsgs ignore unknown Tue Apr 05 16:27:22 GMT 2011 0x7A8CC252 ./dram_fifo_fall.gise ignore gise Tue Apr 05 16:27:22 GMT 2011 0x1D1F53A9 ./dram_fifo_fall.xise ignore xise Tue Apr 05 16:27:22 GMT 2011 0x1E49B963 deliver_readme_generator flist_generator ./dram_fifo_fall_flist.txt ignore txtFlist txt Tue Apr 05 16:27:23 GMT 2011 0x21C271E1 dram ./dram/user_design/mig.prj coregen ./ ./tmp/ ./tmp/_cg xc5vlx110t virtex5 ff1136 -2 BusFormatAngleBracketNotRipped Verilog false Other false false false Ngc false Behavioral Verilog false apply_current_project_options_generator customization_generator ./dram/docs/adr_cntrl_timing.xls ignore unknown Tue Apr 05 16:40:04 GMT 2011 0xAF35ABC0 ./dram/docs/read_data_timing.xls ignore unknown Tue Apr 05 16:40:04 GMT 2011 0xD41334D2 ./dram/docs/ug086.pdf ignore pdf Tue Apr 05 16:40:04 GMT 2011 0xE22E2DD9 ./dram/docs/write_data_timing.xls ignore unknown Tue Apr 05 16:40:04 GMT 2011 0x605046E7 ./dram/docs/xapp858.url ignore unknown Tue Apr 05 16:40:04 GMT 2011 0x5698FE61 ./dram/example_design/datasheet.txt ignore txt Tue Apr 05 16:40:06 GMT 2011 0xC37D389D ./dram/example_design/log.txt ignore txt Tue Apr 05 16:40:06 GMT 2011 0xC1E7BA28 ./dram/example_design/mig.prj ignore unknown Tue Apr 05 16:40:06 GMT 2011 0xA8882241 ./dram/example_design/par/create_ise.sh ignore unknown Tue Apr 05 16:40:05 GMT 2011 0x4061A2FB ./dram/example_design/par/dram.cdc ignore unknown Tue Apr 05 16:40:06 GMT 2011 0x6EE977AF ./dram/example_design/par/dram.ucf ignore ucf Tue Apr 05 16:40:04 GMT 2011 0x5A0C3967 ./dram/example_design/par/icon4_cg.xco ignore xco Tue Apr 05 16:40:05 GMT 2011 0x4A7195DB ./dram/example_design/par/ise_flow.sh ignore unknown Tue Apr 05 16:40:06 GMT 2011 0x73708A72 ./dram/example_design/par/makeproj.sh ignore unknown Tue Apr 05 16:40:05 GMT 2011 0xCFE64DF9 ./dram/example_design/par/mem_interface_top.ut ignore unknown Tue Apr 05 16:40:05 GMT 2011 0x86B57F5F ./dram/example_design/par/readme.txt ignore txt Tue Apr 05 16:40:05 GMT 2011 0xB61B5CA2 ./dram/example_design/par/rem_files.sh ignore unknown Tue Apr 05 16:40:05 GMT 2011 0x7D95BC3B ./dram/example_design/par/set_ise_prop.tcl ignore tcl Tue Apr 05 16:40:05 GMT 2011 0x3985F253 ./dram/example_design/par/vio_async_in100_cg.xco ignore xco Tue Apr 05 16:40:05 GMT 2011 0x150DD2E5 ./dram/example_design/par/vio_async_in192_cg.xco ignore xco Tue Apr 05 16:40:05 GMT 2011 0x3056F7D4 ./dram/example_design/par/vio_async_in96_cg.xco ignore xco Tue Apr 05 16:40:05 GMT 2011 0xFCA8FE3A ./dram/example_design/par/vio_sync_out32_cg.xco ignore xco Tue Apr 05 16:40:05 GMT 2011 0x3E1B42D8 ./dram/example_design/par/xst_run.txt ignore txt Tue Apr 05 16:40:06 GMT 2011 0xBBC98CDC ./dram/example_design/rtl/ddr2_chipscope.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x13004F63 ./dram/example_design/rtl/ddr2_ctrl.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0xC3D6C942 ./dram/example_design/rtl/ddr2_idelay_ctrl.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x4E0236B8 ./dram/example_design/rtl/ddr2_infrastructure.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x1F4DA34F ./dram/example_design/rtl/ddr2_mem_if_top.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x5CA50F62 ./dram/example_design/rtl/ddr2_phy_calib.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x5D99496C ./dram/example_design/rtl/ddr2_phy_ctl_io.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0xC0350AB6 ./dram/example_design/rtl/ddr2_phy_dm_iob.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0xE026F687 ./dram/example_design/rtl/ddr2_phy_dq_iob.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0xB5481EF2 ./dram/example_design/rtl/ddr2_phy_dqs_iob.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x6AA23EE3 ./dram/example_design/rtl/ddr2_phy_init.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x484F40E9 ./dram/example_design/rtl/ddr2_phy_io.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x3E2D935D ./dram/example_design/rtl/ddr2_phy_top.v ignore verilog Tue Apr 05 16:40:05 GMT 2011 0x84E8B7FA ./dram/example_design/rtl/ddr2_phy_write.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x9F3FAE3F ./dram/example_design/rtl/ddr2_tb_test_addr_gen.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x6310BD19 ./dram/example_design/rtl/ddr2_tb_test_cmp.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x7E4007C0 ./dram/example_design/rtl/ddr2_tb_test_data_gen.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0xE54696F7 ./dram/example_design/rtl/ddr2_tb_test_gen.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x1AAEAAF8 ./dram/example_design/rtl/ddr2_tb_top.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0xD624063D ./dram/example_design/rtl/ddr2_top.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0xFD835B0A ./dram/example_design/rtl/ddr2_usr_addr_fifo.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x40199D58 ./dram/example_design/rtl/ddr2_usr_rd.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0x1D8C33F9 ./dram/example_design/rtl/ddr2_usr_top.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0xC70D8ABA ./dram/example_design/rtl/ddr2_usr_wr.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0xEBF2E3B2 ./dram/example_design/rtl/dram.v ignore verilog Tue Apr 05 16:40:05 GMT 2011 0xF57AEE60 ./dram/example_design/sim/ddr2_model.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0xF630302C ./dram/example_design/sim/ddr2_model_parameters.vh ignore unknown Tue Apr 05 16:40:04 GMT 2011 0x1D074097 ./dram/example_design/sim/sim.do ignore unknown Tue Apr 05 16:40:06 GMT 2011 0x862A01F0 ./dram/example_design/sim/sim_tb_top.v ignore verilog Tue Apr 05 16:40:04 GMT 2011 0xC2EF0A39 ./dram/example_design/sim/wiredly.v ignore verilog Tue Apr 05 16:40:06 GMT 2011 0x6D7F8BC1 ./dram/example_design/synth/dram.lso ignore unknown Tue Apr 05 16:40:06 GMT 2011 0xEEDE3797 ./dram/example_design/synth/dram.prj ignore unknown Tue Apr 05 16:40:06 GMT 2011 0x381F2EBF ./dram/example_design/synth/mem_interface_top_synp.sdc ignore unknown Tue Apr 05 16:40:06 GMT 2011 0x4BF3FF0A ./dram/example_design/synth/script_synp.tcl ignore tcl Tue Apr 05 16:40:06 GMT 2011 0xE6E6500E ./dram/user_design/datasheet.txt ignore txt Tue Apr 05 16:40:07 GMT 2011 0x51EB744D ./dram/user_design/log.txt ignore txt Tue Apr 05 16:40:07 GMT 2011 0x12B6A9AC ./dram/user_design/mig.prj ignore unknown Tue Apr 05 16:40:07 GMT 2011 0xA8882241 ./dram/user_design/par/create_ise.sh ignore unknown Tue Apr 05 16:40:07 GMT 2011 0x4061A2FB ./dram/user_design/par/dram.cdc ignore unknown Tue Apr 05 16:40:07 GMT 2011 0x6EE977AF ./dram/user_design/par/dram.ucf ucf Tue Apr 05 16:40:07 GMT 2011 0xA0F58F97 ./dram/user_design/par/icon4_cg.xco ignore xco Tue Apr 05 16:40:07 GMT 2011 0x4A7195DB ./dram/user_design/par/ise_flow.sh ignore unknown Tue Apr 05 16:40:07 GMT 2011 0x73708A72 ./dram/user_design/par/makeproj.sh ignore unknown Tue Apr 05 16:40:07 GMT 2011 0xCFE64DF9 ./dram/user_design/par/mem_interface_top.ut ignore unknown Tue Apr 05 16:40:07 GMT 2011 0x86B57F5F ./dram/user_design/par/readme.txt ignore txt Tue Apr 05 16:40:07 GMT 2011 0xBDF11E52 ./dram/user_design/par/rem_files.sh ignore unknown Tue Apr 05 16:40:07 GMT 2011 0x7D95BC3B ./dram/user_design/par/set_ise_prop.tcl ignore tcl Tue Apr 05 16:40:07 GMT 2011 0x572F43EC ./dram/user_design/par/vio_async_in100_cg.xco ignore xco Tue Apr 05 16:40:07 GMT 2011 0x150DD2E5 ./dram/user_design/par/vio_async_in192_cg.xco ignore xco Tue Apr 05 16:40:07 GMT 2011 0x3056F7D4 ./dram/user_design/par/vio_async_in96_cg.xco ignore xco Tue Apr 05 16:40:07 GMT 2011 0xFCA8FE3A ./dram/user_design/par/vio_sync_out32_cg.xco ignore xco Tue Apr 05 16:40:07 GMT 2011 0x3E1B42D8 ./dram/user_design/par/xst_run.txt ignore txt Tue Apr 05 16:40:07 GMT 2011 0xBBC98CDC ./dram/user_design/rtl/ddr2_chipscope.v verilog Tue Apr 05 16:40:06 GMT 2011 0x13004F63 ./dram/user_design/rtl/ddr2_ctrl.v verilog Tue Apr 05 16:40:06 GMT 2011 0xC3D6C942 ./dram/user_design/rtl/ddr2_idelay_ctrl.v verilog Tue Apr 05 16:40:06 GMT 2011 0x4E0236B8 ./dram/user_design/rtl/ddr2_infrastructure.v verilog Tue Apr 05 16:40:06 GMT 2011 0x1F4DA34F ./dram/user_design/rtl/ddr2_mem_if_top.v verilog Tue Apr 05 16:40:06 GMT 2011 0x5CA50F62 ./dram/user_design/rtl/ddr2_phy_calib.v verilog Tue Apr 05 16:40:06 GMT 2011 0x5D99496C ./dram/user_design/rtl/ddr2_phy_ctl_io.v verilog Tue Apr 05 16:40:06 GMT 2011 0xC0350AB6 ./dram/user_design/rtl/ddr2_phy_dm_iob.v verilog Tue Apr 05 16:40:06 GMT 2011 0xE026F687 ./dram/user_design/rtl/ddr2_phy_dq_iob.v verilog Tue Apr 05 16:40:06 GMT 2011 0xB5481EF2 ./dram/user_design/rtl/ddr2_phy_dqs_iob.v verilog Tue Apr 05 16:40:06 GMT 2011 0x6AA23EE3 ./dram/user_design/rtl/ddr2_phy_init.v verilog Tue Apr 05 16:40:06 GMT 2011 0x484F40E9 ./dram/user_design/rtl/ddr2_phy_io.v verilog Tue Apr 05 16:40:06 GMT 2011 0x3E2D935D ./dram/user_design/rtl/ddr2_phy_top.v verilog Tue Apr 05 16:40:07 GMT 2011 0x84E8B7FA ./dram/user_design/rtl/ddr2_phy_write.v verilog Tue Apr 05 16:40:06 GMT 2011 0x9F3FAE3F ./dram/user_design/rtl/ddr2_top.v verilog Tue Apr 05 16:40:06 GMT 2011 0xFD835B0A ./dram/user_design/rtl/ddr2_usr_addr_fifo.v verilog Tue Apr 05 16:40:06 GMT 2011 0x40199D58 ./dram/user_design/rtl/ddr2_usr_rd.v verilog Tue Apr 05 16:40:06 GMT 2011 0x1D8C33F9 ./dram/user_design/rtl/ddr2_usr_top.v verilog Tue Apr 05 16:40:06 GMT 2011 0xC70D8ABA ./dram/user_design/rtl/ddr2_usr_wr.v verilog Tue Apr 05 16:40:06 GMT 2011 0xEBF2E3B2 ./dram/user_design/rtl/dram.v verilog Tue Apr 05 16:40:07 GMT 2011 0x07C2B78B ./dram/user_design/sim/ddr2_model.v ignore verilog Tue Apr 05 16:40:06 GMT 2011 0xF630302C ./dram/user_design/sim/ddr2_model_parameters.vh ignore unknown Tue Apr 05 16:40:06 GMT 2011 0x1D074097 ./dram/user_design/sim/ddr2_tb_test_addr_gen.v ignore verilog Tue Apr 05 16:40:06 GMT 2011 0x6310BD19 ./dram/user_design/sim/ddr2_tb_test_cmp.v ignore verilog Tue Apr 05 16:40:06 GMT 2011 0x7E4007C0 ./dram/user_design/sim/ddr2_tb_test_data_gen.v ignore verilog Tue Apr 05 16:40:06 GMT 2011 0xE54696F7 ./dram/user_design/sim/ddr2_tb_test_gen.v ignore verilog Tue Apr 05 16:40:06 GMT 2011 0x1AAEAAF8 ./dram/user_design/sim/ddr2_tb_top.v ignore verilog Tue Apr 05 16:40:06 GMT 2011 0xD624063D ./dram/user_design/sim/sim.do ignore unknown Tue Apr 05 16:40:07 GMT 2011 0x862A01F0 ./dram/user_design/sim/sim_tb_top.v ignore verilog Tue Apr 05 16:40:06 GMT 2011 0xAFB3EED9 ./dram/user_design/sim/wiredly.v ignore verilog Tue Apr 05 16:40:07 GMT 2011 0x6D7F8BC1 ./dram/user_design/synth/dram.lso ignore unknown Tue Apr 05 16:40:07 GMT 2011 0xEEDE3797 ./dram/user_design/synth/dram.prj ignore unknown Tue Apr 05 16:40:07 GMT 2011 0x0A17E334 ./dram/user_design/synth/mem_interface_top_synp.sdc ignore unknown Tue Apr 05 16:40:07 GMT 2011 0x4BF3FF0A ./dram/user_design/synth/script_synp.tcl ignore tcl Tue Apr 05 16:40:07 GMT 2011 0xB4CD288C ./dram.veo veo Tue Apr 05 16:40:07 GMT 2011 0xFCA448AE ./dram_xmdf.tcl ignore tcl Tue Apr 05 16:40:07 GMT 2011 0xF9346F2D ip_xco_generator ./dram.xco xco Tue Apr 05 16:40:08 GMT 2011 0x233E60C2 implementation_source_generator instantiation_template_generator xco_generator ./dram.xco xco Tue Apr 05 16:40:09 GMT 2011 0x52F13DE8 xmdf_generator ise_generator ./_xmsgs/pn_parser.xmsgs ignore unknown Tue Apr 05 16:40:12 GMT 2011 0xDE1D52E2 ./dram.gise ignore gise Tue Apr 05 16:40:12 GMT 2011 0x00A32788 ./dram.xise ignore xise Tue Apr 05 16:40:12 GMT 2011 0xC85A02F6 deliver_readme_generator ./dram_readme.txt ignore txtReadme txt Tue Apr 05 16:40:13 GMT 2011 0xA213FA26 flist_generator ./dram_flist.txt ignore txtFlist txt Tue Apr 05 16:40:13 GMT 2011 0xE644368A view_readme_generator coregen ./ ./tmp/ ./tmp/_cg xc5vlx110t virtex5 ff1136 -2 BusFormatAngleBracketNotRipped Verilog false Other false false false Ngc false Behavioral Verilog false