#
# Constraints generated by Synplify Pro maprc, Build 312R
#

# Period Constraints

#Begin clock constraints
NET "clk_in" TNM_NET = "clk_in"; 
TIMESPEC "TS_clk_in" = PERIOD "clk_in" 12.000 ns HIGH 50.00%; 
#End clock constraints



# I/O Registers Packing Constraints
INST "flash_inst/wb_dat[*]" IOB=FALSE; # flash_inst/wb_dat[63:0]
INST "flash_inst/wb1_dat[*]" IOB=FALSE; # flash_inst/wb1_dat[63:0]

# I/O Registers Packing Constraints
INST "uart16550/regs/i_uart_sync_flops/flop_0[0]" IOB=FALSE;

# End of generated constraints