# Date: Tue Apr  5 16:26:02 2011

SET addpads = false
SET asysymbol = false
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc5vlx110t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = ff1136
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
SET workingdirectory = ./tmp/

# CRC: e8561b33