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#
# Xilinx Core Generator version 12.3
# Date: Mon Mar 14 23:37:43 2011
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
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#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc5vlx110t
SET devicefamily = virtex5
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1136
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT MIG family Xilinx,_Inc. 3.6
# END Select
# BEGIN Parameters
CSET component_name=dram
CSET xml_input_file=./dram/user_design/mig.prj
# END Parameters
GENERATE
# CRC: f2eca964