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SET designentry = Verilog
SET BusFormat = BusFormatAngleBracketNotRipped
SET devicefamily = virtex5
SET device = xc5vlx110t
SET package = ff1136
SET speedgrade = -3
SET FlowVendor = Foundation_ISE
SET VerilogSim = True
SET VHDLSim = True
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=dram_fifo
CSET data_count=false
CSET data_count_width=10
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=1021
CSET full_threshold_negate_value=1020
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=104
CSET input_depth=1024
CSET output_data_width=104
CSET output_depth=1024
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=10
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=false
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=true
CSET write_data_count_width=8
GENERATE