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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
pcx_fifo YourInstanceName (
	.clk(clk),
	.rst(rst),
	.din(din), // Bus [129 : 0] 
	.wr_en(wr_en),
	.rd_en(rd_en),
	.dout(dout), // Bus [129 : 0] 
	.full(full),
	.empty(empty));

// INST_TAG_END ------ End INSTANTIATION Template ---------

// You must compile the wrapper file pcx_fifo.v when simulating
// the core, pcx_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".