#-- Synopsys, Inc. #-- Version E-2010.09-SP3 #-- Project file /home/sal/Desktop/sparc64soc/synplicity/proj_1.prj #project files add_file -verilog "../trunk/Top/W1.v" add_file -verilog "../trunk/OC-UART/raminfr.v" add_file -verilog "../trunk/OC-UART/timescale.v" add_file -verilog "../trunk/OC-UART/uart_debug_if.v" add_file -verilog "../trunk/OC-UART/uart_defines.v" add_file -verilog "../trunk/OC-UART/uart_receiver.v" add_file -verilog "../trunk/OC-UART/uart_regs.v" add_file -verilog "../trunk/OC-UART/uart_rfifo.v" add_file -verilog "../trunk/OC-UART/uart_sync_flops.v" add_file -verilog "../trunk/OC-UART/uart_tfifo.v" add_file -verilog "../trunk/OC-UART/uart_top.v" add_file -verilog "../trunk/OC-UART/uart_transmitter.v" add_file -verilog "../trunk/OC-UART/uart_wb.v" add_file -verilog "../trunk/NOR-flash/WBFLASH.v" add_file -verilog "../trunk/os2wb/l1ddir.v" add_file -verilog "../trunk/os2wb/l1dir.v" add_file -verilog "../trunk/os2wb/l1idir.v" add_file -verilog "../trunk/os2wb/os2wb.v" add_file -verilog "../trunk/os2wb/os2wb_dual.v" add_file -verilog "../trunk/os2wb/rst_ctrl.v" add_file -verilog "../trunk/os2wb/s1_top.v" add_file -verilog "../trunk/T1-common/common/cluster_header.v" add_file -verilog "../trunk/T1-common/common/cluster_header_ctu.v" add_file -verilog "../trunk/T1-common/common/cluster_header_dup.v" add_file -verilog "../trunk/T1-common/common/cluster_header_sync.v" add_file -verilog "../trunk/T1-common/common/cmp_sram_redhdr.v" add_file -verilog "../trunk/T1-common/common/dbl_buf.v" add_file -verilog "../trunk/T1-common/common/swrvr_clib.v" add_file -verilog "../trunk/T1-common/common/swrvr_dlib.v" add_file -verilog "../trunk/T1-common/common/sync_pulse_synchronizer.v" add_file -verilog "../trunk/T1-common/common/synchronizer_asr.v" add_file -verilog "../trunk/T1-common/common/synchronizer_asr_dup.v" add_file -verilog "../trunk/T1-common/common/test_stub_bist.v" add_file -verilog "../trunk/T1-common/common/test_stub_scan.v" add_file -verilog "../trunk/T1-common/common/ucb_bus_in.v" add_file -verilog "../trunk/T1-common/common/ucb_bus_out.v" add_file -verilog "../trunk/T1-common/common/ucb_flow_2buf.v" add_file -verilog "../trunk/T1-common/common/ucb_flow_jbi.v" add_file -verilog "../trunk/T1-common/common/ucb_flow_spi.v" add_file -verilog "../trunk/T1-common/common/ucb_noflow.v" add_file -verilog "../trunk/T1-common/m1/m1.V" add_file -verilog "../trunk/T1-common/srams/bw_r_cm16x40.v" add_file -verilog "../trunk/T1-common/srams/bw_r_cm16x40b.v" add_file -verilog "../trunk/T1-common/srams/bw_r_dcd.v" add_file -verilog "../trunk/T1-common/srams/bw_r_dcm.v" add_file -verilog "../trunk/T1-common/srams/bw_r_efa.v" add_file -verilog "../trunk/T1-common/srams/bw_r_frf.v" add_file -verilog "../trunk/T1-common/srams/bw_r_icd.v" add_file -verilog "../trunk/T1-common/srams/bw_r_idct.v" add_file -verilog "../trunk/T1-common/srams/bw_r_irf.v" add_file -verilog "../trunk/T1-common/srams/bw_r_irf_fpga1.v" add_file -verilog "../trunk/T1-common/srams/bw_r_irf_register.v" add_file -verilog "../trunk/T1-common/srams/bw_r_l2d.v" add_file -verilog "../trunk/T1-common/srams/bw_r_l2d_32k.v" add_file -verilog "../trunk/T1-common/srams/bw_r_l2d_rep_bot.v" add_file -verilog "../trunk/T1-common/srams/bw_r_l2d_rep_top.v" add_file -verilog "../trunk/T1-common/srams/bw_r_l2t.v" add_file -verilog "../trunk/T1-common/srams/bw_r_rf16x128d.v" add_file -verilog "../trunk/T1-common/srams/bw_r_rf16x160.v" add_file -verilog "../trunk/T1-common/srams/bw_r_rf16x32.v" add_file -verilog "../trunk/T1-common/srams/bw_r_rf32x108.v" add_file -verilog "../trunk/T1-common/srams/bw_r_rf32x152b.v" add_file -verilog "../trunk/T1-common/srams/bw_r_rf32x80.v" add_file -verilog "../trunk/T1-common/srams/bw_r_scm.v" add_file -verilog "../trunk/T1-common/srams/bw_r_tlb.v" add_file -verilog "../trunk/T1-common/srams/bw_r_tlb_fpga.v" add_file -verilog "../trunk/T1-common/srams/bw_rf_16x65.v" add_file -verilog "../trunk/T1-common/srams/bw_rf_16x81.v" add_file -verilog "../trunk/T1-common/srams/regfile_1w_4r.v" add_file -verilog "../trunk/T1-common/u1/u1.V" add_file -verilog "../trunk/T1-FPU/bw_clk_cl_fpu_cmp.v" add_file -verilog "../trunk/T1-FPU/fpu.v" add_file -verilog "../trunk/T1-FPU/fpu_add.v" add_file -verilog "../trunk/T1-FPU/fpu_add_ctl.v" add_file -verilog "../trunk/T1-FPU/fpu_add_exp_dp.v" add_file -verilog "../trunk/T1-FPU/fpu_add_frac_dp.v" add_file -verilog "../trunk/T1-FPU/fpu_cnt_lead0_53b.v" add_file -verilog "../trunk/T1-FPU/fpu_cnt_lead0_64b.v" add_file -verilog "../trunk/T1-FPU/fpu_cnt_lead0_lvl1.v" add_file -verilog "../trunk/T1-FPU/fpu_cnt_lead0_lvl2.v" add_file -verilog "../trunk/T1-FPU/fpu_cnt_lead0_lvl3.v" add_file -verilog "../trunk/T1-FPU/fpu_cnt_lead0_lvl4.v" add_file -verilog "../trunk/T1-FPU/fpu_denorm_3b.v" add_file -verilog "../trunk/T1-FPU/fpu_denorm_3to1.v" add_file -verilog "../trunk/T1-FPU/fpu_denorm_frac.v" add_file -verilog "../trunk/T1-FPU/fpu_div.v" add_file -verilog "../trunk/T1-FPU/fpu_div_ctl.v" add_file -verilog "../trunk/T1-FPU/fpu_div_exp_dp.v" add_file -verilog "../trunk/T1-FPU/fpu_div_frac_dp.v" add_file -verilog "../trunk/T1-FPU/fpu_in.v" add_file -verilog "../trunk/T1-FPU/fpu_in2_gt_in1_2b.v" add_file -verilog "../trunk/T1-FPU/fpu_in2_gt_in1_3b.v" add_file -verilog "../trunk/T1-FPU/fpu_in2_gt_in1_3to1.v" add_file -verilog "../trunk/T1-FPU/fpu_in2_gt_in1_frac.v" add_file -verilog "../trunk/T1-FPU/fpu_in_ctl.v" add_file -verilog "../trunk/T1-FPU/fpu_in_dp.v" add_file -verilog "../trunk/T1-FPU/fpu_mul.v" add_file -verilog "../trunk/T1-FPU/fpu_mul_ctl.v" add_file -verilog "../trunk/T1-FPU/fpu_mul_exp_dp.v" add_file -verilog "../trunk/T1-FPU/fpu_mul_frac_dp.v" add_file -verilog "../trunk/T1-FPU/fpu_out.v" add_file -verilog "../trunk/T1-FPU/fpu_out_ctl.v" add_file -verilog "../trunk/T1-FPU/fpu_out_dp.v" add_file -verilog "../trunk/T1-FPU/fpu_rptr_groups.v" add_file -verilog "../trunk/T1-FPU/fpu_rptr_macros.v" add_file -verilog "../trunk/T1-FPU/fpu_rptr_min_global.v" add_file -verilog "../trunk/WB/wb_conbus_arb.v" add_file -verilog "../trunk/WB/wb_conbus_defines.v" add_file -verilog "../trunk/WB/wb_conbus_top.v" add_file -verilog "../trunk/WB2ALTDDR3/dram_wb.v" add_file -verilog "../xup5lx110t/cachedir.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram_fifo.v" add_file -verilog "../xup5lx110t/ipcore_dir/pcx_fifo.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/dram.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_chipscope.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_ctrl.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_idelay_ctrl.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_infrastructure.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_mem_if_top.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_calib.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_ctl_io.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_dm_iob.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_dq_iob.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_dqs_iob.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_init.v" add_file -vhdl -lib work "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_init.vhd" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_io.v" add_file -vhdl -lib work "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_io.vhd" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_top.v" add_file -vhdl -lib work "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_top.vhd" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_write.v" add_file -vhdl -lib work "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_phy_write.vhd" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_top.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_usr_addr_fifo.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_usr_rd.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_usr_top.v" add_file -verilog "../xup5lx110t/ipcore_dir/dram/user_design/rtl/ddr2_usr_wr.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_alu.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_alu_16eql.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_aluadder64.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_aluaddsub.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_alulogic.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_aluor32.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_aluspr.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_aluzcmp64.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_byp.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_byp_eccgen.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_div.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_div_32eql.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_div_yreg.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecc.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecc_dec.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecl.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecl_cnt6.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecl_divcntl.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecl_eccctl.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecl_mdqctl.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_ecl_wb.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_eclbyplog.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_eclbyplog_rs1.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_eclccr.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_eclcomp7.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_reg.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_rml.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_rml_cwp.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_rml_inc3.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_rndrob.v" add_file -verilog "../trunk/T1-CPU/exu/sparc_exu_shft.v" add_file -verilog "../trunk/T1-CPU/ffu/sparc_ffu.v" add_file -verilog "../trunk/T1-CPU/ffu/sparc_ffu_ctl.v" add_file -verilog "../trunk/T1-CPU/ffu/sparc_ffu_ctl_visctl.v" add_file -verilog "../trunk/T1-CPU/ffu/sparc_ffu_dp.v" add_file -verilog "../trunk/T1-CPU/ffu/sparc_ffu_part_add32.v" add_file -verilog "../trunk/T1-CPU/ffu/sparc_ffu_vis.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_cmp35.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_ctr5.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_dcl.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_dec.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_errctl.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_errdp.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_fcl.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_fdp.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_ifqctl.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_ifqdp.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_imd.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_incr46.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_invctl.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_lfsr5.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_lru4.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_mbist.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_milfsm.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_par16.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_par32.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_par34.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_rndrob.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_sscan.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_swl.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_swpla.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_thrcmpl.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_thrfsm.v" add_file -verilog "../trunk/T1-CPU/ifu/sparc_ifu_wseldp.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_asi_decode.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_dc_parity_gen.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_dcache_lfsr.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_dcdp.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_dctl.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_dctldp.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_excpctl.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_pcx_qmon.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_qctl1.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_qctl2.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_qdp1.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_qdp2.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_rrobin_picker2.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_stb_ctl.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_stb_ctldp.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_stb_rwctl.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_stb_rwdp.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_tagdp.v" add_file -verilog "../trunk/T1-CPU/lsu/lsu_tlbdp.v" add_file -verilog "../trunk/T1-CPU/mul/mul64.v" add_file -verilog "../trunk/T1-CPU/mul/sparc_mul_cntl.v" add_file -verilog "../trunk/T1-CPU/mul/sparc_mul_dp.v" add_file -verilog "../trunk/T1-CPU/mul/sparc_mul_top.v" add_file -verilog "../trunk/T1-CPU/rtl/bw_clk_cl_sparc_cmp.v" add_file -verilog "../trunk/T1-CPU/rtl/cpx_spc_buf.v" add_file -verilog "../trunk/T1-CPU/rtl/cpx_spc_rpt.v" add_file -verilog "../trunk/T1-CPU/rtl/sparc.v" add_file -verilog "../trunk/T1-CPU/rtl/spc_pcx_buf.v" add_file -verilog "../trunk/T1-CPU/spu/spu.v" add_file -verilog "../trunk/T1-CPU/spu/spu_ctl.v" add_file -verilog "../trunk/T1-CPU/spu/spu_lsurpt.v" add_file -verilog "../trunk/T1-CPU/spu/spu_lsurpt1.v" add_file -verilog "../trunk/T1-CPU/spu/spu_maaddr.v" add_file -verilog "../trunk/T1-CPU/spu/spu_maaeqb.v" add_file -verilog "../trunk/T1-CPU/spu/spu_mactl.v" add_file -verilog "../trunk/T1-CPU/spu/spu_madp.v" add_file -verilog "../trunk/T1-CPU/spu/spu_maexp.v" add_file -verilog "../trunk/T1-CPU/spu/spu_mald.v" add_file -verilog "../trunk/T1-CPU/spu/spu_mamul.v" add_file -verilog "../trunk/T1-CPU/spu/spu_mared.v" add_file -verilog "../trunk/T1-CPU/spu/spu_mast.v" add_file -verilog "../trunk/T1-CPU/spu/spu_wen.v" add_file -verilog "../trunk/T1-CPU/tlu/sparc_tlu_dec64.v" add_file -verilog "../trunk/T1-CPU/tlu/sparc_tlu_intctl.v" add_file -verilog "../trunk/T1-CPU/tlu/sparc_tlu_intdp.v" add_file -verilog "../trunk/T1-CPU/tlu/sparc_tlu_penc64.v" add_file -verilog "../trunk/T1-CPU/tlu/sparc_tlu_zcmp64.v" add_file -verilog "../trunk/T1-CPU/tlu/tlu.v" add_file -verilog "../trunk/T1-CPU/tlu/tlu_addern_32.v" add_file -verilog "../trunk/T1-CPU/tlu/tlu_hyperv.v" add_file -verilog "../trunk/T1-CPU/tlu/tlu_incr64.v" add_file -verilog "../trunk/T1-CPU/tlu/tlu_misctl.v" add_file -verilog "../trunk/T1-CPU/tlu/tlu_mmu_ctl.v" add_file -verilog "../trunk/T1-CPU/tlu/tlu_mmu_dp.v" add_file -verilog "../trunk/T1-CPU/tlu/tlu_pib.v" add_file -verilog "../trunk/T1-CPU/tlu/tlu_prencoder16.v" add_file -verilog "../trunk/T1-CPU/tlu/tlu_rrobin_picker.v" add_file -verilog "../trunk/T1-CPU/tlu/tlu_tcl.v" add_file -verilog "../trunk/T1-CPU/tlu/tlu_tdp.v" add_file -verilog "../xup5lx110t/ipcore_dir/pll.v" #implementation: "rev_1" impl -add rev_1 -type fpga # #implementation attributes set_option -vlog_std v2001 set_option -project_relative_includes 1 set_option -enable_nfilter 0 set_option -hdl_define -set "FPGA FPGA_SYN" set_option -include_path /home/sal/Desktop/sparc64soc/trunk/T1-common/include/ #device options set_option -technology Virtex5 set_option -part XC5VLX20T set_option -package FF323 set_option -speed_grade -1 set_option -part_companion "" #compilation/mapping options set_option -use_fsm_explorer 0 set_option -top_module "W1" # mapper_options set_option -frequency auto set_option -write_verilog 0 set_option -write_vhdl 0 # Xilinx Virtex2 set_option -run_prop_extract 1 set_option -maxfan 10000 set_option -disable_io_insertion 0 set_option -pipe 1 set_option -update_models_cp 0 set_option -retiming 0 set_option -no_sequential_opt 0 set_option -fixgatedclocks 3 set_option -fixgeneratedclocks 3 # Xilinx Virtex5 set_option -enable_prepacking 1 # NFilter set_option -popfeed 0 set_option -constprop 0 set_option -createhierarchy 0 # sequential_optimization_options set_option -symbolic_fsm_compiler 1 # Compiler Options set_option -compiler_compatible 0 set_option -resource_sharing 1 #VIF options set_option -write_vif 1 #automatic place and route (vendor) options set_option -write_apr_constraint 1 #set result format/file last project -result_file "./rev_1/W1.edf" #design plan options set_option -nfilter_user_path "" impl -active "rev_1"