#
# ChangeLog for trunk/sim in XOpenSparcT1
# 
# Generated by Trac 0.12.2
# 11/25/24 20:23:09
 
Tue, 05 Apr 2011 09:58:40 GMT pntsvt00 [27]
	* trunk/NOR-flash/WBFLASH.v (modified)
	* trunk/T1-common/srams/bw_r_scm.v (modified)
	* trunk/Top/W1.v (modified)
	* trunk/Xilinx/cachedir.v (modified)
	* trunk/os2wb/os2wb.v (modified)
	* trunk/sim/simula.do (modified)
	* trunk/sw/hello2.c (added)

	eliminato baco store consecutivi. esegue correttamente il codice


Mon, 04 Apr 2011 11:58:11 GMT pntsvt00 [26]
	* trunk/T1-CPU/exu/sparc_exu.v (modified)
	* trunk/T1-CPU/exu/sparc_exu_alu.v (modified)
	* trunk/T1-common/srams/bw_r_irf.v (modified)
	* trunk/WB/wb_conbus_top.v (modified)
	* trunk/Xilinx/cachedir.v (modified)
	* trunk/os2wb/os2wb.v (modified)
	* trunk/sim/flash.v (modified)
	* trunk/sim/simula.do (modified)
	* trunk/sw/hello.c (modified)
	* trunk/sw/hello.dump (modified)
	* trunk/tools/dump2hex.php (modified)

	checkpoint: baco con store consecutivi


Fri, 01 Apr 2011 10:30:46 GMT pntsvt00 [23]
	* trunk/Top/W1.v (modified)
	* trunk/WB2ALTDDR3/dram_wb.v (modified)
	* trunk/Xilinx/dram_fifo_fall.v (added)
	* trunk/Xilinx/dram_fifo_fall.xco (added)
	* trunk/os2wb/os2wb.v (modified)
	* trunk/sim/tb_top.v (modified)

	supera il test di write e read dalla  DDR


Thu, 31 Mar 2011 12:31:26 GMT pntsvt00 [22]
	* trunk/NOR-flash/WBFLASH.v (modified)
	* trunk/T1-common/srams/bw_r_icd.v (modified)
	* trunk/T1-common/srams/bw_r_irf.v (modified)
	* trunk/Top/W1.v (modified)
	* trunk/WB/wb_conbus_top.v (modified)
	* trunk/WB2ALTDDR3/dram_wb.v (modified)
	* trunk/os2wb/os2wb.v (modified)
	* trunk/os2wb/s1_top.v (modified)
	* trunk/sim/sim.do (deleted)
	* trunk/sim/sim_tb_top.v (modified)
	* trunk/sim/simula.do (modified)
	* trunk/sim/tb_top.v (modified)
	* trunk/sim/wiredly.vhd (deleted)

	checkpoint: la DDR effettua l'init


Mon, 28 Mar 2011 08:42:33 GMT pntsvt00 [21]
	* trunk/sim/flash.v (modified)

	modificato hello.c, ora flash.v legge da memory_hello.hex


Fri, 25 Mar 2011 18:21:45 GMT pntsvt00 [19]
	* trunk/sim/hello.dump (deleted)
	* trunk/sim/memory.hex (modified)
	* trunk/sw/compila (modified)
	* trunk/sw/hello.c (added)
	* trunk/sw/hello.dump (added)
	* trunk/sw/test.dump (added)
	* trunk/tools/dump2hex.php (modified)

	ora ho 2 sorgenti SPARC-V9, memory.hex e  memory_hello.hex


Fri, 25 Mar 2011 16:38:57 GMT pntsvt00 [18]
	* trunk/sim/hello.dump (added)
	* trunk/sim/memory.hex (added)
	* trunk/sw (added)
	* trunk/sw/README (added)
	* trunk/sw/compila (added)
	* trunk/sw/test.c (added)

	compilato us sorgente con architettura SPARC-V9


Fri, 25 Mar 2011 12:19:25 GMT pntsvt00 [17]
	* trunk/Top/W1.v (modified)
	* trunk/WB/wb_conbus_top.v (modified)
	* trunk/WB2ALTDDR3/dram_wb.v (modified)
	* trunk/Xilinx/cachedir.v (modified)
	* trunk/Xilinx/dram.v (modified)
	* trunk/os2wb/os2wb.v (modified)
	* trunk/sim/flash.v (modified)
	* trunk/sim/simula.do (modified)
	* trunk/sim/tb_top.v (modified)
	* trunk/tools (added)
	* trunk/tools/dump2hex.php (added)

	la simulazione legge dalla flash


Thu, 24 Mar 2011 15:05:49 GMT pntsvt00 [16]
	* trunk/sim/tb_top.v (modified)

	ora la simulazione parte


Thu, 24 Mar 2011 14:58:51 GMT pntsvt00 [15]
	* trunk/sim/simula.do (modified)

	modificato simula.do: ora arriva al Loadimg della simulazione


Thu, 24 Mar 2011 14:47:26 GMT pntsvt00 [14]
	* trunk/Top/W1.v (modified)
	* trunk/os2wb/os2wb.v (modified)
	* trunk/os2wb/os2wb_dual.v (modified)
	* trunk/sim/simula.do (modified)

	commit per simulazione di os2wb e Top


Thu, 24 Mar 2011 14:42:39 GMT pntsvt00 [13]
	* trunk/sim/simula.do (added)

	commit dofile per simulazione


Thu, 24 Mar 2011 14:38:52 GMT ttvmrc00 [12]
	* trunk/sim/flash.v (added)

	aggiunto flash.v


Thu, 24 Mar 2011 14:38:46 GMT pntsvt00 [11]
	* trunk/sim/tb_top.v (added)

	commit versione simulabile


Tue, 22 Mar 2011 20:08:58 GMT pntsvt00 [10]
	* README.TXT (added)
	* trunk/Top/W1.v (modified)
	* trunk/WB2ALTDDR3/dram_wb.v (modified)
	* trunk/Xilinx/cachedir.v (added)
	* trunk/Xilinx/ddr2_chipscope.v (added)
	* trunk/Xilinx/ddr2_ctrl.v (added)
	* trunk/Xilinx/ddr2_idelay_ctrl.v (added)
	* trunk/Xilinx/ddr2_infrastructure.v (added)
	* trunk/Xilinx/ddr2_mem_if_top.v (added)
	* trunk/Xilinx/ddr2_phy_calib.v (added)
	* trunk/Xilinx/ddr2_phy_ctl_io.v (added)
	* trunk/Xilinx/ddr2_phy_dm_iob.v (added)
	* trunk/Xilinx/ddr2_phy_dq_iob.v (added)
	* trunk/Xilinx/ddr2_phy_dqs_iob.v (added)
	* trunk/Xilinx/ddr2_phy_init.v (added)
	* trunk/Xilinx/ddr2_phy_io.v (added)
	* trunk/Xilinx/ddr2_phy_top.v (added)
	* trunk/Xilinx/ddr2_phy_write.v (added)
	* trunk/Xilinx/ddr2_top.v (added)
	* trunk/Xilinx/ddr2_usr_addr_fifo.v (added)
	* trunk/Xilinx/ddr2_usr_rd.v (added)
	* trunk/Xilinx/ddr2_usr_top.v (added)
	* trunk/Xilinx/ddr2_usr_wr.v (added)
	* trunk/Xilinx/dram.v (added)
	* trunk/Xilinx/pll.v (modified)
	* trunk/os2wb/os2wb.v (modified)
	* trunk/os2wb/s1_top.v (modified)
	* trunk/sim (added)
	* trunk/sim/ddr2_model.v (added)
	* trunk/sim/ddr2_model_parameters.vh (added)
	* trunk/sim/sim.do (added)
	* trunk/sim/sim_tb_top.v (added)
	* trunk/sim/sim_tb_top.vhd (added)
	* trunk/sim/wiredly.v (added)
	* trunk/sim/wiredly.vhd (added)
	* trunk/synplicity/proj_1.prj (modified)
	* trunk/synplicity/rev_1/W1.ucf (added)
	* trunk/synplicity/rev_1/dram_fifo.ngc (added)
	* trunk/synplicity/rev_1/pcx_fifo.ngc (added)
	* trunk/synplicity/rev_1/run_ise.tcl (added)
	* trunk/synplicity/rev_1/run_xise.tcl (added)
	* trunk/synplicity/rev_1/synplicity.ucf (added)

	versione sintetizzabile