`timescale 1ns/1ps 
/*module dictatorGate();

module lazyOR (
		// directions
		N,
		E,
		S,
		W,
		//clock status
		status //,
		// rotation
		//R
	       );

module lazyAND (
		// directions
		N,
		E,
		S,
		W,
		//clock status
		status //,
		// rotation
		//R
	       );

module Diode (
		// directions
		N,
		E,
		S,
		W,
		//clock status
		status //,
		// rotation
		//R
	       );

*/
module MQCAcell (
		// directions
		N,
		E,
		S,
		W,
		//clock status
		status //,
		// rotation
		//R
	       );



parameter reset=2'b00;
parameter switch=2'b01;
parameter hold=2'b10;

function integer bintopol; // conversion function from binary to polarization 
input a; //  input argument port 
case (a) 
	1'b0: bintopol = -1; 
	1'b1: bintopol = 1;
	1'bz: bintopol = 0;
	1'bx: bintopol = 32'bz;
	endcase
	endfunction

	function [1:1] compute; // function definition 
	input  N, E, S, W;
	integer 	  polarization;
	begin
	polarization = bintopol(N) + bintopol(S) - 1*(bintopol(E) + bintopol(W));							 
if ( polarization == 0) 
	compute = 1'bz;
else if  ( polarization > 0)
	compute = 1'b1;
	else
	compute = 1'b0;
	end						  
	endfunction // compute


	// //status 00=relax,01=switch, 10=hold, 11=release
	inout N, E, S, W;
	reg Nv, Ev, Sv, Wv;
	input R;
	input [1:0] status;
	reg value;


assign #1 N = (status==reset)?1'bz:(N===1'bz)?value:N;
assign #1 S = (S!==1'bz) ? Sv:S;
assign #1 E = (E!==1'bz) ? Ev:E;
assign #1 W = (W!==1'bz) ? Wv:W;

always @(status,N,S,E,W)
	begin
		if (status == reset)  //hold
			value = 1'bz;
		else if (value===1'bz) 
			value =  compute(N,E,S,W);		
	end
endmodule // QCAcell