#Makefile per Verilog
VERSION = 0.8

all:    progs

mqcawire:
	/usr/local/bin/iverilog -o testbench MQCAcell.v tbMQCAwire.v
	chmod 755 testbench
	
mqcacell:
	/usr/local/bin/iverilog -o testbench MQCAcell.v tbMQCAcell.v
	chmod 755 testbench
progs : 
	/usr/local/bin/iverilog -otestbench *.v
	chmod 755 testbench 

sim:
	./testbench
	/usr/bin/gtkwave dump.vcd wave.sav  
clean	   :       
	rm -f testbench 

# DO NOT DELETE