source: HDLQ/TestBenches/TB.v @ 1

module test_bench;
reg in,fault;
wire out;


Inverter INV (
        .in (in),
        .out(out),
        .fault(fault)
        );
initial  
begin     
        in = 0;     
        fault = 1;
end     
always
     #5 in = !in;

endmodule