Revision 1,
2.4 KB
checked in by ttvmrc00, 14 years ago
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upload iniziale
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Property svn:executable set to
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1 | module test_bench_EXOR; |
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2 | reg in1,in2; |
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3 | reg f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,f15,f16; |
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4 | wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,out,outFaultFree; |
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5 | |
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6 | Fanout Fanout1 ( |
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7 | .in (in1), |
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8 | .out1(w9), |
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9 | .out2(w1), |
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10 | .fault(f1) |
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11 | ); |
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12 | Fanout Fanout2 ( |
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13 | .in (in2), |
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14 | .out1(w4), |
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15 | .out2(w5), |
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16 | .fault(f6) |
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17 | ); |
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18 | LShapedWire LS1 ( |
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19 | .in (w9), |
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20 | .out(w10), |
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21 | .fault(f14) |
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22 | ); |
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23 | LShapedWire LS4 ( |
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24 | .in (w10), |
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25 | .out(w11), |
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26 | .fault(f15) |
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27 | ); |
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28 | LShapedWire LS3 ( |
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29 | .in (w4), |
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30 | .out(w14), |
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31 | .fault(f7) |
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32 | ); |
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33 | LShapedWire LS2 ( |
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34 | .in (w5), |
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35 | .out(w6), |
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36 | .fault(f10) |
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37 | ); |
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38 | LShapedWire LS5 ( |
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39 | .in (w3), |
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40 | .out(w12), |
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41 | .fault(f5) |
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42 | ); |
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43 | LShapedWire LS6 ( |
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44 | .in (w8), |
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45 | .out(w13), |
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46 | .fault(f16) |
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47 | ); |
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48 | |
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49 | Inverter INV1 ( |
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50 | .in (w1), |
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51 | .out(w2), |
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52 | .fault(f2) |
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53 | ); |
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54 | |
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55 | Inverter INV2 ( |
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56 | .in (w6), |
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57 | .out(w7), |
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58 | .fault(f11) |
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59 | ); |
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60 | |
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61 | MajorityVoter MV1 ( |
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62 | .A (w2), |
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63 | .B (0), |
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64 | .C (w14), |
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65 | .out (w3), |
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66 | .fault1 (f4), |
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67 | .fault0 (f3) |
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68 | ); |
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69 | |
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70 | MajorityVoter MV2 ( |
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71 | .A (w7), |
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72 | .B (0), |
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73 | .C (w11), |
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74 | .out (w8), |
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75 | .fault1(f13), |
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76 | .fault0 (f12) |
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77 | ); |
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78 | |
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79 | MajorityVoter MV3 ( |
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80 | .A (w12), |
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81 | .B (1), |
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82 | .C (w13), |
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83 | .out (out), |
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84 | .fault1 (f9), |
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85 | .fault0 (f8) |
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86 | ); |
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87 | |
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88 | |
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89 | xor (outFaultFree, in1,in2); |
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90 | |
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91 | |
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92 | |
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93 | initial |
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94 | begin |
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95 | in1 = 0; |
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96 | in2 = 0; |
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97 | f1 = 0; |
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98 | f2 = 0; |
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99 | f3 = 0; |
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100 | f4 = 0; |
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101 | f5 = 0; |
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102 | f6 = 0; |
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103 | f7 = 0; |
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104 | f8 = 0; |
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105 | f9 = 0; |
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106 | f10 = 0; |
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107 | f11 = 0; |
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108 | f12 = 0; |
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109 | f13 = 0; |
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110 | f14 = 0; |
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111 | f15 = 0; |
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112 | f16 = 0; |
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113 | end |
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114 | |
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115 | // exhaustive stimuli |
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116 | always |
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117 | #5 in1 = !in1; |
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118 | always |
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119 | #10 in2 = !in2; |
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120 | |
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121 | always |
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122 | #20 f1 = !f1; |
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123 | always |
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124 | #40 f2 = !f2; |
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125 | always |
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126 | #80 f3 = !f3; |
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127 | always |
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128 | #160 f4 = !f4; |
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129 | always |
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130 | #320 f5 = !f5; |
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131 | always |
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132 | #640 f6 = !f6; |
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133 | always |
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134 | #1280 f7 = !f7; |
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135 | always |
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136 | #2560 f8 = !f8; |
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137 | always |
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138 | #5120 f9 = !f9; |
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139 | always |
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140 | #10240 f10 = !f10; |
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141 | always |
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142 | #20480 f11 = !f11; |
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143 | always |
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144 | #40960 f12 = !f12; |
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145 | always |
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146 | #81920 f13 = !f13; |
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147 | always |
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148 | #163840 f14 = !f14; |
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149 | always |
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150 | #327680 f15 = !f15; |
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151 | always |
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152 | #655360 f16 = !f16; |
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153 | |
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154 | |
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155 | /* 2 faults stimuli TODO |
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156 | always |
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157 | #5 in1 = !in1; |
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158 | always |
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159 | #10 in2 = !in2; |
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160 | always |
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161 | #20 f1 = !f1; |
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162 | always |
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163 | #40 f2 = !f2; |
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164 | always |
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165 | #80 f3 = !f3; |
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166 | always |
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167 | #160 f4 = !f4; |
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168 | always |
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169 | #320 f5 = !f5; |
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170 | always |
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171 | #640 f6 = !f6; |
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172 | always |
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173 | #1280 f7 = !f7; |
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174 | always |
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175 | #2560 f8 = !f8; |
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176 | always |
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177 | #5120 f9 = !f9; |
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178 | always |
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179 | #10240 f10 = !f10; |
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180 | always |
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181 | #20480 f11 = !f11; |
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182 | always |
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183 | #40960 f12 = !f12; |
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184 | always |
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185 | #81920 f13 = !f13; |
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186 | always |
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187 | #163840 f14 = !f14; |
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188 | always |
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189 | #327680 f15 = !f15; |
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190 | always |
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191 | #655360 f16 = !f16; |
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192 | */ |
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193 | endmodule |
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194 | |
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195 | |
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196 | |
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197 | |
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198 | |
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199 | |
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200 | |
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201 | |
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