source: HDLQ/TestBenches/TBMV.v @ 1

module test_benchMV;
reg a,b,c,fault1,fault0;
wire out;


MajorityVoter MV (
        .A (a),
        .B (b),
        .C (c),
        .out(out),
        .fault1(fault1),
        .fault0(fault0)
        );
initial  
begin     
        a = 0;     
        b = 0;
        c = 0;
        fault1 = 0;
        fault0 = 0;
end     
always
begin
     #5 a = !a;
     #1 a =1'bz;
     #1 a= 1'b1;
end
always
     #10 b = !b;
always
     #20 c = !c;
always
     #40 fault1 = !fault1;
always
     #80 fault0 = !fault0;

endmodule