source: HDLQ/TestBenches/TBMVBI2.v @ 1

module test_benchMV_bi;
reg a,b,fault1,fault0;
wor toZ,toZp;
reg ck,d;
reg regtoZ, regtoZp;
reg [1:0] zone2,zone1;
MajorityVoter_bi4 MV (
        .status (zone2),
        .A(a),
        .B(b),
        .Z(toZ),
        .Zp(toZp),
        .fault1(fault1),
        .fault0(fault0)
        );
assign toZp = regtoZp;
assign toZ  = regtoZ;
initial  
begin     
        a = 0;     
        b = 1;
        fault1 = 0;
        fault0 = 0;
        zone2=2'b00;
        regtoZp=1;
        regtoZ=1'bz;
end     

always
 begin
  #5 zone2 =zone2+1;
 end            
always
begin
  #12.5 regtoZp <= 1'bz;
  #30 regtoZp <= 1;
  #10 regtoZp=1'bz;
end
always 
begin
  #27 regtoZ <=0; 
  #17.5 regtoZ <=1;
  #7.5  regtoZ <=1'bz;
end

endmodule