source: HDLQ/TestBenches/TBWIREb.v @ 1

module test_bench_wireb ;
reg a; 
reg [1:0]status;
reg b;

Wire_bi3 w1(
        .A(in), 
        .B(out), 
        .status(status)
        );
//assign  in = (status == 2'b10 )? 1'bz :a;
assign in = a ;
assign  out = b;
initial
begin
status=2'b0;
a=1;
b=1'bz;
end
always 
 #5 status <= status +1;
always
begin
#12.5  a <= 1'bz;
#25 a <= 1;
// #10 a<=  1;
// #12 a<=  0;
end
always
begin
#17.5 b<=0;
#12 b<=1;
#5b<=1'bz;
end
endmodule