1 | ////////////////////////////////////////////////////////////////////// |
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2 | //// //// |
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3 | //// eth_maccontrol.v //// |
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4 | //// //// |
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5 | //// This file is part of the Ethernet IP core project //// |
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6 | //// http://www.opencores.org/projects/ethmac/ //// |
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7 | //// //// |
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8 | //// Author(s): //// |
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9 | //// - Igor Mohor (igorM@opencores.org) //// |
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10 | //// //// |
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11 | //// All additional information is avaliable in the Readme.txt //// |
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12 | //// file. //// |
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13 | //// //// |
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14 | ////////////////////////////////////////////////////////////////////// |
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15 | //// //// |
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16 | //// Copyright (C) 2001 Authors //// |
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17 | //// //// |
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18 | //// This source file may be used and distributed without //// |
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19 | //// restriction provided that this copyright statement is not //// |
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20 | //// removed from the file and that any derivative work contains //// |
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21 | //// the original copyright notice and the associated disclaimer. //// |
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22 | //// //// |
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23 | //// This source file is free software; you can redistribute it //// |
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24 | //// and/or modify it under the terms of the GNU Lesser General //// |
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25 | //// Public License as published by the Free Software Foundation; //// |
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26 | //// either version 2.1 of the License, or (at your option) any //// |
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27 | //// later version. //// |
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28 | //// //// |
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29 | //// This source is distributed in the hope that it will be //// |
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30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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32 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
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33 | //// details. //// |
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34 | //// //// |
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35 | //// You should have received a copy of the GNU Lesser General //// |
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36 | //// Public License along with this source; if not, download it //// |
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37 | //// from http://www.opencores.org/lgpl.shtml //// |
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38 | //// //// |
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39 | ////////////////////////////////////////////////////////////////////// |
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40 | // |
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41 | // CVS Revision History |
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42 | // |
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43 | // $Log: not supported by cvs2svn $ |
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44 | // Revision 1.6 2002/11/22 01:57:06 mohor |
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45 | // Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
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46 | // synchronized. |
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47 | // |
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48 | // Revision 1.5 2002/11/21 00:14:39 mohor |
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49 | // TxDone and TxAbort changed so they're not propagated to the wishbone |
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50 | // module when control frame is transmitted. |
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51 | // |
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52 | // Revision 1.4 2002/11/19 17:37:32 mohor |
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53 | // When control frame (PAUSE) was sent, status was written in the |
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54 | // eth_wishbone module and both TXB and TXC interrupts were set. Fixed. |
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55 | // Only TXC interrupt is set. |
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56 | // |
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57 | // Revision 1.3 2002/01/23 10:28:16 mohor |
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58 | // Link in the header changed. |
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59 | // |
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60 | // Revision 1.2 2001/10/19 08:43:51 mohor |
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61 | // eth_timescale.v changed to timescale.v This is done because of the |
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62 | // simulation of the few cores in a one joined project. |
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63 | // |
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64 | // Revision 1.1 2001/08/06 14:44:29 mohor |
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65 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
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66 | // Include files fixed to contain no path. |
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67 | // File names and module names changed ta have a eth_ prologue in the name. |
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68 | // File eth_timescale.v is used to define timescale |
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69 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. |
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70 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
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71 | // and Mdo_OE. The bidirectional signal must be created on the top level. This |
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72 | // is done due to the ASIC tools. |
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73 | // |
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74 | // Revision 1.1 2001/07/30 21:23:42 mohor |
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75 | // Directory structure changed. Files checked and joind together. |
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76 | // |
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77 | // Revision 1.1 2001/07/03 12:51:54 mohor |
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78 | // Initial release of the MAC Control module. |
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79 | // |
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80 | // |
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81 | // |
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82 | // |
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83 | |
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84 | |
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85 | `include "timescale.v" |
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86 | |
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87 | |
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88 | module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn, |
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89 | TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd, |
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90 | ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV, |
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91 | MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut, |
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92 | TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm, |
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93 | ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2 |
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94 | ); |
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95 | |
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96 | |
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97 | parameter Tp = 1; |
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98 | |
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99 | |
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100 | input MTxClk; // Transmit clock (from PHY) |
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101 | input MRxClk; // Receive clock (from PHY) |
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102 | input TxReset; // Transmit reset |
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103 | input RxReset; // Receive reset |
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104 | input TPauseRq; // Transmit control frame (from host) |
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105 | input [7:0] TxDataIn; // Transmit packet data byte (from host) |
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106 | input TxStartFrmIn; // Transmit packet start frame input (from host) |
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107 | input TxUsedDataIn; // Transmit packet used data (from TxEthMAC) |
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108 | input TxEndFrmIn; // Transmit packet end frame input (from host) |
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109 | input TxDoneIn; // Transmit packet done (from TxEthMAC) |
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110 | input TxAbortIn; // Transmit packet abort (input from TxEthMAC) |
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111 | input PadIn; // Padding (input from registers) |
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112 | input CrcEnIn; // Crc append (input from registers) |
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113 | input [7:0] RxData; // Receive Packet Data (from RxEthMAC) |
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114 | input RxValid; // Received a valid packet |
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115 | input RxStartFrm; // Receive packet start frame (input from RxEthMAC) |
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116 | input RxEndFrm; // Receive packet end frame (input from RxEthMAC) |
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117 | input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC) |
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118 | input ReceivedPacketGood; // Received packet is good |
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119 | input ReceivedLengthOK; // Length of the received packet is OK |
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120 | input TxFlow; // Tx flow control (from registers) |
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121 | input RxFlow; // Rx flow control (from registers) |
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122 | input DlyCrcEn; // Delayed CRC enabled (from registers) |
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123 | input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers) |
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124 | input [47:0] MAC; // MAC address (from registers) |
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125 | input RxStatusWriteLatched_sync2; |
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126 | input r_PassAll; |
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127 | |
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128 | output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC) |
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129 | output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC) |
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130 | output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC) |
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131 | output TxDoneOut; // Transmit packet done (to host) |
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132 | output TxAbortOut; // Transmit packet aborted (to host) |
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133 | output TxUsedDataOut; // Transmit packet used data (to host) |
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134 | output PadOut; // Padding (output to TxEthMAC) |
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135 | output CrcEnOut; // Crc append (output to TxEthMAC) |
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136 | output WillSendControlFrame; |
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137 | output TxCtrlEndFrm; |
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138 | output ReceivedPauseFrm; |
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139 | output ControlFrmAddressOK; |
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140 | output SetPauseTimer; |
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141 | |
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142 | reg TxUsedDataOutDetected; |
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143 | reg TxAbortInLatched; |
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144 | reg TxDoneInLatched; |
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145 | reg MuxedDone; |
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146 | reg MuxedAbort; |
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147 | |
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148 | wire Pause; |
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149 | wire TxCtrlStartFrm; |
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150 | wire [7:0] ControlData; |
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151 | wire CtrlMux; |
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152 | wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC) |
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153 | wire BlockTxDone; |
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154 | |
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155 | |
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156 | // Signal TxUsedDataOut was detected (a transfer is already in progress) |
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157 | always @ (posedge MTxClk or posedge TxReset) |
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158 | begin |
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159 | if(TxReset) |
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160 | TxUsedDataOutDetected <= #Tp 1'b0; |
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161 | else |
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162 | if(TxDoneIn | TxAbortIn) |
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163 | TxUsedDataOutDetected <= #Tp 1'b0; |
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164 | else |
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165 | if(TxUsedDataOut) |
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166 | TxUsedDataOutDetected <= #Tp 1'b1; |
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167 | end |
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168 | |
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169 | |
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170 | // Latching variables |
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171 | always @ (posedge MTxClk or posedge TxReset) |
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172 | begin |
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173 | if(TxReset) |
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174 | begin |
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175 | TxAbortInLatched <= #Tp 1'b0; |
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176 | TxDoneInLatched <= #Tp 1'b0; |
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177 | end |
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178 | else |
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179 | begin |
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180 | TxAbortInLatched <= #Tp TxAbortIn; |
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181 | TxDoneInLatched <= #Tp TxDoneIn; |
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182 | end |
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183 | end |
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184 | |
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185 | |
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186 | |
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187 | // Generating muxed abort signal |
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188 | always @ (posedge MTxClk or posedge TxReset) |
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189 | begin |
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190 | if(TxReset) |
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191 | MuxedAbort <= #Tp 1'b0; |
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192 | else |
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193 | if(TxStartFrmIn) |
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194 | MuxedAbort <= #Tp 1'b0; |
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195 | else |
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196 | if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected) |
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197 | MuxedAbort <= #Tp 1'b1; |
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198 | end |
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199 | |
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200 | |
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201 | // Generating muxed done signal |
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202 | always @ (posedge MTxClk or posedge TxReset) |
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203 | begin |
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204 | if(TxReset) |
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205 | MuxedDone <= #Tp 1'b0; |
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206 | else |
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207 | if(TxStartFrmIn) |
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208 | MuxedDone <= #Tp 1'b0; |
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209 | else |
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210 | if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected) |
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211 | MuxedDone <= #Tp 1'b1; |
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212 | end |
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213 | |
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214 | |
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215 | // TxDoneOut |
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216 | assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) : |
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217 | ((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn); |
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218 | |
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219 | // TxAbortOut |
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220 | assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) : |
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221 | ((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn); |
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222 | |
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223 | // TxUsedDataOut |
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224 | assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn; |
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225 | |
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226 | // TxStartFrmOut |
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227 | assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause); |
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228 | |
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229 | |
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230 | // TxEndFrmOut |
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231 | assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn; |
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232 | |
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233 | |
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234 | // TxDataOut[7:0] |
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235 | assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0]; |
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236 | |
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237 | |
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238 | // PadOut |
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239 | assign PadOut = PadIn | SendingCtrlFrm; |
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240 | |
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241 | |
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242 | // CrcEnOut |
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243 | assign CrcEnOut = CrcEnIn | SendingCtrlFrm; |
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244 | |
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245 | |
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246 | |
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247 | // Connecting receivecontrol module |
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248 | eth_receivecontrol receivecontrol1 |
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249 | ( |
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250 | .MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData), |
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251 | .RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow), |
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252 | .ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn), |
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253 | .TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK), |
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254 | .ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected), |
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255 | .Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK), |
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256 | .r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer) |
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257 | ); |
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258 | |
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259 | |
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260 | eth_transmitcontrol transmitcontrol1 |
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261 | ( |
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262 | .MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut), |
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263 | .TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq), |
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264 | .TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV), |
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265 | .MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm), |
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266 | .CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone) |
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267 | ); |
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268 | |
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269 | |
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270 | |
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271 | endmodule |
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