[6] | 1 | ////////////////////////////////////////////////////////////////////// |
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| 2 | //// //// |
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| 3 | //// eth_miim.v //// |
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| 4 | //// //// |
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| 5 | //// This file is part of the Ethernet IP core project //// |
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| 6 | //// http://www.opencores.org/projects/ethmac/ //// |
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| 7 | //// //// |
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| 8 | //// Author(s): //// |
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| 9 | //// - Igor Mohor (igorM@opencores.org) //// |
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| 10 | //// //// |
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| 11 | //// All additional information is avaliable in the Readme.txt //// |
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| 12 | //// file. //// |
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| 13 | //// //// |
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| 14 | ////////////////////////////////////////////////////////////////////// |
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| 15 | //// //// |
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| 16 | //// Copyright (C) 2001 Authors //// |
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| 17 | //// //// |
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| 18 | //// This source file may be used and distributed without //// |
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| 19 | //// restriction provided that this copyright statement is not //// |
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| 20 | //// removed from the file and that any derivative work contains //// |
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| 21 | //// the original copyright notice and the associated disclaimer. //// |
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| 22 | //// //// |
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| 23 | //// This source file is free software; you can redistribute it //// |
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| 24 | //// and/or modify it under the terms of the GNU Lesser General //// |
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| 25 | //// Public License as published by the Free Software Foundation; //// |
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| 26 | //// either version 2.1 of the License, or (at your option) any //// |
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| 27 | //// later version. //// |
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| 28 | //// //// |
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| 29 | //// This source is distributed in the hope that it will be //// |
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| 30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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| 31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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| 32 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
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| 33 | //// details. //// |
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| 34 | //// //// |
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| 35 | //// You should have received a copy of the GNU Lesser General //// |
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| 36 | //// Public License along with this source; if not, download it //// |
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| 37 | //// from http://www.opencores.org/lgpl.shtml //// |
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| 38 | //// //// |
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| 39 | ////////////////////////////////////////////////////////////////////// |
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| 40 | // |
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| 41 | // CVS Revision History |
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| 42 | // |
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| 43 | // $Log: not supported by cvs2svn $ |
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| 44 | // Revision 1.6 2005/02/21 12:48:07 igorm |
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| 45 | // Warning fixes. |
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| 46 | // |
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| 47 | // Revision 1.5 2003/05/16 10:08:27 mohor |
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| 48 | // Busy was set 2 cycles too late. Reported by Dennis Scott. |
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| 49 | // |
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| 50 | // Revision 1.4 2002/08/14 18:32:10 mohor |
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| 51 | // - Busy signal was not set on time when scan status operation was performed |
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| 52 | // and clock was divided with more than 2. |
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| 53 | // - Nvalid remains valid two more clocks (was previously cleared too soon). |
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| 54 | // |
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| 55 | // Revision 1.3 2002/01/23 10:28:16 mohor |
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| 56 | // Link in the header changed. |
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| 57 | // |
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| 58 | // Revision 1.2 2001/10/19 08:43:51 mohor |
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| 59 | // eth_timescale.v changed to timescale.v This is done because of the |
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| 60 | // simulation of the few cores in a one joined project. |
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| 61 | // |
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| 62 | // Revision 1.1 2001/08/06 14:44:29 mohor |
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| 63 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
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| 64 | // Include files fixed to contain no path. |
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| 65 | // File names and module names changed ta have a eth_ prologue in the name. |
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| 66 | // File eth_timescale.v is used to define timescale |
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| 67 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. |
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| 68 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
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| 69 | // and Mdo_OE. The bidirectional signal must be created on the top level. This |
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| 70 | // is done due to the ASIC tools. |
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| 71 | // |
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| 72 | // Revision 1.2 2001/08/02 09:25:31 mohor |
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| 73 | // Unconnected signals are now connected. |
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| 74 | // |
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| 75 | // Revision 1.1 2001/07/30 21:23:42 mohor |
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| 76 | // Directory structure changed. Files checked and joind together. |
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| 77 | // |
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| 78 | // Revision 1.3 2001/06/01 22:28:56 mohor |
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| 79 | // This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. |
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| 80 | // |
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| 81 | // |
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| 82 | |
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| 83 | `include "timescale.v" |
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| 84 | |
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| 85 | |
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| 86 | module eth_miim |
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| 87 | ( |
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| 88 | Clk, |
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| 89 | Reset, |
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| 90 | Divider, |
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| 91 | NoPre, |
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| 92 | CtrlData, |
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| 93 | Rgad, |
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| 94 | Fiad, |
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| 95 | WCtrlData, |
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| 96 | RStat, |
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| 97 | ScanStat, |
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| 98 | Mdi, |
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| 99 | Mdo, |
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| 100 | MdoEn, |
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| 101 | Mdc, |
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| 102 | Busy, |
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| 103 | Prsd, |
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| 104 | LinkFail, |
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| 105 | Nvalid, |
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| 106 | WCtrlDataStart, |
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| 107 | RStatStart, |
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| 108 | UpdateMIIRX_DATAReg |
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| 109 | ); |
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| 110 | |
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| 111 | |
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| 112 | |
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| 113 | input Clk; // Host Clock |
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| 114 | input Reset; // General Reset |
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| 115 | input [7:0] Divider; // Divider for the host clock |
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| 116 | input [15:0] CtrlData; // Control Data (to be written to the PHY reg.) |
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| 117 | input [4:0] Rgad; // Register Address (within the PHY) |
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| 118 | input [4:0] Fiad; // PHY Address |
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| 119 | input NoPre; // No Preamble (no 32-bit preamble) |
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| 120 | input WCtrlData; // Write Control Data operation |
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| 121 | input RStat; // Read Status operation |
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| 122 | input ScanStat; // Scan Status operation |
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| 123 | input Mdi; // MII Management Data In |
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| 124 | |
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| 125 | output Mdc; // MII Management Data Clock |
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| 126 | output Mdo; // MII Management Data Output |
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| 127 | output MdoEn; // MII Management Data Output Enable |
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| 128 | output Busy; // Busy Signal |
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| 129 | output LinkFail; // Link Integrity Signal |
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| 130 | output Nvalid; // Invalid Status (qualifier for the valid scan result) |
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| 131 | |
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| 132 | output [15:0] Prsd; // Read Status Data (data read from the PHY) |
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| 133 | |
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| 134 | output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register |
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| 135 | output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register |
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| 136 | output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data |
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| 137 | |
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| 138 | parameter Tp = 1; |
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| 139 | |
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| 140 | |
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| 141 | reg Nvalid; |
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| 142 | reg EndBusy_d; // Pre-end Busy signal |
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| 143 | reg EndBusy; // End Busy signal (stops the operation in progress) |
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| 144 | |
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| 145 | reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle |
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| 146 | reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles |
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| 147 | reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles |
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| 148 | reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected) |
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| 149 | reg WCtrlDataStart_q; |
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| 150 | reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle |
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| 151 | reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles |
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| 152 | |
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| 153 | reg RStat_q1; // Read Status operation delayed 1 Clk cycle |
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| 154 | reg RStat_q2; // Read Status operation delayed 2 Clk cycles |
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| 155 | reg RStat_q3; // Read Status operation delayed 3 Clk cycles |
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| 156 | reg RStatStart; // Start Read Status Command (positive edge detected) |
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| 157 | reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle |
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| 158 | reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles |
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| 159 | |
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| 160 | reg ScanStat_q1; // Scan Status operation delayed 1 cycle |
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| 161 | reg ScanStat_q2; // Scan Status operation delayed 2 cycles |
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| 162 | reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn |
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| 163 | |
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| 164 | wire WriteDataOp; // Write Data Operation (positive edge detected) |
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| 165 | wire ReadStatusOp; // Read Status Operation (positive edge detected) |
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| 166 | wire ScanStatusOp; // Scan Status Operation (positive edge detected) |
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| 167 | wire StartOp; // Start Operation (start of any of the preceding operations) |
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| 168 | wire EndOp; // End of Operation |
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| 169 | |
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| 170 | reg InProgress; // Operation in progress |
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| 171 | reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle |
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| 172 | reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles |
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| 173 | reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles |
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| 174 | |
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| 175 | reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress) |
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| 176 | reg [6:0] BitCounter; // Bit Counter |
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| 177 | |
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| 178 | |
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| 179 | wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register. |
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| 180 | wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises. |
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| 181 | wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal |
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| 182 | wire MdcEn_n; |
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| 183 | |
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| 184 | wire LatchByte1_d2; |
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| 185 | wire LatchByte0_d2; |
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| 186 | reg LatchByte1_d; |
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| 187 | reg LatchByte0_d; |
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| 188 | reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register |
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| 189 | |
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| 190 | reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data |
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| 191 | |
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| 192 | |
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| 193 | |
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| 194 | |
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| 195 | |
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| 196 | // Generation of the EndBusy signal. It is used for ending the MII Management operation. |
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| 197 | always @ (posedge Clk or posedge Reset) |
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| 198 | begin |
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| 199 | if(Reset) |
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| 200 | begin |
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| 201 | EndBusy_d <= #Tp 1'b0; |
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| 202 | EndBusy <= #Tp 1'b0; |
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| 203 | end |
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| 204 | else |
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| 205 | begin |
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| 206 | EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3; |
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| 207 | EndBusy <= #Tp EndBusy_d; |
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| 208 | end |
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| 209 | end |
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| 210 | |
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| 211 | |
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| 212 | // Update MII RX_DATA register |
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| 213 | always @ (posedge Clk or posedge Reset) |
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| 214 | begin |
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| 215 | if(Reset) |
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| 216 | UpdateMIIRX_DATAReg <= #Tp 0; |
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| 217 | else |
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| 218 | if(EndBusy & ~WCtrlDataStart_q) |
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| 219 | UpdateMIIRX_DATAReg <= #Tp 1; |
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| 220 | else |
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| 221 | UpdateMIIRX_DATAReg <= #Tp 0; |
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| 222 | end |
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| 223 | |
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| 224 | |
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| 225 | |
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| 226 | // Generation of the delayed signals used for positive edge triggering. |
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| 227 | always @ (posedge Clk or posedge Reset) |
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| 228 | begin |
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| 229 | if(Reset) |
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| 230 | begin |
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| 231 | WCtrlData_q1 <= #Tp 1'b0; |
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| 232 | WCtrlData_q2 <= #Tp 1'b0; |
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| 233 | WCtrlData_q3 <= #Tp 1'b0; |
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| 234 | |
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| 235 | RStat_q1 <= #Tp 1'b0; |
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| 236 | RStat_q2 <= #Tp 1'b0; |
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| 237 | RStat_q3 <= #Tp 1'b0; |
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| 238 | |
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| 239 | ScanStat_q1 <= #Tp 1'b0; |
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| 240 | ScanStat_q2 <= #Tp 1'b0; |
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| 241 | SyncStatMdcEn <= #Tp 1'b0; |
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| 242 | end |
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| 243 | else |
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| 244 | begin |
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| 245 | WCtrlData_q1 <= #Tp WCtrlData; |
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| 246 | WCtrlData_q2 <= #Tp WCtrlData_q1; |
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| 247 | WCtrlData_q3 <= #Tp WCtrlData_q2; |
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| 248 | |
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| 249 | RStat_q1 <= #Tp RStat; |
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| 250 | RStat_q2 <= #Tp RStat_q1; |
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| 251 | RStat_q3 <= #Tp RStat_q2; |
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| 252 | |
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| 253 | ScanStat_q1 <= #Tp ScanStat; |
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| 254 | ScanStat_q2 <= #Tp ScanStat_q1; |
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| 255 | if(MdcEn) |
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| 256 | SyncStatMdcEn <= #Tp ScanStat_q2; |
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| 257 | end |
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| 258 | end |
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| 259 | |
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| 260 | |
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| 261 | // Generation of the Start Commands (Write Control Data or Read Status) |
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| 262 | always @ (posedge Clk or posedge Reset) |
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| 263 | begin |
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| 264 | if(Reset) |
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| 265 | begin |
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| 266 | WCtrlDataStart <= #Tp 1'b0; |
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| 267 | WCtrlDataStart_q <= #Tp 1'b0; |
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| 268 | RStatStart <= #Tp 1'b0; |
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| 269 | end |
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| 270 | else |
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| 271 | begin |
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| 272 | if(EndBusy) |
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| 273 | begin |
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| 274 | WCtrlDataStart <= #Tp 1'b0; |
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| 275 | RStatStart <= #Tp 1'b0; |
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| 276 | end |
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| 277 | else |
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| 278 | begin |
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| 279 | if(WCtrlData_q2 & ~WCtrlData_q3) |
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| 280 | WCtrlDataStart <= #Tp 1'b1; |
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| 281 | if(RStat_q2 & ~RStat_q3) |
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| 282 | RStatStart <= #Tp 1'b1; |
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| 283 | WCtrlDataStart_q <= #Tp WCtrlDataStart; |
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| 284 | end |
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| 285 | end |
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| 286 | end |
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| 287 | |
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| 288 | |
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| 289 | // Generation of the Nvalid signal (indicates when the status is invalid) |
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| 290 | always @ (posedge Clk or posedge Reset) |
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| 291 | begin |
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| 292 | if(Reset) |
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| 293 | Nvalid <= #Tp 1'b0; |
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| 294 | else |
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| 295 | begin |
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| 296 | if(~InProgress_q2 & InProgress_q3) |
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| 297 | begin |
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| 298 | Nvalid <= #Tp 1'b0; |
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| 299 | end |
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| 300 | else |
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| 301 | begin |
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| 302 | if(ScanStat_q2 & ~SyncStatMdcEn) |
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| 303 | Nvalid <= #Tp 1'b1; |
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| 304 | end |
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| 305 | end |
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| 306 | end |
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| 307 | |
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| 308 | // Signals used for the generation of the Operation signals (positive edge) |
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| 309 | always @ (posedge Clk or posedge Reset) |
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| 310 | begin |
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| 311 | if(Reset) |
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| 312 | begin |
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| 313 | WCtrlDataStart_q1 <= #Tp 1'b0; |
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| 314 | WCtrlDataStart_q2 <= #Tp 1'b0; |
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| 315 | |
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| 316 | RStatStart_q1 <= #Tp 1'b0; |
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| 317 | RStatStart_q2 <= #Tp 1'b0; |
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| 318 | |
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| 319 | InProgress_q1 <= #Tp 1'b0; |
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| 320 | InProgress_q2 <= #Tp 1'b0; |
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| 321 | InProgress_q3 <= #Tp 1'b0; |
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| 322 | |
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| 323 | LatchByte0_d <= #Tp 1'b0; |
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| 324 | LatchByte1_d <= #Tp 1'b0; |
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| 325 | |
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| 326 | LatchByte <= #Tp 2'b00; |
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| 327 | end |
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| 328 | else |
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| 329 | begin |
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| 330 | if(MdcEn) |
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| 331 | begin |
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| 332 | WCtrlDataStart_q1 <= #Tp WCtrlDataStart; |
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| 333 | WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1; |
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| 334 | |
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| 335 | RStatStart_q1 <= #Tp RStatStart; |
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| 336 | RStatStart_q2 <= #Tp RStatStart_q1; |
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| 337 | |
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| 338 | LatchByte[0] <= #Tp LatchByte0_d; |
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| 339 | LatchByte[1] <= #Tp LatchByte1_d; |
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| 340 | |
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| 341 | LatchByte0_d <= #Tp LatchByte0_d2; |
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| 342 | LatchByte1_d <= #Tp LatchByte1_d2; |
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| 343 | |
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| 344 | InProgress_q1 <= #Tp InProgress; |
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| 345 | InProgress_q2 <= #Tp InProgress_q1; |
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| 346 | InProgress_q3 <= #Tp InProgress_q2; |
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| 347 | end |
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| 348 | end |
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| 349 | end |
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| 350 | |
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| 351 | |
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| 352 | // Generation of the Operation signals |
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| 353 | assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2; |
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| 354 | assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2; |
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| 355 | assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2; |
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| 356 | assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp; |
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| 357 | |
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| 358 | // Busy |
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| 359 | assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid; |
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| 360 | |
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| 361 | |
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| 362 | // Generation of the InProgress signal (indicates when an operation is in progress) |
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| 363 | // Generation of the WriteOp signal (indicates when a write is in progress) |
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| 364 | always @ (posedge Clk or posedge Reset) |
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| 365 | begin |
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| 366 | if(Reset) |
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| 367 | begin |
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| 368 | InProgress <= #Tp 1'b0; |
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| 369 | WriteOp <= #Tp 1'b0; |
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| 370 | end |
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| 371 | else |
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| 372 | begin |
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| 373 | if(MdcEn) |
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| 374 | begin |
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| 375 | if(StartOp) |
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| 376 | begin |
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| 377 | if(~InProgress) |
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| 378 | WriteOp <= #Tp WriteDataOp; |
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| 379 | InProgress <= #Tp 1'b1; |
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| 380 | end |
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| 381 | else |
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| 382 | begin |
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| 383 | if(EndOp) |
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| 384 | begin |
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| 385 | InProgress <= #Tp 1'b0; |
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| 386 | WriteOp <= #Tp 1'b0; |
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| 387 | end |
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| 388 | end |
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| 389 | end |
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| 390 | end |
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| 391 | end |
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| 392 | |
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| 393 | |
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| 394 | |
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| 395 | // Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted) |
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| 396 | always @ (posedge Clk or posedge Reset) |
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| 397 | begin |
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| 398 | if(Reset) |
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| 399 | BitCounter[6:0] <= #Tp 7'h0; |
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| 400 | else |
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| 401 | begin |
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| 402 | if(MdcEn) |
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| 403 | begin |
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| 404 | if(InProgress) |
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| 405 | begin |
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| 406 | if(NoPre & ( BitCounter == 7'h0 )) |
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| 407 | BitCounter[6:0] <= #Tp 7'h21; |
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| 408 | else |
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| 409 | BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1; |
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| 410 | end |
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| 411 | else |
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| 412 | BitCounter[6:0] <= #Tp 7'h0; |
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| 413 | end |
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| 414 | end |
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| 415 | end |
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| 416 | |
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| 417 | |
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| 418 | // Operation ends when the Bit Counter reaches 63 |
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| 419 | assign EndOp = BitCounter==63; |
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| 420 | |
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| 421 | assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20))); |
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| 422 | assign ByteSelect[1] = InProgress & (BitCounter == 7'h28); |
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| 423 | assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30); |
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| 424 | assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38); |
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| 425 | |
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| 426 | |
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| 427 | // Latch Byte selects which part of Read Status Data is updated from the shift register |
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| 428 | assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37; |
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| 429 | assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F; |
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| 430 | |
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| 431 | |
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| 432 | // Connecting the Clock Generator Module |
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| 433 | eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) |
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| 434 | ); |
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| 435 | |
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| 436 | // Connecting the Shift Register Module |
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| 437 | eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), |
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| 438 | .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), |
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| 439 | .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail) |
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| 440 | ); |
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| 441 | |
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| 442 | // Connecting the Output Control Module |
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| 443 | eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), |
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| 444 | .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), |
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| 445 | .Mdo(Mdo), .MdoEn(MdoEn) |
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| 446 | ); |
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| 447 | |
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| 448 | endmodule |
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