1 | ////////////////////////////////////////////////////////////////////// |
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2 | //// //// |
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3 | //// eth_register.v //// |
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4 | //// //// |
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5 | //// This file is part of the Ethernet IP core project //// |
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6 | //// http://www.opencores.org/projects/ethmac/ //// |
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7 | //// //// |
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8 | //// Author(s): //// |
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9 | //// - Igor Mohor (igorM@opencores.org) //// |
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10 | //// //// |
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11 | //// All additional information is avaliable in the Readme.txt //// |
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12 | //// file. //// |
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13 | //// //// |
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14 | ////////////////////////////////////////////////////////////////////// |
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15 | //// //// |
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16 | //// Copyright (C) 2001, 2002 Authors //// |
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17 | //// //// |
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18 | //// This source file may be used and distributed without //// |
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19 | //// restriction provided that this copyright statement is not //// |
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20 | //// removed from the file and that any derivative work contains //// |
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21 | //// the original copyright notice and the associated disclaimer. //// |
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22 | //// //// |
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23 | //// This source file is free software; you can redistribute it //// |
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24 | //// and/or modify it under the terms of the GNU Lesser General //// |
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25 | //// Public License as published by the Free Software Foundation; //// |
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26 | //// either version 2.1 of the License, or (at your option) any //// |
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27 | //// later version. //// |
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28 | //// //// |
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29 | //// This source is distributed in the hope that it will be //// |
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30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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32 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
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33 | //// details. //// |
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34 | //// //// |
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35 | //// You should have received a copy of the GNU Lesser General //// |
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36 | //// Public License along with this source; if not, download it //// |
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37 | //// from http://www.opencores.org/lgpl.shtml //// |
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38 | //// //// |
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39 | ////////////////////////////////////////////////////////////////////// |
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40 | // |
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41 | // CVS Revision History |
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42 | // |
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43 | // $Log: not supported by cvs2svn $ |
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44 | // Revision 1.5 2002/08/16 12:33:27 mohor |
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45 | // Parameter ResetValue changed to capital letters. |
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46 | // |
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47 | // Revision 1.4 2002/02/26 16:18:08 mohor |
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48 | // Reset values are passed to registers through parameters |
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49 | // |
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50 | // Revision 1.3 2002/01/23 10:28:16 mohor |
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51 | // Link in the header changed. |
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52 | // |
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53 | // Revision 1.2 2001/10/19 08:43:51 mohor |
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54 | // eth_timescale.v changed to timescale.v This is done because of the |
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55 | // simulation of the few cores in a one joined project. |
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56 | // |
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57 | // Revision 1.1 2001/08/06 14:44:29 mohor |
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58 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
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59 | // Include files fixed to contain no path. |
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60 | // File names and module names changed ta have a eth_ prologue in the name. |
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61 | // File eth_timescale.v is used to define timescale |
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62 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. |
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63 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
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64 | // and Mdo_OE. The bidirectional signal must be created on the top level. This |
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65 | // is done due to the ASIC tools. |
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66 | // |
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67 | // |
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68 | // |
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69 | // |
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70 | // |
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71 | // |
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72 | // |
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73 | |
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74 | `include "timescale.v" |
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75 | |
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76 | |
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77 | module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset); |
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78 | |
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79 | parameter WIDTH = 8; // default parameter of the register width |
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80 | parameter RESET_VALUE = 0; |
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81 | |
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82 | input [WIDTH-1:0] DataIn; |
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83 | |
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84 | input Write; |
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85 | input Clk; |
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86 | input Reset; |
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87 | input SyncReset; |
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88 | |
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89 | output [WIDTH-1:0] DataOut; |
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90 | reg [WIDTH-1:0] DataOut; |
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91 | |
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92 | |
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93 | |
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94 | always @ (posedge Clk or posedge Reset) |
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95 | begin |
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96 | if(Reset) |
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97 | DataOut<=#1 RESET_VALUE; |
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98 | else |
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99 | if(SyncReset) |
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100 | DataOut<=#1 RESET_VALUE; |
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101 | else |
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102 | if(Write) // write |
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103 | DataOut<=#1 DataIn; |
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104 | end |
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105 | |
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106 | |
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107 | |
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108 | endmodule // Register |
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