1 | ////////////////////////////////////////////////////////////////////// |
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2 | //// //// |
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3 | //// eth_registers.v //// |
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4 | //// //// |
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5 | //// This file is part of the Ethernet IP core project //// |
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6 | //// http://www.opencores.org/projects/ethmac/ //// |
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7 | //// //// |
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8 | //// Author(s): //// |
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9 | //// - Igor Mohor (igorM@opencores.org) //// |
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10 | //// //// |
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11 | //// All additional information is avaliable in the Readme.txt //// |
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12 | //// file. //// |
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13 | //// //// |
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14 | ////////////////////////////////////////////////////////////////////// |
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15 | //// //// |
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16 | //// Copyright (C) 2001, 2002 Authors //// |
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17 | //// //// |
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18 | //// This source file may be used and distributed without //// |
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19 | //// restriction provided that this copyright statement is not //// |
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20 | //// removed from the file and that any derivative work contains //// |
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21 | //// the original copyright notice and the associated disclaimer. //// |
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22 | //// //// |
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23 | //// This source file is free software; you can redistribute it //// |
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24 | //// and/or modify it under the terms of the GNU Lesser General //// |
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25 | //// Public License as published by the Free Software Foundation; //// |
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26 | //// either version 2.1 of the License, or (at your option) any //// |
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27 | //// later version. //// |
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28 | //// //// |
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29 | //// This source is distributed in the hope that it will be //// |
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30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
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31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
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32 | //// PURPOSE. See the GNU Lesser General Public License for more //// |
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33 | //// details. //// |
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34 | //// //// |
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35 | //// You should have received a copy of the GNU Lesser General //// |
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36 | //// Public License along with this source; if not, download it //// |
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37 | //// from http://www.opencores.org/lgpl.shtml //// |
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38 | //// //// |
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39 | ////////////////////////////////////////////////////////////////////// |
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40 | // |
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41 | // CVS Revision History |
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42 | // |
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43 | // $Log: not supported by cvs2svn $ |
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44 | // Revision 1.28 2004/04/26 15:26:23 igorm |
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45 | // - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the |
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46 | // previous update of the core. |
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47 | // - TxBDAddress is set to 0 after the TX is enabled in the MODER register. |
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48 | // - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER |
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49 | // register. (thanks to Mathias and Torbjorn) |
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50 | // - Multicast reception was fixed. Thanks to Ulrich Gries |
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51 | // |
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52 | // Revision 1.27 2004/04/26 11:42:17 igorm |
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53 | // TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. |
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54 | // |
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55 | // Revision 1.26 2003/11/12 18:24:59 tadejm |
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56 | // WISHBONE slave changed and tested from only 32-bit accesss to byte access. |
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57 | // |
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58 | // Revision 1.25 2003/04/18 16:26:25 mohor |
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59 | // RxBDAddress was updated also when value to r_TxBDNum was written with |
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60 | // greater value than allowed. |
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61 | // |
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62 | // Revision 1.24 2002/11/22 01:57:06 mohor |
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63 | // Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
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64 | // synchronized. |
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65 | // |
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66 | // Revision 1.23 2002/11/19 18:13:49 mohor |
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67 | // r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. |
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68 | // |
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69 | // Revision 1.22 2002/11/14 18:37:20 mohor |
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70 | // r_Rst signal does not reset any module any more and is removed from the design. |
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71 | // |
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72 | // Revision 1.21 2002/09/10 10:35:23 mohor |
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73 | // Ethernet debug registers removed. |
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74 | // |
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75 | // Revision 1.20 2002/09/04 18:40:25 mohor |
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76 | // ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to |
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77 | // the control frames connected. |
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78 | // |
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79 | // Revision 1.19 2002/08/19 16:01:40 mohor |
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80 | // Only values smaller or equal to 0x80 can be written to TX_BD_NUM register. |
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81 | // r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut. |
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82 | // |
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83 | // Revision 1.18 2002/08/16 22:28:23 mohor |
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84 | // Syntax error fixed. |
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85 | // |
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86 | // Revision 1.17 2002/08/16 22:23:03 mohor |
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87 | // Syntax error fixed. |
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88 | // |
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89 | // Revision 1.16 2002/08/16 22:14:22 mohor |
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90 | // Synchronous reset added to all registers. Defines used for width. r_MiiMRst |
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91 | // changed from bit position 10 to 9. |
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92 | // |
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93 | // Revision 1.15 2002/08/14 18:26:37 mohor |
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94 | // LinkFailRegister is reflecting the status of the PHY's link fail status bit. |
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95 | // |
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96 | // Revision 1.14 2002/04/22 14:03:44 mohor |
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97 | // Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled |
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98 | // or not. |
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99 | // |
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100 | // Revision 1.13 2002/02/26 16:18:09 mohor |
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101 | // Reset values are passed to registers through parameters |
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102 | // |
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103 | // Revision 1.12 2002/02/17 13:23:42 mohor |
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104 | // Define missmatch fixed. |
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105 | // |
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106 | // Revision 1.11 2002/02/16 14:03:44 mohor |
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107 | // Registered trimmed. Unused registers removed. |
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108 | // |
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109 | // Revision 1.10 2002/02/15 11:08:25 mohor |
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110 | // File format fixed a bit. |
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111 | // |
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112 | // Revision 1.9 2002/02/14 20:19:41 billditt |
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113 | // Modified for Address Checking, |
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114 | // addition of eth_addrcheck.v |
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115 | // |
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116 | // Revision 1.8 2002/02/12 17:01:19 mohor |
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117 | // HASH0 and HASH1 registers added. |
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118 | |
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119 | // Revision 1.7 2002/01/23 10:28:16 mohor |
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120 | // Link in the header changed. |
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121 | // |
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122 | // Revision 1.6 2001/12/05 15:00:16 mohor |
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123 | // RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors |
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124 | // instead of the number of RX descriptors). |
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125 | // |
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126 | // Revision 1.5 2001/12/05 10:22:19 mohor |
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127 | // ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. |
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128 | // |
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129 | // Revision 1.4 2001/10/19 08:43:51 mohor |
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130 | // eth_timescale.v changed to timescale.v This is done because of the |
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131 | // simulation of the few cores in a one joined project. |
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132 | // |
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133 | // Revision 1.3 2001/10/18 12:07:11 mohor |
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134 | // Status signals changed, Adress decoding changed, interrupt controller |
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135 | // added. |
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136 | // |
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137 | // Revision 1.2 2001/09/24 15:02:56 mohor |
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138 | // Defines changed (All precede with ETH_). Small changes because some |
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139 | // tools generate warnings when two operands are together. Synchronization |
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140 | // between two clocks domains in eth_wishbonedma.v is changed (due to ASIC |
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141 | // demands). |
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142 | // |
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143 | // Revision 1.1 2001/08/06 14:44:29 mohor |
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144 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). |
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145 | // Include files fixed to contain no path. |
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146 | // File names and module names changed ta have a eth_ prologue in the name. |
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147 | // File eth_timescale.v is used to define timescale |
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148 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. |
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149 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O |
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150 | // and Mdo_OE. The bidirectional signal must be created on the top level. This |
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151 | // is done due to the ASIC tools. |
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152 | // |
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153 | // Revision 1.2 2001/08/02 09:25:31 mohor |
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154 | // Unconnected signals are now connected. |
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155 | // |
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156 | // Revision 1.1 2001/07/30 21:23:42 mohor |
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157 | // Directory structure changed. Files checked and joind together. |
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158 | // |
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159 | // |
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160 | // |
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161 | // |
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162 | // |
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163 | // |
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164 | |
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165 | `include "eth_defines.v" |
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166 | `include "timescale.v" |
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167 | |
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168 | |
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169 | module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, |
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170 | r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn, |
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171 | r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG, |
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172 | r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn, |
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173 | TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, |
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174 | r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet, |
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175 | r_CollValid, r_TxFlow, r_RxFlow, r_PassAll, |
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176 | r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat, |
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177 | r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat, |
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178 | LinkFail, r_MAC, WCtrlDataStart, RStatStart, |
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179 | UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o, |
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180 | r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm, |
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181 | StartTxDone, TxClk, RxClk, SetPauseTimer |
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182 | ); |
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183 | |
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184 | parameter Tp = 1; |
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185 | |
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186 | input [31:0] DataIn; |
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187 | input [7:0] Address; |
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188 | |
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189 | input Rw; |
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190 | input [3:0] Cs; |
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191 | input Clk; |
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192 | input Reset; |
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193 | |
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194 | input WCtrlDataStart; |
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195 | input RStatStart; |
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196 | |
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197 | input UpdateMIIRX_DATAReg; |
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198 | input [15:0] Prsd; |
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199 | |
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200 | output [31:0] DataOut; |
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201 | reg [31:0] DataOut; |
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202 | |
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203 | output r_RecSmall; |
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204 | output r_Pad; |
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205 | output r_HugEn; |
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206 | output r_CrcEn; |
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207 | output r_DlyCrcEn; |
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208 | output r_FullD; |
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209 | output r_ExDfrEn; |
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210 | output r_NoBckof; |
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211 | output r_LoopBck; |
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212 | output r_IFG; |
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213 | output r_Pro; |
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214 | output r_Iam; |
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215 | output r_Bro; |
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216 | output r_NoPre; |
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217 | output r_TxEn; |
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218 | output r_RxEn; |
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219 | output [31:0] r_HASH0; |
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220 | output [31:0] r_HASH1; |
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221 | |
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222 | input TxB_IRQ; |
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223 | input TxE_IRQ; |
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224 | input RxB_IRQ; |
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225 | input RxE_IRQ; |
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226 | input Busy_IRQ; |
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227 | |
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228 | output [6:0] r_IPGT; |
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229 | |
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230 | output [6:0] r_IPGR1; |
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231 | |
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232 | output [6:0] r_IPGR2; |
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233 | |
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234 | output [15:0] r_MinFL; |
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235 | output [15:0] r_MaxFL; |
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236 | |
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237 | output [3:0] r_MaxRet; |
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238 | output [5:0] r_CollValid; |
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239 | |
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240 | output r_TxFlow; |
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241 | output r_RxFlow; |
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242 | output r_PassAll; |
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243 | |
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244 | output r_MiiNoPre; |
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245 | output [7:0] r_ClkDiv; |
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246 | |
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247 | output r_WCtrlData; |
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248 | output r_RStat; |
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249 | output r_ScanStat; |
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250 | |
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251 | output [4:0] r_RGAD; |
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252 | output [4:0] r_FIAD; |
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253 | |
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254 | output [15:0]r_CtrlData; |
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255 | |
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256 | |
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257 | input NValid_stat; |
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258 | input Busy_stat; |
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259 | input LinkFail; |
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260 | |
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261 | output [47:0]r_MAC; |
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262 | output [7:0] r_TxBDNum; |
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263 | output int_o; |
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264 | output [15:0]r_TxPauseTV; |
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265 | output r_TxPauseRq; |
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266 | input RstTxPauseRq; |
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267 | input TxCtrlEndFrm; |
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268 | input StartTxDone; |
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269 | input TxClk; |
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270 | input RxClk; |
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271 | input SetPauseTimer; |
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272 | |
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273 | reg irq_txb; |
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274 | reg irq_txe; |
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275 | reg irq_rxb; |
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276 | reg irq_rxe; |
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277 | reg irq_busy; |
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278 | reg irq_txc; |
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279 | reg irq_rxc; |
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280 | |
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281 | reg SetTxCIrq_txclk; |
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282 | reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3; |
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283 | reg SetTxCIrq; |
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284 | reg ResetTxCIrq_sync1, ResetTxCIrq_sync2; |
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285 | |
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286 | reg SetRxCIrq_rxclk; |
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287 | reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3; |
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288 | reg SetRxCIrq; |
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289 | reg ResetRxCIrq_sync1; |
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290 | reg ResetRxCIrq_sync2; |
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291 | reg ResetRxCIrq_sync3; |
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292 | |
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293 | wire [3:0] Write = Cs & {4{Rw}}; |
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294 | wire Read = (|Cs) & ~Rw; |
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295 | |
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296 | wire MODER_Sel = (Address == `ETH_MODER_ADR ); |
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297 | wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR ); |
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298 | wire INT_MASK_Sel = (Address == `ETH_INT_MASK_ADR ); |
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299 | wire IPGT_Sel = (Address == `ETH_IPGT_ADR ); |
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300 | wire IPGR1_Sel = (Address == `ETH_IPGR1_ADR ); |
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301 | wire IPGR2_Sel = (Address == `ETH_IPGR2_ADR ); |
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302 | wire PACKETLEN_Sel = (Address == `ETH_PACKETLEN_ADR ); |
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303 | wire COLLCONF_Sel = (Address == `ETH_COLLCONF_ADR ); |
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304 | |
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305 | wire CTRLMODER_Sel = (Address == `ETH_CTRLMODER_ADR ); |
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306 | wire MIIMODER_Sel = (Address == `ETH_MIIMODER_ADR ); |
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307 | wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR ); |
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308 | wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR ); |
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309 | wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR ); |
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310 | wire MAC_ADDR0_Sel = (Address == `ETH_MAC_ADDR0_ADR ); |
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311 | wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR ); |
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312 | wire HASH0_Sel = (Address == `ETH_HASH0_ADR ); |
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313 | wire HASH1_Sel = (Address == `ETH_HASH1_ADR ); |
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314 | wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR ); |
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315 | wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR ); |
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316 | wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR ); |
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317 | |
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318 | |
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319 | wire [2:0] MODER_Wr; |
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320 | wire [0:0] INT_SOURCE_Wr; |
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321 | wire [0:0] INT_MASK_Wr; |
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322 | wire [0:0] IPGT_Wr; |
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323 | wire [0:0] IPGR1_Wr; |
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324 | wire [0:0] IPGR2_Wr; |
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325 | wire [3:0] PACKETLEN_Wr; |
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326 | wire [2:0] COLLCONF_Wr; |
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327 | wire [0:0] CTRLMODER_Wr; |
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328 | wire [1:0] MIIMODER_Wr; |
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329 | wire [0:0] MIICOMMAND_Wr; |
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330 | wire [1:0] MIIADDRESS_Wr; |
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331 | wire [1:0] MIITX_DATA_Wr; |
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332 | wire MIIRX_DATA_Wr; |
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333 | wire [3:0] MAC_ADDR0_Wr; |
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334 | wire [1:0] MAC_ADDR1_Wr; |
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335 | wire [3:0] HASH0_Wr; |
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336 | wire [3:0] HASH1_Wr; |
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337 | wire [2:0] TXCTRL_Wr; |
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338 | wire [0:0] TX_BD_NUM_Wr; |
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339 | |
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340 | assign MODER_Wr[0] = Write[0] & MODER_Sel; |
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341 | assign MODER_Wr[1] = Write[1] & MODER_Sel; |
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342 | assign MODER_Wr[2] = Write[2] & MODER_Sel; |
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343 | assign INT_SOURCE_Wr[0] = Write[0] & INT_SOURCE_Sel; |
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344 | assign INT_MASK_Wr[0] = Write[0] & INT_MASK_Sel; |
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345 | assign IPGT_Wr[0] = Write[0] & IPGT_Sel; |
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346 | assign IPGR1_Wr[0] = Write[0] & IPGR1_Sel; |
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347 | assign IPGR2_Wr[0] = Write[0] & IPGR2_Sel; |
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348 | assign PACKETLEN_Wr[0] = Write[0] & PACKETLEN_Sel; |
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349 | assign PACKETLEN_Wr[1] = Write[1] & PACKETLEN_Sel; |
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350 | assign PACKETLEN_Wr[2] = Write[2] & PACKETLEN_Sel; |
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351 | assign PACKETLEN_Wr[3] = Write[3] & PACKETLEN_Sel; |
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352 | assign COLLCONF_Wr[0] = Write[0] & COLLCONF_Sel; |
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353 | assign COLLCONF_Wr[1] = 1'b0; // Not used |
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354 | assign COLLCONF_Wr[2] = Write[2] & COLLCONF_Sel; |
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355 | |
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356 | assign CTRLMODER_Wr[0] = Write[0] & CTRLMODER_Sel; |
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357 | assign MIIMODER_Wr[0] = Write[0] & MIIMODER_Sel; |
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358 | assign MIIMODER_Wr[1] = Write[1] & MIIMODER_Sel; |
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359 | assign MIICOMMAND_Wr[0] = Write[0] & MIICOMMAND_Sel; |
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360 | assign MIIADDRESS_Wr[0] = Write[0] & MIIADDRESS_Sel; |
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361 | assign MIIADDRESS_Wr[1] = Write[1] & MIIADDRESS_Sel; |
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362 | assign MIITX_DATA_Wr[0] = Write[0] & MIITX_DATA_Sel; |
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363 | assign MIITX_DATA_Wr[1] = Write[1] & MIITX_DATA_Sel; |
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364 | assign MIIRX_DATA_Wr = UpdateMIIRX_DATAReg; |
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365 | assign MAC_ADDR0_Wr[0] = Write[0] & MAC_ADDR0_Sel; |
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366 | assign MAC_ADDR0_Wr[1] = Write[1] & MAC_ADDR0_Sel; |
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367 | assign MAC_ADDR0_Wr[2] = Write[2] & MAC_ADDR0_Sel; |
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368 | assign MAC_ADDR0_Wr[3] = Write[3] & MAC_ADDR0_Sel; |
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369 | assign MAC_ADDR1_Wr[0] = Write[0] & MAC_ADDR1_Sel; |
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370 | assign MAC_ADDR1_Wr[1] = Write[1] & MAC_ADDR1_Sel; |
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371 | assign HASH0_Wr[0] = Write[0] & HASH0_Sel; |
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372 | assign HASH0_Wr[1] = Write[1] & HASH0_Sel; |
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373 | assign HASH0_Wr[2] = Write[2] & HASH0_Sel; |
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374 | assign HASH0_Wr[3] = Write[3] & HASH0_Sel; |
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375 | assign HASH1_Wr[0] = Write[0] & HASH1_Sel; |
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376 | assign HASH1_Wr[1] = Write[1] & HASH1_Sel; |
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377 | assign HASH1_Wr[2] = Write[2] & HASH1_Sel; |
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378 | assign HASH1_Wr[3] = Write[3] & HASH1_Sel; |
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379 | assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel; |
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380 | assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel; |
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381 | assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel; |
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382 | assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80); |
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383 | |
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384 | |
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385 | |
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386 | wire [31:0] MODEROut; |
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387 | wire [31:0] INT_SOURCEOut; |
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388 | wire [31:0] INT_MASKOut; |
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389 | wire [31:0] IPGTOut; |
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390 | wire [31:0] IPGR1Out; |
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391 | wire [31:0] IPGR2Out; |
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392 | wire [31:0] PACKETLENOut; |
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393 | wire [31:0] COLLCONFOut; |
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394 | wire [31:0] CTRLMODEROut; |
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395 | wire [31:0] MIIMODEROut; |
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396 | wire [31:0] MIICOMMANDOut; |
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397 | wire [31:0] MIIADDRESSOut; |
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398 | wire [31:0] MIITX_DATAOut; |
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399 | wire [31:0] MIIRX_DATAOut; |
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400 | wire [31:0] MIISTATUSOut; |
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401 | wire [31:0] MAC_ADDR0Out; |
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402 | wire [31:0] MAC_ADDR1Out; |
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403 | wire [31:0] TX_BD_NUMOut; |
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404 | wire [31:0] HASH0Out; |
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405 | wire [31:0] HASH1Out; |
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406 | wire [31:0] TXCTRLOut; |
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407 | |
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408 | // MODER Register |
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409 | eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0 |
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410 | ( |
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411 | .DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]), |
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412 | .DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]), |
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413 | .Write (MODER_Wr[0]), |
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414 | .Clk (Clk), |
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415 | .Reset (Reset), |
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416 | .SyncReset (1'b0) |
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417 | ); |
---|
418 | eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1 |
---|
419 | ( |
---|
420 | .DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]), |
---|
421 | .DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]), |
---|
422 | .Write (MODER_Wr[1]), |
---|
423 | .Clk (Clk), |
---|
424 | .Reset (Reset), |
---|
425 | .SyncReset (1'b0) |
---|
426 | ); |
---|
427 | eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2 |
---|
428 | ( |
---|
429 | .DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]), |
---|
430 | .DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]), |
---|
431 | .Write (MODER_Wr[2]), |
---|
432 | .Clk (Clk), |
---|
433 | .Reset (Reset), |
---|
434 | .SyncReset (1'b0) |
---|
435 | ); |
---|
436 | assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0; |
---|
437 | |
---|
438 | // INT_MASK Register |
---|
439 | eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0 |
---|
440 | ( |
---|
441 | .DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]), |
---|
442 | .DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]), |
---|
443 | .Write (INT_MASK_Wr[0]), |
---|
444 | .Clk (Clk), |
---|
445 | .Reset (Reset), |
---|
446 | .SyncReset (1'b0) |
---|
447 | ); |
---|
448 | assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0; |
---|
449 | |
---|
450 | // IPGT Register |
---|
451 | eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0 |
---|
452 | ( |
---|
453 | .DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]), |
---|
454 | .DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]), |
---|
455 | .Write (IPGT_Wr[0]), |
---|
456 | .Clk (Clk), |
---|
457 | .Reset (Reset), |
---|
458 | .SyncReset (1'b0) |
---|
459 | ); |
---|
460 | assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0; |
---|
461 | |
---|
462 | // IPGR1 Register |
---|
463 | eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0 |
---|
464 | ( |
---|
465 | .DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]), |
---|
466 | .DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]), |
---|
467 | .Write (IPGR1_Wr[0]), |
---|
468 | .Clk (Clk), |
---|
469 | .Reset (Reset), |
---|
470 | .SyncReset (1'b0) |
---|
471 | ); |
---|
472 | assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0; |
---|
473 | |
---|
474 | // IPGR2 Register |
---|
475 | eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0 |
---|
476 | ( |
---|
477 | .DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]), |
---|
478 | .DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]), |
---|
479 | .Write (IPGR2_Wr[0]), |
---|
480 | .Clk (Clk), |
---|
481 | .Reset (Reset), |
---|
482 | .SyncReset (1'b0) |
---|
483 | ); |
---|
484 | assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0; |
---|
485 | |
---|
486 | // PACKETLEN Register |
---|
487 | eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0 |
---|
488 | ( |
---|
489 | .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]), |
---|
490 | .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]), |
---|
491 | .Write (PACKETLEN_Wr[0]), |
---|
492 | .Clk (Clk), |
---|
493 | .Reset (Reset), |
---|
494 | .SyncReset (1'b0) |
---|
495 | ); |
---|
496 | eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1 |
---|
497 | ( |
---|
498 | .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]), |
---|
499 | .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]), |
---|
500 | .Write (PACKETLEN_Wr[1]), |
---|
501 | .Clk (Clk), |
---|
502 | .Reset (Reset), |
---|
503 | .SyncReset (1'b0) |
---|
504 | ); |
---|
505 | eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2 |
---|
506 | ( |
---|
507 | .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]), |
---|
508 | .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]), |
---|
509 | .Write (PACKETLEN_Wr[2]), |
---|
510 | .Clk (Clk), |
---|
511 | .Reset (Reset), |
---|
512 | .SyncReset (1'b0) |
---|
513 | ); |
---|
514 | eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3 |
---|
515 | ( |
---|
516 | .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]), |
---|
517 | .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]), |
---|
518 | .Write (PACKETLEN_Wr[3]), |
---|
519 | .Clk (Clk), |
---|
520 | .Reset (Reset), |
---|
521 | .SyncReset (1'b0) |
---|
522 | ); |
---|
523 | |
---|
524 | // COLLCONF Register |
---|
525 | eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0 |
---|
526 | ( |
---|
527 | .DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]), |
---|
528 | .DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]), |
---|
529 | .Write (COLLCONF_Wr[0]), |
---|
530 | .Clk (Clk), |
---|
531 | .Reset (Reset), |
---|
532 | .SyncReset (1'b0) |
---|
533 | ); |
---|
534 | eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2 |
---|
535 | ( |
---|
536 | .DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]), |
---|
537 | .DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]), |
---|
538 | .Write (COLLCONF_Wr[2]), |
---|
539 | .Clk (Clk), |
---|
540 | .Reset (Reset), |
---|
541 | .SyncReset (1'b0) |
---|
542 | ); |
---|
543 | assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0; |
---|
544 | assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0; |
---|
545 | |
---|
546 | // TX_BD_NUM Register |
---|
547 | eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0 |
---|
548 | ( |
---|
549 | .DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]), |
---|
550 | .DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]), |
---|
551 | .Write (TX_BD_NUM_Wr[0]), |
---|
552 | .Clk (Clk), |
---|
553 | .Reset (Reset), |
---|
554 | .SyncReset (1'b0) |
---|
555 | ); |
---|
556 | assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0; |
---|
557 | |
---|
558 | // CTRLMODER Register |
---|
559 | eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0 |
---|
560 | ( |
---|
561 | .DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]), |
---|
562 | .DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]), |
---|
563 | .Write (CTRLMODER_Wr[0]), |
---|
564 | .Clk (Clk), |
---|
565 | .Reset (Reset), |
---|
566 | .SyncReset (1'b0) |
---|
567 | ); |
---|
568 | assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0; |
---|
569 | |
---|
570 | // MIIMODER Register |
---|
571 | eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0 |
---|
572 | ( |
---|
573 | .DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]), |
---|
574 | .DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]), |
---|
575 | .Write (MIIMODER_Wr[0]), |
---|
576 | .Clk (Clk), |
---|
577 | .Reset (Reset), |
---|
578 | .SyncReset (1'b0) |
---|
579 | ); |
---|
580 | eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1 |
---|
581 | ( |
---|
582 | .DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]), |
---|
583 | .DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]), |
---|
584 | .Write (MIIMODER_Wr[1]), |
---|
585 | .Clk (Clk), |
---|
586 | .Reset (Reset), |
---|
587 | .SyncReset (1'b0) |
---|
588 | ); |
---|
589 | assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0; |
---|
590 | |
---|
591 | // MIICOMMAND Register |
---|
592 | eth_register #(1, 0) MIICOMMAND0 |
---|
593 | ( |
---|
594 | .DataIn (DataIn[0]), |
---|
595 | .DataOut (MIICOMMANDOut[0]), |
---|
596 | .Write (MIICOMMAND_Wr[0]), |
---|
597 | .Clk (Clk), |
---|
598 | .Reset (Reset), |
---|
599 | .SyncReset (1'b0) |
---|
600 | ); |
---|
601 | eth_register #(1, 0) MIICOMMAND1 |
---|
602 | ( |
---|
603 | .DataIn (DataIn[1]), |
---|
604 | .DataOut (MIICOMMANDOut[1]), |
---|
605 | .Write (MIICOMMAND_Wr[0]), |
---|
606 | .Clk (Clk), |
---|
607 | .Reset (Reset), |
---|
608 | .SyncReset (RStatStart) |
---|
609 | ); |
---|
610 | eth_register #(1, 0) MIICOMMAND2 |
---|
611 | ( |
---|
612 | .DataIn (DataIn[2]), |
---|
613 | .DataOut (MIICOMMANDOut[2]), |
---|
614 | .Write (MIICOMMAND_Wr[0]), |
---|
615 | .Clk (Clk), |
---|
616 | .Reset (Reset), |
---|
617 | .SyncReset (WCtrlDataStart) |
---|
618 | ); |
---|
619 | assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0; |
---|
620 | |
---|
621 | // MIIADDRESSRegister |
---|
622 | eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0 |
---|
623 | ( |
---|
624 | .DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]), |
---|
625 | .DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]), |
---|
626 | .Write (MIIADDRESS_Wr[0]), |
---|
627 | .Clk (Clk), |
---|
628 | .Reset (Reset), |
---|
629 | .SyncReset (1'b0) |
---|
630 | ); |
---|
631 | eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1 |
---|
632 | ( |
---|
633 | .DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]), |
---|
634 | .DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]), |
---|
635 | .Write (MIIADDRESS_Wr[1]), |
---|
636 | .Clk (Clk), |
---|
637 | .Reset (Reset), |
---|
638 | .SyncReset (1'b0) |
---|
639 | ); |
---|
640 | assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0; |
---|
641 | assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0; |
---|
642 | |
---|
643 | // MIITX_DATA Register |
---|
644 | eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0 |
---|
645 | ( |
---|
646 | .DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]), |
---|
647 | .DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]), |
---|
648 | .Write (MIITX_DATA_Wr[0]), |
---|
649 | .Clk (Clk), |
---|
650 | .Reset (Reset), |
---|
651 | .SyncReset (1'b0) |
---|
652 | ); |
---|
653 | eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1 |
---|
654 | ( |
---|
655 | .DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]), |
---|
656 | .DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]), |
---|
657 | .Write (MIITX_DATA_Wr[1]), |
---|
658 | .Clk (Clk), |
---|
659 | .Reset (Reset), |
---|
660 | .SyncReset (1'b0) |
---|
661 | ); |
---|
662 | assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0; |
---|
663 | |
---|
664 | // MIIRX_DATA Register |
---|
665 | eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA |
---|
666 | ( |
---|
667 | .DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]), |
---|
668 | .DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]), |
---|
669 | .Write (MIIRX_DATA_Wr), // not written from WB |
---|
670 | .Clk (Clk), |
---|
671 | .Reset (Reset), |
---|
672 | .SyncReset (1'b0) |
---|
673 | ); |
---|
674 | assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0; |
---|
675 | |
---|
676 | // MAC_ADDR0 Register |
---|
677 | eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0 |
---|
678 | ( |
---|
679 | .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]), |
---|
680 | .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]), |
---|
681 | .Write (MAC_ADDR0_Wr[0]), |
---|
682 | .Clk (Clk), |
---|
683 | .Reset (Reset), |
---|
684 | .SyncReset (1'b0) |
---|
685 | ); |
---|
686 | eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1 |
---|
687 | ( |
---|
688 | .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]), |
---|
689 | .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]), |
---|
690 | .Write (MAC_ADDR0_Wr[1]), |
---|
691 | .Clk (Clk), |
---|
692 | .Reset (Reset), |
---|
693 | .SyncReset (1'b0) |
---|
694 | ); |
---|
695 | eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2 |
---|
696 | ( |
---|
697 | .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]), |
---|
698 | .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]), |
---|
699 | .Write (MAC_ADDR0_Wr[2]), |
---|
700 | .Clk (Clk), |
---|
701 | .Reset (Reset), |
---|
702 | .SyncReset (1'b0) |
---|
703 | ); |
---|
704 | eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3 |
---|
705 | ( |
---|
706 | .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]), |
---|
707 | .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]), |
---|
708 | .Write (MAC_ADDR0_Wr[3]), |
---|
709 | .Clk (Clk), |
---|
710 | .Reset (Reset), |
---|
711 | .SyncReset (1'b0) |
---|
712 | ); |
---|
713 | |
---|
714 | // MAC_ADDR1 Register |
---|
715 | eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0 |
---|
716 | ( |
---|
717 | .DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]), |
---|
718 | .DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]), |
---|
719 | .Write (MAC_ADDR1_Wr[0]), |
---|
720 | .Clk (Clk), |
---|
721 | .Reset (Reset), |
---|
722 | .SyncReset (1'b0) |
---|
723 | ); |
---|
724 | eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1 |
---|
725 | ( |
---|
726 | .DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]), |
---|
727 | .DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]), |
---|
728 | .Write (MAC_ADDR1_Wr[1]), |
---|
729 | .Clk (Clk), |
---|
730 | .Reset (Reset), |
---|
731 | .SyncReset (1'b0) |
---|
732 | ); |
---|
733 | assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0; |
---|
734 | |
---|
735 | // RXHASH0 Register |
---|
736 | eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0 |
---|
737 | ( |
---|
738 | .DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]), |
---|
739 | .DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]), |
---|
740 | .Write (HASH0_Wr[0]), |
---|
741 | .Clk (Clk), |
---|
742 | .Reset (Reset), |
---|
743 | .SyncReset (1'b0) |
---|
744 | ); |
---|
745 | eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1 |
---|
746 | ( |
---|
747 | .DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]), |
---|
748 | .DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]), |
---|
749 | .Write (HASH0_Wr[1]), |
---|
750 | .Clk (Clk), |
---|
751 | .Reset (Reset), |
---|
752 | .SyncReset (1'b0) |
---|
753 | ); |
---|
754 | eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2 |
---|
755 | ( |
---|
756 | .DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]), |
---|
757 | .DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]), |
---|
758 | .Write (HASH0_Wr[2]), |
---|
759 | .Clk (Clk), |
---|
760 | .Reset (Reset), |
---|
761 | .SyncReset (1'b0) |
---|
762 | ); |
---|
763 | eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3 |
---|
764 | ( |
---|
765 | .DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]), |
---|
766 | .DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]), |
---|
767 | .Write (HASH0_Wr[3]), |
---|
768 | .Clk (Clk), |
---|
769 | .Reset (Reset), |
---|
770 | .SyncReset (1'b0) |
---|
771 | ); |
---|
772 | |
---|
773 | // RXHASH1 Register |
---|
774 | eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0 |
---|
775 | ( |
---|
776 | .DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]), |
---|
777 | .DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]), |
---|
778 | .Write (HASH1_Wr[0]), |
---|
779 | .Clk (Clk), |
---|
780 | .Reset (Reset), |
---|
781 | .SyncReset (1'b0) |
---|
782 | ); |
---|
783 | eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1 |
---|
784 | ( |
---|
785 | .DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]), |
---|
786 | .DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]), |
---|
787 | .Write (HASH1_Wr[1]), |
---|
788 | .Clk (Clk), |
---|
789 | .Reset (Reset), |
---|
790 | .SyncReset (1'b0) |
---|
791 | ); |
---|
792 | eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2 |
---|
793 | ( |
---|
794 | .DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]), |
---|
795 | .DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]), |
---|
796 | .Write (HASH1_Wr[2]), |
---|
797 | .Clk (Clk), |
---|
798 | .Reset (Reset), |
---|
799 | .SyncReset (1'b0) |
---|
800 | ); |
---|
801 | eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3 |
---|
802 | ( |
---|
803 | .DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]), |
---|
804 | .DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]), |
---|
805 | .Write (HASH1_Wr[3]), |
---|
806 | .Clk (Clk), |
---|
807 | .Reset (Reset), |
---|
808 | .SyncReset (1'b0) |
---|
809 | ); |
---|
810 | |
---|
811 | // TXCTRL Register |
---|
812 | eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0 |
---|
813 | ( |
---|
814 | .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]), |
---|
815 | .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]), |
---|
816 | .Write (TXCTRL_Wr[0]), |
---|
817 | .Clk (Clk), |
---|
818 | .Reset (Reset), |
---|
819 | .SyncReset (1'b0) |
---|
820 | ); |
---|
821 | eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1 |
---|
822 | ( |
---|
823 | .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]), |
---|
824 | .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]), |
---|
825 | .Write (TXCTRL_Wr[1]), |
---|
826 | .Clk (Clk), |
---|
827 | .Reset (Reset), |
---|
828 | .SyncReset (1'b0) |
---|
829 | ); |
---|
830 | eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset |
---|
831 | ( |
---|
832 | .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]), |
---|
833 | .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]), |
---|
834 | .Write (TXCTRL_Wr[2]), |
---|
835 | .Clk (Clk), |
---|
836 | .Reset (Reset), |
---|
837 | .SyncReset (RstTxPauseRq) |
---|
838 | ); |
---|
839 | assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0; |
---|
840 | |
---|
841 | |
---|
842 | |
---|
843 | // Reading data from registers |
---|
844 | always @ (Address or Read or MODEROut or INT_SOURCEOut or |
---|
845 | INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or |
---|
846 | PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or |
---|
847 | MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or |
---|
848 | MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or |
---|
849 | HASH0Out or HASH1Out or TXCTRLOut |
---|
850 | ) |
---|
851 | begin |
---|
852 | if(Read) // read |
---|
853 | begin |
---|
854 | case(Address) |
---|
855 | `ETH_MODER_ADR : DataOut<=MODEROut; |
---|
856 | `ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut; |
---|
857 | `ETH_INT_MASK_ADR : DataOut<=INT_MASKOut; |
---|
858 | `ETH_IPGT_ADR : DataOut<=IPGTOut; |
---|
859 | `ETH_IPGR1_ADR : DataOut<=IPGR1Out; |
---|
860 | `ETH_IPGR2_ADR : DataOut<=IPGR2Out; |
---|
861 | `ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut; |
---|
862 | `ETH_COLLCONF_ADR : DataOut<=COLLCONFOut; |
---|
863 | `ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut; |
---|
864 | `ETH_MIIMODER_ADR : DataOut<=MIIMODEROut; |
---|
865 | `ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut; |
---|
866 | `ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut; |
---|
867 | `ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut; |
---|
868 | `ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut; |
---|
869 | `ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut; |
---|
870 | `ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out; |
---|
871 | `ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out; |
---|
872 | `ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut; |
---|
873 | `ETH_HASH0_ADR : DataOut<=HASH0Out; |
---|
874 | `ETH_HASH1_ADR : DataOut<=HASH1Out; |
---|
875 | `ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut; |
---|
876 | |
---|
877 | default: DataOut<=32'h0; |
---|
878 | endcase |
---|
879 | end |
---|
880 | else |
---|
881 | DataOut<=32'h0; |
---|
882 | end |
---|
883 | |
---|
884 | |
---|
885 | assign r_RecSmall = MODEROut[16]; |
---|
886 | assign r_Pad = MODEROut[15]; |
---|
887 | assign r_HugEn = MODEROut[14]; |
---|
888 | assign r_CrcEn = MODEROut[13]; |
---|
889 | assign r_DlyCrcEn = MODEROut[12]; |
---|
890 | // assign r_Rst = MODEROut[11]; This signal is not used any more |
---|
891 | assign r_FullD = MODEROut[10]; |
---|
892 | assign r_ExDfrEn = MODEROut[9]; |
---|
893 | assign r_NoBckof = MODEROut[8]; |
---|
894 | assign r_LoopBck = MODEROut[7]; |
---|
895 | assign r_IFG = MODEROut[6]; |
---|
896 | assign r_Pro = MODEROut[5]; |
---|
897 | assign r_Iam = MODEROut[4]; |
---|
898 | assign r_Bro = MODEROut[3]; |
---|
899 | assign r_NoPre = MODEROut[2]; |
---|
900 | assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD. |
---|
901 | assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD. |
---|
902 | |
---|
903 | assign r_IPGT[6:0] = IPGTOut[6:0]; |
---|
904 | |
---|
905 | assign r_IPGR1[6:0] = IPGR1Out[6:0]; |
---|
906 | |
---|
907 | assign r_IPGR2[6:0] = IPGR2Out[6:0]; |
---|
908 | |
---|
909 | assign r_MinFL[15:0] = PACKETLENOut[31:16]; |
---|
910 | assign r_MaxFL[15:0] = PACKETLENOut[15:0]; |
---|
911 | |
---|
912 | assign r_MaxRet[3:0] = COLLCONFOut[19:16]; |
---|
913 | assign r_CollValid[5:0] = COLLCONFOut[5:0]; |
---|
914 | |
---|
915 | assign r_TxFlow = CTRLMODEROut[2]; |
---|
916 | assign r_RxFlow = CTRLMODEROut[1]; |
---|
917 | assign r_PassAll = CTRLMODEROut[0]; |
---|
918 | |
---|
919 | assign r_MiiNoPre = MIIMODEROut[8]; |
---|
920 | assign r_ClkDiv[7:0] = MIIMODEROut[7:0]; |
---|
921 | |
---|
922 | assign r_WCtrlData = MIICOMMANDOut[2]; |
---|
923 | assign r_RStat = MIICOMMANDOut[1]; |
---|
924 | assign r_ScanStat = MIICOMMANDOut[0]; |
---|
925 | |
---|
926 | assign r_RGAD[4:0] = MIIADDRESSOut[12:8]; |
---|
927 | assign r_FIAD[4:0] = MIIADDRESSOut[4:0]; |
---|
928 | |
---|
929 | assign r_CtrlData[15:0] = MIITX_DATAOut[15:0]; |
---|
930 | |
---|
931 | assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0; |
---|
932 | assign MIISTATUSOut[2] = NValid_stat ; |
---|
933 | assign MIISTATUSOut[1] = Busy_stat ; |
---|
934 | assign MIISTATUSOut[0] = LinkFail ; |
---|
935 | |
---|
936 | assign r_MAC[31:0] = MAC_ADDR0Out[31:0]; |
---|
937 | assign r_MAC[47:32] = MAC_ADDR1Out[15:0]; |
---|
938 | assign r_HASH1[31:0] = HASH1Out; |
---|
939 | assign r_HASH0[31:0] = HASH0Out; |
---|
940 | |
---|
941 | assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0]; |
---|
942 | |
---|
943 | assign r_TxPauseTV[15:0] = TXCTRLOut[15:0]; |
---|
944 | assign r_TxPauseRq = TXCTRLOut[16]; |
---|
945 | |
---|
946 | |
---|
947 | // Synchronizing TxC Interrupt |
---|
948 | always @ (posedge TxClk or posedge Reset) |
---|
949 | begin |
---|
950 | if(Reset) |
---|
951 | SetTxCIrq_txclk <=#Tp 1'b0; |
---|
952 | else |
---|
953 | if(TxCtrlEndFrm & StartTxDone & r_TxFlow) |
---|
954 | SetTxCIrq_txclk <=#Tp 1'b1; |
---|
955 | else |
---|
956 | if(ResetTxCIrq_sync2) |
---|
957 | SetTxCIrq_txclk <=#Tp 1'b0; |
---|
958 | end |
---|
959 | |
---|
960 | |
---|
961 | always @ (posedge Clk or posedge Reset) |
---|
962 | begin |
---|
963 | if(Reset) |
---|
964 | SetTxCIrq_sync1 <=#Tp 1'b0; |
---|
965 | else |
---|
966 | SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk; |
---|
967 | end |
---|
968 | |
---|
969 | always @ (posedge Clk or posedge Reset) |
---|
970 | begin |
---|
971 | if(Reset) |
---|
972 | SetTxCIrq_sync2 <=#Tp 1'b0; |
---|
973 | else |
---|
974 | SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1; |
---|
975 | end |
---|
976 | |
---|
977 | always @ (posedge Clk or posedge Reset) |
---|
978 | begin |
---|
979 | if(Reset) |
---|
980 | SetTxCIrq_sync3 <=#Tp 1'b0; |
---|
981 | else |
---|
982 | SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2; |
---|
983 | end |
---|
984 | |
---|
985 | always @ (posedge Clk or posedge Reset) |
---|
986 | begin |
---|
987 | if(Reset) |
---|
988 | SetTxCIrq <=#Tp 1'b0; |
---|
989 | else |
---|
990 | SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3; |
---|
991 | end |
---|
992 | |
---|
993 | always @ (posedge TxClk or posedge Reset) |
---|
994 | begin |
---|
995 | if(Reset) |
---|
996 | ResetTxCIrq_sync1 <=#Tp 1'b0; |
---|
997 | else |
---|
998 | ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2; |
---|
999 | end |
---|
1000 | |
---|
1001 | always @ (posedge TxClk or posedge Reset) |
---|
1002 | begin |
---|
1003 | if(Reset) |
---|
1004 | ResetTxCIrq_sync2 <=#Tp 1'b0; |
---|
1005 | else |
---|
1006 | ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1; |
---|
1007 | end |
---|
1008 | |
---|
1009 | |
---|
1010 | // Synchronizing RxC Interrupt |
---|
1011 | always @ (posedge RxClk or posedge Reset) |
---|
1012 | begin |
---|
1013 | if(Reset) |
---|
1014 | SetRxCIrq_rxclk <=#Tp 1'b0; |
---|
1015 | else |
---|
1016 | if(SetPauseTimer & r_RxFlow) |
---|
1017 | SetRxCIrq_rxclk <=#Tp 1'b1; |
---|
1018 | else |
---|
1019 | if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3)) |
---|
1020 | SetRxCIrq_rxclk <=#Tp 1'b0; |
---|
1021 | end |
---|
1022 | |
---|
1023 | |
---|
1024 | always @ (posedge Clk or posedge Reset) |
---|
1025 | begin |
---|
1026 | if(Reset) |
---|
1027 | SetRxCIrq_sync1 <=#Tp 1'b0; |
---|
1028 | else |
---|
1029 | SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk; |
---|
1030 | end |
---|
1031 | |
---|
1032 | always @ (posedge Clk or posedge Reset) |
---|
1033 | begin |
---|
1034 | if(Reset) |
---|
1035 | SetRxCIrq_sync2 <=#Tp 1'b0; |
---|
1036 | else |
---|
1037 | SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1; |
---|
1038 | end |
---|
1039 | |
---|
1040 | always @ (posedge Clk or posedge Reset) |
---|
1041 | begin |
---|
1042 | if(Reset) |
---|
1043 | SetRxCIrq_sync3 <=#Tp 1'b0; |
---|
1044 | else |
---|
1045 | SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2; |
---|
1046 | end |
---|
1047 | |
---|
1048 | always @ (posedge Clk or posedge Reset) |
---|
1049 | begin |
---|
1050 | if(Reset) |
---|
1051 | SetRxCIrq <=#Tp 1'b0; |
---|
1052 | else |
---|
1053 | SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3; |
---|
1054 | end |
---|
1055 | |
---|
1056 | always @ (posedge RxClk or posedge Reset) |
---|
1057 | begin |
---|
1058 | if(Reset) |
---|
1059 | ResetRxCIrq_sync1 <=#Tp 1'b0; |
---|
1060 | else |
---|
1061 | ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2; |
---|
1062 | end |
---|
1063 | |
---|
1064 | always @ (posedge RxClk or posedge Reset) |
---|
1065 | begin |
---|
1066 | if(Reset) |
---|
1067 | ResetRxCIrq_sync2 <=#Tp 1'b0; |
---|
1068 | else |
---|
1069 | ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1; |
---|
1070 | end |
---|
1071 | |
---|
1072 | always @ (posedge RxClk or posedge Reset) |
---|
1073 | begin |
---|
1074 | if(Reset) |
---|
1075 | ResetRxCIrq_sync3 <=#Tp 1'b0; |
---|
1076 | else |
---|
1077 | ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2; |
---|
1078 | end |
---|
1079 | |
---|
1080 | |
---|
1081 | |
---|
1082 | // Interrupt generation |
---|
1083 | always @ (posedge Clk or posedge Reset) |
---|
1084 | begin |
---|
1085 | if(Reset) |
---|
1086 | irq_txb <= 1'b0; |
---|
1087 | else |
---|
1088 | if(TxB_IRQ) |
---|
1089 | irq_txb <= #Tp 1'b1; |
---|
1090 | else |
---|
1091 | if(INT_SOURCE_Wr[0] & DataIn[0]) |
---|
1092 | irq_txb <= #Tp 1'b0; |
---|
1093 | end |
---|
1094 | |
---|
1095 | always @ (posedge Clk or posedge Reset) |
---|
1096 | begin |
---|
1097 | if(Reset) |
---|
1098 | irq_txe <= 1'b0; |
---|
1099 | else |
---|
1100 | if(TxE_IRQ) |
---|
1101 | irq_txe <= #Tp 1'b1; |
---|
1102 | else |
---|
1103 | if(INT_SOURCE_Wr[0] & DataIn[1]) |
---|
1104 | irq_txe <= #Tp 1'b0; |
---|
1105 | end |
---|
1106 | |
---|
1107 | always @ (posedge Clk or posedge Reset) |
---|
1108 | begin |
---|
1109 | if(Reset) |
---|
1110 | irq_rxb <= 1'b0; |
---|
1111 | else |
---|
1112 | if(RxB_IRQ) |
---|
1113 | irq_rxb <= #Tp 1'b1; |
---|
1114 | else |
---|
1115 | if(INT_SOURCE_Wr[0] & DataIn[2]) |
---|
1116 | irq_rxb <= #Tp 1'b0; |
---|
1117 | end |
---|
1118 | |
---|
1119 | always @ (posedge Clk or posedge Reset) |
---|
1120 | begin |
---|
1121 | if(Reset) |
---|
1122 | irq_rxe <= 1'b0; |
---|
1123 | else |
---|
1124 | if(RxE_IRQ) |
---|
1125 | irq_rxe <= #Tp 1'b1; |
---|
1126 | else |
---|
1127 | if(INT_SOURCE_Wr[0] & DataIn[3]) |
---|
1128 | irq_rxe <= #Tp 1'b0; |
---|
1129 | end |
---|
1130 | |
---|
1131 | always @ (posedge Clk or posedge Reset) |
---|
1132 | begin |
---|
1133 | if(Reset) |
---|
1134 | irq_busy <= 1'b0; |
---|
1135 | else |
---|
1136 | if(Busy_IRQ) |
---|
1137 | irq_busy <= #Tp 1'b1; |
---|
1138 | else |
---|
1139 | if(INT_SOURCE_Wr[0] & DataIn[4]) |
---|
1140 | irq_busy <= #Tp 1'b0; |
---|
1141 | end |
---|
1142 | |
---|
1143 | always @ (posedge Clk or posedge Reset) |
---|
1144 | begin |
---|
1145 | if(Reset) |
---|
1146 | irq_txc <= 1'b0; |
---|
1147 | else |
---|
1148 | if(SetTxCIrq) |
---|
1149 | irq_txc <= #Tp 1'b1; |
---|
1150 | else |
---|
1151 | if(INT_SOURCE_Wr[0] & DataIn[5]) |
---|
1152 | irq_txc <= #Tp 1'b0; |
---|
1153 | end |
---|
1154 | |
---|
1155 | always @ (posedge Clk or posedge Reset) |
---|
1156 | begin |
---|
1157 | if(Reset) |
---|
1158 | irq_rxc <= 1'b0; |
---|
1159 | else |
---|
1160 | if(SetRxCIrq) |
---|
1161 | irq_rxc <= #Tp 1'b1; |
---|
1162 | else |
---|
1163 | if(INT_SOURCE_Wr[0] & DataIn[6]) |
---|
1164 | irq_rxc <= #Tp 1'b0; |
---|
1165 | end |
---|
1166 | |
---|
1167 | // Generating interrupt signal |
---|
1168 | assign int_o = irq_txb & INT_MASKOut[0] | |
---|
1169 | irq_txe & INT_MASKOut[1] | |
---|
1170 | irq_rxb & INT_MASKOut[2] | |
---|
1171 | irq_rxe & INT_MASKOut[3] | |
---|
1172 | irq_busy & INT_MASKOut[4] | |
---|
1173 | irq_txc & INT_MASKOut[5] | |
---|
1174 | irq_rxc & INT_MASKOut[6] ; |
---|
1175 | |
---|
1176 | // For reading interrupt status |
---|
1177 | assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb}; |
---|
1178 | |
---|
1179 | |
---|
1180 | |
---|
1181 | endmodule |
---|