1 | // ========== Copyright Header Begin ========================================== |
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2 | // |
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3 | // OpenSPARC T1 Processor File: sparc_exu_eclbyplog_rs1.v |
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4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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6 | // |
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7 | // The above named program is free software; you can redistribute it and/or |
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8 | // modify it under the terms of the GNU General Public |
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9 | // License version 2 as published by the Free Software Foundation. |
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10 | // |
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11 | // The above named program is distributed in the hope that it will be |
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12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | // General Public License for more details. |
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15 | // |
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16 | // You should have received a copy of the GNU General Public |
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17 | // License along with this work; if not, write to the Free Software |
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18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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19 | // |
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20 | // ========== Copyright Header End ============================================ |
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21 | //////////////////////////////////////////////////////////////////////// |
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22 | /* |
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23 | // Module Name: sparc_exu_eclbyplog_rs1 |
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24 | // Description: This block implements the bypass logic for a single |
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25 | // operand. It takes the destination registers of all |
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26 | // four forwarding sources and the rs. It also has the |
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27 | // thread for the instruction in each stage and whether |
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28 | // the instruction writes to the register file. It won't |
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29 | // bypass if bypass_enable is low or rs =0. This is for the |
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30 | // special case of rs1 which has two bypass sets. One uses |
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31 | // the pc as an input (other) and one does not. |
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32 | */ |
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33 | module sparc_exu_eclbyplog_rs1 (/*AUTOARG*/ |
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34 | // Outputs |
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35 | rs_sel_mux1_m, rs_sel_mux1_w, rs_sel_mux1_w2, rs_sel_mux1_other, |
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36 | rs_sel_mux2_usemux1, rs_sel_mux2_rf, rs_sel_mux2_e, |
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37 | rs_sel_mux2_ld, rs_sel_longmux_g2, rs_sel_longmux_w2, |
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38 | rs_sel_longmux_ldxa, ecl_byp_rcc_mux1_sel_m, |
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39 | ecl_byp_rcc_mux1_sel_w, ecl_byp_rcc_mux1_sel_w2, |
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40 | ecl_byp_rcc_mux1_sel_other, ecl_byp_rcc_mux2_sel_usemux1, |
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41 | ecl_byp_rcc_mux2_sel_rf, ecl_byp_rcc_mux2_sel_e, |
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42 | ecl_byp_rcc_mux2_sel_ld, |
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43 | // Inputs |
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44 | sehold, use_other, rs, rd_e, rd_m, ecl_irf_rd_w, ld_rd_g, |
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45 | wb_byplog_rd_w2, wb_byplog_rd_g2, tid_d, thr_match_de, |
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46 | thr_match_dm, ecl_irf_tid_w, ld_thr_match_dg, wb_byplog_tid_w2, |
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47 | ld_thr_match_dg2, ifu_exu_kill_e, wb_e, bypass_m, |
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48 | lsu_exu_dfill_vld_g, bypass_w, wb_byplog_wen_w2, wb_byplog_wen_g2, |
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49 | ecl_byp_ldxa_g |
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50 | ) ; |
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51 | input sehold; |
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52 | input use_other; |
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53 | input [4:0] rs; // source register |
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54 | input [4:0] rd_e; // destination regs for all stages |
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55 | input [4:0] rd_m; |
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56 | input [4:0] ecl_irf_rd_w; |
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57 | input [4:0] ld_rd_g; |
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58 | input [4:0] wb_byplog_rd_w2; |
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59 | input [4:0] wb_byplog_rd_g2; |
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60 | input [1:0] tid_d; |
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61 | input thr_match_de; |
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62 | input thr_match_dm; |
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63 | input [1:0] ecl_irf_tid_w; |
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64 | input ld_thr_match_dg; |
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65 | input [1:0] wb_byplog_tid_w2; |
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66 | input ld_thr_match_dg2; |
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67 | input ifu_exu_kill_e; |
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68 | input wb_e; // whether each stage writes to reg |
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69 | input bypass_m; // file |
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70 | input lsu_exu_dfill_vld_g; |
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71 | input bypass_w; |
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72 | input wb_byplog_wen_w2; |
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73 | input wb_byplog_wen_g2; |
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74 | input ecl_byp_ldxa_g; |
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75 | |
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76 | output rs_sel_mux1_m; |
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77 | output rs_sel_mux1_w; |
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78 | output rs_sel_mux1_w2; |
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79 | output rs_sel_mux1_other; |
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80 | output rs_sel_mux2_usemux1; |
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81 | output rs_sel_mux2_rf; |
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82 | output rs_sel_mux2_e; |
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83 | output rs_sel_mux2_ld; |
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84 | output rs_sel_longmux_g2; |
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85 | output rs_sel_longmux_w2; |
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86 | output rs_sel_longmux_ldxa; |
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87 | output ecl_byp_rcc_mux1_sel_m; |
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88 | output ecl_byp_rcc_mux1_sel_w; |
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89 | output ecl_byp_rcc_mux1_sel_w2; |
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90 | output ecl_byp_rcc_mux1_sel_other; |
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91 | output ecl_byp_rcc_mux2_sel_usemux1; |
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92 | output ecl_byp_rcc_mux2_sel_rf; |
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93 | output ecl_byp_rcc_mux2_sel_e; |
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94 | output ecl_byp_rcc_mux2_sel_ld; |
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95 | |
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96 | |
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97 | wire use_e, use_m, use_w, use_w2, use_rf, use_ld, use_ldxa; |
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98 | wire match_e, match_m, match_w, match_w2, match_ld; // outputs of comparison |
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99 | wire match_g2; |
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100 | wire bypass; // boolean that allows bypassing |
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101 | wire rs_is_nonzero; |
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102 | wire rcc_bypass; |
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103 | |
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104 | // Don't bypass if rs == 0 or we are supposed to use other |
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105 | assign rs_is_nonzero = rs[0]|rs[1]|rs[2]|rs[3]|rs[4]; |
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106 | assign bypass = rs_is_nonzero & ~use_other & ~sehold; |
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107 | |
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108 | // Normal pipe priority: E, M, W, RF |
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109 | // Ld priority: LD, RF |
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110 | // W2 priority: W2, RF |
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111 | assign use_e = match_e & wb_e & ~ifu_exu_kill_e; |
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112 | assign use_m = match_m & bypass_m & ~use_e; |
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113 | assign use_w = match_w & bypass_w & ~use_m & ~use_e; |
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114 | assign use_ld = match_ld & lsu_exu_dfill_vld_g & ~ecl_byp_ldxa_g; |
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115 | assign use_ldxa = match_ld & ecl_byp_ldxa_g; |
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116 | assign use_w2 = (match_w2 & wb_byplog_wen_w2 | match_g2 & wb_byplog_wen_g2) & ~use_e & ~use_m; |
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117 | assign use_rf = ~use_w2 & ~use_w & ~use_m & ~use_e & ~use_ld & ~use_ldxa; |
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118 | |
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119 | // mux1[M, W, W2, OTHER(optional)] |
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120 | // mux2[mux1, RF, E, LD] |
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121 | assign rs_sel_mux2_e = (use_e & bypass); |
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122 | assign rs_sel_mux2_rf = ((use_rf | ~bypass) & ~use_other); |
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123 | assign rs_sel_mux2_ld = (use_ld & ~use_e & ~use_w & ~use_m & ~use_w2 & bypass); |
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124 | assign rs_sel_mux2_usemux1 = (use_other & ~sehold) | (~rs_sel_mux1_other & ~use_e); |
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125 | assign rs_sel_mux1_other = ~((use_m | use_w | use_w2 | use_ldxa) & bypass); |
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126 | assign rs_sel_mux1_w2 = ((use_ldxa | use_w2) & bypass); |
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127 | assign rs_sel_mux1_w = (use_w & ~use_w2 & ~use_ldxa & bypass); |
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128 | assign rs_sel_mux1_m = (use_m & ~use_w2 & ~use_ldxa & bypass); |
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129 | |
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130 | assign rs_sel_longmux_ldxa = use_ldxa; |
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131 | assign rs_sel_longmux_g2 = match_g2 & wb_byplog_wen_g2 & ~use_ldxa; |
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132 | assign rs_sel_longmux_w2 = ~use_ldxa & ~(match_g2 & wb_byplog_wen_g2); |
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133 | |
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134 | // Bypassing for cc generation (don't use other input) |
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135 | assign rcc_bypass = rs_is_nonzero; |
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136 | assign ecl_byp_rcc_mux2_sel_e = use_e & rcc_bypass; |
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137 | assign ecl_byp_rcc_mux2_sel_rf = use_rf | ~rcc_bypass; |
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138 | assign ecl_byp_rcc_mux2_sel_ld = use_ld & ~use_e & ~use_w & ~use_m & ~use_w2 & rcc_bypass; |
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139 | assign ecl_byp_rcc_mux2_sel_usemux1 = (use_m | use_w | use_w2 | use_ldxa) & rcc_bypass & ~use_e; |
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140 | assign ecl_byp_rcc_mux1_sel_other = ~(use_m | use_w | use_w2 | use_ldxa); |
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141 | assign ecl_byp_rcc_mux1_sel_w2 = use_w2 | use_ldxa; |
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142 | assign ecl_byp_rcc_mux1_sel_w = use_w & ~use_w2 & ~use_ldxa; |
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143 | assign ecl_byp_rcc_mux1_sel_m = use_m & ~use_w2 & ~use_ldxa; |
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144 | |
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145 | // Comparisons |
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146 | assign match_e = thr_match_de & (rs[4:0] == rd_e[4:0]); |
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147 | // sparc_exu_eclcomp7 e_comp7(.out(match_e), .in1({tid_d[1:0],rs[4:0]}), |
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148 | // .in2({ecl_rml_tid_e[1:0],rd_e[4:0]})); |
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149 | assign match_m = thr_match_dm & (rs[4:0] == rd_m[4:0]); |
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150 | // sparc_exu_eclcomp7 m_comp7(.out(match_m), .in1({tid_d[1:0],rs[4:0]}), |
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151 | // .in2({tid_m[1:0],rd_m[4:0]})); |
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152 | sparc_exu_eclcomp7 w_comp7(.out(match_w), .in1({tid_d[1:0],rs[4:0]}), |
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153 | .in2({ecl_irf_tid_w[1:0],ecl_irf_rd_w[4:0]})); |
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154 | sparc_exu_eclcomp7 w2_comp7(.out(match_w2), .in1({tid_d[1:0],rs[4:0]}), |
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155 | .in2({wb_byplog_tid_w2[1:0],wb_byplog_rd_w2[4:0]})); |
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156 | assign match_ld = ld_thr_match_dg & (rs[4:0] == ld_rd_g[4:0]); |
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157 | assign match_g2 = ld_thr_match_dg2 & (rs[4:0] == wb_byplog_rd_g2[4:0]); |
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158 | /* -----\/----- EXCLUDED -----\/----- |
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159 | sparc_exu_eclcomp7 ld_comp7(.out(match_ld), .in1({tid_d[1:0],rs[4:0]}), |
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160 | .in2({ld_tid_g[1:0],ld_rd_g[4:0]})); |
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161 | sparc_exu_eclcomp7 g2_comp7(.out(match_g2), .in1({tid_d[1:0],rs[4:0]}), |
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162 | .in2({wb_byplog_tid_g2[1:0],wb_byplog_rd_g2[4:0]})); |
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163 | -----/\----- EXCLUDED -----/\----- */ |
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164 | |
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165 | |
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166 | endmodule // sparc_exu_eclbyplog |
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