1 | // ========== Copyright Header Begin ========================================== |
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2 | // |
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3 | // OpenSPARC T1 Processor File: sparc_exu_reg.v |
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4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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6 | // |
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7 | // The above named program is free software; you can redistribute it and/or |
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8 | // modify it under the terms of the GNU General Public |
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9 | // License version 2 as published by the Free Software Foundation. |
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10 | // |
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11 | // The above named program is distributed in the hope that it will be |
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12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | // General Public License for more details. |
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15 | // |
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16 | // You should have received a copy of the GNU General Public |
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17 | // License along with this work; if not, write to the Free Software |
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18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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19 | // |
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20 | // ========== Copyright Header End ============================================ |
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21 | module sparc_exu_reg (/*AUTOARG*/ |
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22 | // Outputs |
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23 | data_out, |
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24 | // Inputs |
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25 | clk, se, thr_out, wen_w, thr_w, data_in_w |
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26 | ) ; |
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27 | parameter SIZE = 3; |
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28 | |
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29 | input clk; |
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30 | input se; |
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31 | input [3:0] thr_out; |
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32 | input wen_w; |
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33 | input [3:0] thr_w; |
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34 | input [SIZE -1:0] data_in_w; |
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35 | |
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36 | output [SIZE-1:0] data_out; |
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37 | |
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38 | wire [SIZE-1:0] data_thr0; |
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39 | wire [SIZE-1:0] data_thr1; |
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40 | wire [SIZE-1:0] data_thr2; |
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41 | wire [SIZE-1:0] data_thr3; |
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42 | wire [SIZE-1:0] data_thr0_next; |
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43 | wire [SIZE-1:0] data_thr1_next; |
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44 | wire [SIZE-1:0] data_thr2_next; |
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45 | wire [SIZE-1:0] data_thr3_next; |
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46 | |
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47 | wire wen_thr0_w; |
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48 | wire wen_thr1_w; |
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49 | wire wen_thr2_w; |
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50 | wire wen_thr3_w; |
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51 | |
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52 | ////////////////////////////////// |
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53 | // Output selection for reg |
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54 | ////////////////////////////////// |
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55 | `ifdef FPGA_SYN_1THREAD |
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56 | assign data_out[SIZE -1:0] = data_thr0[SIZE -1:0]; |
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57 | assign wen_thr0_w = (thr_w[0] & wen_w); |
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58 | // mux between new and current value |
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59 | mux2ds #(SIZE) data_next0_mux(.dout(data_thr0_next[SIZE -1:0]), |
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60 | .in0(data_thr0[SIZE -1:0]), |
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61 | .in1(data_in_w[SIZE -1:0]), |
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62 | .sel0(~wen_thr0_w), |
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63 | .sel1(wen_thr0_w)); |
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64 | dff_s #(SIZE) dff_reg_thr0(.din(data_thr0_next[SIZE -1:0]), .clk(clk), .q(data_thr0[SIZE -1:0]), |
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65 | .se(se), .si(), .so()); |
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66 | `else // !`ifdef FPGA_SYN_1THREAD |
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67 | |
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68 | // mux between the 4 regs |
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69 | mux4ds #(SIZE) mux_data_out1(.dout(data_out[SIZE -1:0]), .sel0(thr_out[0]), |
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70 | .sel1(thr_out[1]), .sel2(thr_out[2]), |
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71 | .sel3(thr_out[3]), .in0(data_thr0[SIZE -1:0]), |
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72 | .in1(data_thr1[SIZE -1:0]), .in2(data_thr2[SIZE -1:0]), |
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73 | .in3(data_thr3[SIZE -1:0])); |
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74 | |
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75 | ////////////////////////////////////// |
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76 | // Storage of reg |
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77 | ////////////////////////////////////// |
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78 | // enable input for each thread |
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79 | assign wen_thr0_w = (thr_w[0] & wen_w); |
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80 | assign wen_thr1_w = (thr_w[1] & wen_w); |
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81 | assign wen_thr2_w = (thr_w[2] & wen_w); |
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82 | assign wen_thr3_w = (thr_w[3] & wen_w); |
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83 | |
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84 | // mux between new and current value |
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85 | mux2ds #(SIZE) data_next0_mux(.dout(data_thr0_next[SIZE -1:0]), |
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86 | .in0(data_thr0[SIZE -1:0]), |
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87 | .in1(data_in_w[SIZE -1:0]), |
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88 | .sel0(~wen_thr0_w), |
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89 | .sel1(wen_thr0_w)); |
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90 | mux2ds #(SIZE) data_next1_mux(.dout(data_thr1_next[SIZE -1:0]), |
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91 | .in0(data_thr1[SIZE -1:0]), |
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92 | .in1(data_in_w[SIZE -1:0]), |
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93 | .sel0(~wen_thr1_w), |
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94 | .sel1(wen_thr1_w)); |
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95 | mux2ds #(SIZE) data_next2_mux(.dout(data_thr2_next[SIZE -1:0]), |
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96 | .in0(data_thr2[SIZE -1:0]), |
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97 | .in1(data_in_w[SIZE -1:0]), |
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98 | .sel0(~wen_thr2_w), |
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99 | .sel1(wen_thr2_w)); |
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100 | mux2ds #(SIZE) data_next3_mux(.dout(data_thr3_next[SIZE -1:0]), |
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101 | .in0(data_thr3[SIZE -1:0]), |
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102 | .in1(data_in_w[SIZE -1:0]), |
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103 | .sel0(~wen_thr3_w), |
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104 | .sel1(wen_thr3_w)); |
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105 | |
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106 | // store new value |
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107 | dff_s #(SIZE) dff_reg_thr0(.din(data_thr0_next[SIZE -1:0]), .clk(clk), .q(data_thr0[SIZE -1:0]), |
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108 | .se(se), .si(), .so()); |
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109 | dff_s #(SIZE) dff_reg_thr1(.din(data_thr1_next[SIZE -1:0]), .clk(clk), .q(data_thr1[SIZE -1:0]), |
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110 | .se(se), .si(), .so()); |
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111 | dff_s #(SIZE) dff_reg_thr2(.din(data_thr2_next[SIZE -1:0]), .clk(clk), .q(data_thr2[SIZE -1:0]), |
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112 | .se(se), .si(), .so()); |
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113 | dff_s #(SIZE) dff_reg_thr3(.din(data_thr3_next[SIZE -1:0]), .clk(clk), .q(data_thr3[SIZE -1:0]), |
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114 | .se(se), .si(), .so()); |
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115 | `endif // !`ifdef FPGA_SYN_1THREAD |
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116 | |
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117 | endmodule // sparc_exu_reg |
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