| 1 | // ========== Copyright Header Begin ========================================== |
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| 2 | // |
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| 3 | // OpenSPARC T1 Processor File: lsu_stb_rwdp.v |
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| 4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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| 5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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| 6 | // |
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| 7 | // The above named program is free software; you can redistribute it and/or |
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| 8 | // modify it under the terms of the GNU General Public |
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| 9 | // License version 2 as published by the Free Software Foundation. |
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| 10 | // |
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| 11 | // The above named program is distributed in the hope that it will be |
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| 12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | // General Public License for more details. |
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| 15 | // |
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| 16 | // You should have received a copy of the GNU General Public |
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| 17 | // License along with this work; if not, write to the Free Software |
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| 18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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| 19 | // |
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| 20 | // ========== Copyright Header End ============================================ |
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| 21 | /////////////////////////////////////////////////////////////////// |
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| 22 | /* |
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| 23 | // Description: Datapath for STB |
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| 24 | // - Mainly for formatting stb data |
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| 25 | */ |
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| 26 | //////////////////////////////////////////////////////////////////////// |
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| 27 | // Global header file includes |
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| 28 | //////////////////////////////////////////////////////////////////////// |
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| 29 | `include "sys.h" // system level definition file which contains the |
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| 30 | // time scale definition |
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| 31 | |
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| 32 | `include "iop.h" |
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| 33 | |
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| 34 | //////////////////////////////////////////////////////////////////////// |
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| 35 | // Local header file includes / local defines |
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| 36 | //////////////////////////////////////////////////////////////////////// |
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| 37 | |
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| 38 | module lsu_stb_rwdp (/*AUTOARG*/ |
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| 39 | // Outputs |
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| 40 | so, stb_rdata_ramd_buf, stb_rdata_ramd_b74_buf, lsu_stb_st_data_g, |
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| 41 | // Inputs |
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| 42 | rclk, si, se, rst_tri_en, exu_lsu_rs3_data_e, |
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| 43 | lsu_stb_data_early_sel_e, lsu_stb_data_final_sel_m, |
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| 44 | exu_lsu_rs2_data_e, lsu_st_sz_bhww_m, lsu_st_sz_dw_m, |
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| 45 | lsu_st_sz_bhw_m, lsu_st_sz_wdw_m, lsu_st_sz_b_m, lsu_st_sz_w_m, |
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| 46 | lsu_st_sz_hw_m, lsu_st_sz_hww_m, ffu_lsu_data, lsu_st_hw_le_g, |
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| 47 | lsu_st_w_or_dbl_le_g, lsu_st_x_le_g, lsu_swap_sel_default_g, |
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| 48 | lsu_swap_sel_default_byte_7_2_g, stb_rdata_ramd, |
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| 49 | stb_rdata_ramd_b74 |
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| 50 | ) ; |
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| 51 | |
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| 52 | input rclk ; |
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| 53 | input si; |
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| 54 | output so; |
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| 55 | input se; |
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| 56 | input rst_tri_en; |
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| 57 | |
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| 58 | input [63:0] exu_lsu_rs3_data_e ; // data for store. |
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| 59 | input [3:0] lsu_stb_data_early_sel_e ;// early source of data for stb |
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| 60 | input lsu_stb_data_final_sel_m ;// early source of data for stb |
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| 61 | input [63:0] exu_lsu_rs2_data_e ; // rs2 data for cas. |
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| 62 | input lsu_st_sz_bhww_m ; // byte or hword or word |
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| 63 | input lsu_st_sz_dw_m ; // double word |
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| 64 | input lsu_st_sz_bhw_m ; // byte or hword |
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| 65 | input lsu_st_sz_wdw_m ; // word or dword |
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| 66 | input lsu_st_sz_b_m ; // byte |
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| 67 | input lsu_st_sz_w_m ; // word |
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| 68 | input lsu_st_sz_hw_m ; // hword |
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| 69 | input lsu_st_sz_hww_m ; // hword or word |
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| 70 | input [63:0] ffu_lsu_data ; // fp store data - m stage |
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| 71 | //input lsu_bendian_access_g ; // bendian st |
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| 72 | //input lsu_stdbl_inst_m ; // stdbl |
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| 73 | |
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| 74 | input lsu_st_hw_le_g; |
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| 75 | input lsu_st_w_or_dbl_le_g; |
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| 76 | input lsu_st_x_le_g; |
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| 77 | input lsu_swap_sel_default_g; |
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| 78 | input lsu_swap_sel_default_byte_7_2_g; |
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| 79 | |
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| 80 | input [69:0] stb_rdata_ramd; |
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| 81 | input stb_rdata_ramd_b74; |
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| 82 | |
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| 83 | output [69:0] stb_rdata_ramd_buf; |
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| 84 | output stb_rdata_ramd_b74_buf; |
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| 85 | |
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| 86 | output [63:0] lsu_stb_st_data_g ; // data to be written to stb |
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| 87 | |
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| 88 | wire [7:0] byte0, byte1, byte2, byte3 ; |
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| 89 | wire [7:0] byte4, byte5, byte6, byte7 ; |
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| 90 | wire [7:0] swap_byte0, swap_byte1, swap_byte2, swap_byte3 ; |
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| 91 | wire [7:0] swap_byte4, swap_byte5, swap_byte6, swap_byte7 ; |
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| 92 | |
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| 93 | wire [63:0] stb_st_data_g ; |
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| 94 | wire [63:0] stb_st_data_early_e ; |
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| 95 | wire [63:0] stb_st_data_early_m ; |
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| 96 | wire [63:0] stb_st_data_final_m ; |
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| 97 | wire st_sz_bhww_g ; |
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| 98 | wire st_sz_dw_g ; |
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| 99 | wire st_sz_bhw_g ; |
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| 100 | wire st_sz_wdw_g ; |
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| 101 | wire st_sz_b_g ; |
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| 102 | wire st_sz_w_g ; |
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| 103 | wire st_sz_hw_g ; |
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| 104 | wire st_sz_hww_g ; |
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| 105 | //wire bendian ; |
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| 106 | //wire stdbl_g ; |
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| 107 | |
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| 108 | wire clk; |
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| 109 | assign clk = rclk; |
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| 110 | |
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| 111 | //assign stb_st_data_early_e[63:0] = //@@ bw_u1_muxi41d_2x |
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| 112 | // lsu_stb_data_early_sel_e[0] ? 64'hffff_ffff_ffff_ffff : // ldstub writes all ones |
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| 113 | // lsu_stb_data_early_sel_e[1] ? exu_lsu_rs2_data_e[63:0] : // cas pkt1 uses rs2 |
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| 114 | // lsu_stb_data_early_sel_e[2] ? exu_lsu_rs3_data_e[63:0] : // use rs3/rd data. |
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| 115 | // lsu_stb_data_early_sel_e[3] ? {exu_lsu_rs2_data_e[31:0],exu_lsu_rs3_data_e[31:0]} : |
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| 116 | // else std non-alt |
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| 117 | // 64'hxxxx_xxxx_xxxx_xxxx ; |
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| 118 | |
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| 119 | mux4ds #(64) stb_st_data_early_e_mx ( |
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| 120 | .in0 (64'hffff_ffff_ffff_ffff), |
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| 121 | .in1 (exu_lsu_rs2_data_e[63:0]), |
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| 122 | .in2 (exu_lsu_rs3_data_e[63:0]), |
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| 123 | .in3 ({exu_lsu_rs2_data_e[31:0],exu_lsu_rs3_data_e[31:0]}), |
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| 124 | .sel0(lsu_stb_data_early_sel_e[0]), |
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| 125 | .sel1(lsu_stb_data_early_sel_e[1]), |
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| 126 | .sel2(lsu_stb_data_early_sel_e[2]), |
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| 127 | .sel3(lsu_stb_data_early_sel_e[3]), |
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| 128 | .dout(stb_st_data_early_e[63:0])); |
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| 129 | |
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| 130 | |
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| 131 | // Stage early data to m |
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| 132 | dff_s #(64) stgm_rs2 ( //@@ bw_u1_soffi_2x |
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| 133 | .din (stb_st_data_early_e[63:0]), |
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| 134 | .q (stb_st_data_early_m[63:0]), |
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| 135 | .clk (clk), |
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| 136 | .se (se), .si (), .so () |
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| 137 | ); |
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| 138 | |
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| 139 | assign stb_st_data_final_m[63:0] = //@@ bw_u1_muxi21_2x |
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| 140 | lsu_stb_data_final_sel_m ? stb_st_data_early_m[63:0] : ffu_lsu_data[63:0] ; // mux in fpst data |
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| 141 | |
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| 142 | // Precursor of data to be stored in stb |
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| 143 | // For ldstub, all one's need to be written to stb. |
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| 144 | // For cas/swap, data remains unmodified. |
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| 145 | // Stage final data to g |
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| 146 | dff_s #(64) stgg_rs2 ( //@@ bw_u1_soffi_2x |
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| 147 | .din (stb_st_data_final_m[63:0]), |
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| 148 | .q (stb_st_data_g[63:0]), |
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| 149 | .clk (clk), |
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| 150 | .se (se), .si (), .so () |
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| 151 | ); |
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| 152 | |
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| 153 | dff_s #(8) stgm_sel ( //@@ bw_u1_soff_8x |
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| 154 | .din ({lsu_st_sz_bhww_m,lsu_st_sz_dw_m,lsu_st_sz_bhw_m,lsu_st_sz_wdw_m, |
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| 155 | lsu_st_sz_b_m,lsu_st_sz_w_m,lsu_st_sz_hw_m,lsu_st_sz_hww_m}), |
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| 156 | .q ({st_sz_bhww_g,st_sz_dw_g,st_sz_bhw_g,st_sz_wdw_g, |
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| 157 | st_sz_b_g,st_sz_w_g,st_sz_hw_g,st_sz_hww_g}), |
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| 158 | .clk (clk), |
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| 159 | .se (se), .si (), .so () |
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| 160 | ); |
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| 161 | |
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| 162 | // Now format data for st data. |
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| 163 | assign byte0[7:0] = stb_st_data_g[7:0] ; //@@ PASS |
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| 164 | assign byte1[7:0] = stb_st_data_g[15:8] ; //@@ PASS |
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| 165 | assign byte2[7:0] = stb_st_data_g[23:16] ; //@@ PASS |
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| 166 | assign byte3[7:0] = stb_st_data_g[31:24] ; //@@ PASS |
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| 167 | assign byte4[7:0] = stb_st_data_g[39:32] ; //@@ PASS |
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| 168 | assign byte5[7:0] = stb_st_data_g[47:40] ; //@@ PASS |
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| 169 | assign byte6[7:0] = stb_st_data_g[55:48] ; //@@ PASS |
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| 170 | assign byte7[7:0] = stb_st_data_g[63:56] ; //@@ PASS |
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| 171 | |
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| 172 | |
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| 173 | //assign bendian = lsu_bendian_access_g ; // bendian store |
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| 174 | |
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| 175 | // Control needs to move to lsu_stb_rwctl once this is fully tested. |
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| 176 | |
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| 177 | // First do swap for big-endian vs little-endian case. |
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| 178 | |
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| 179 | //wire swap_sel_default ; |
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| 180 | |
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| 181 | //assign swap_sel_default = bendian | (~bendian & st_sz_b_g) ; |
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| 182 | |
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| 183 | // swap byte0 |
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| 184 | //assign swap_byte0[7:0] = //@@ bw_u1_muxi41d_4x |
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| 185 | // lsu_swap_sel_default_g ? byte0[7:0] : |
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| 186 | // lsu_st_hw_le_g ? byte1[7:0] : |
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| 187 | // lsu_st_w_or_dbl_le_g ? byte3[7:0] : |
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| 188 | // lsu_st_x_le_g ? byte7[7:0] : 8'bxxxx_xxxx ; |
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| 189 | |
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| 190 | mux4ds #(8) swap_byte0_mx ( |
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| 191 | .in0 (byte0[7:0]), .sel0(lsu_swap_sel_default_g), |
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| 192 | .in1 (byte1[7:0]), .sel1(lsu_st_hw_le_g), |
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| 193 | .in2 (byte3[7:0]), .sel2(lsu_st_w_or_dbl_le_g), |
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| 194 | .in3 (byte7[7:0]), .sel3(lsu_st_x_le_g), |
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| 195 | .dout(swap_byte0[7:0])); |
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| 196 | |
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| 197 | // swap byte1 |
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| 198 | //assign swap_byte1[7:0] = //@@ bw_u1_muxi41d_4x |
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| 199 | // lsu_swap_sel_default_g ? byte1[7:0] : |
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| 200 | // lsu_st_hw_le_g ? byte0[7:0] : |
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| 201 | // lsu_st_w_or_dbl_le_g ? byte2[7:0] : |
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| 202 | // lsu_st_x_le_g ? byte6[7:0] : 8'bxxxx_xxxx ; |
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| 203 | |
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| 204 | mux4ds #(8) swap_byte1_mx ( |
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| 205 | .in0 (byte1[7:0]), .sel0(lsu_swap_sel_default_g), |
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| 206 | .in1 (byte0[7:0]), .sel1(lsu_st_hw_le_g), |
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| 207 | .in2 (byte2[7:0]), .sel2(lsu_st_w_or_dbl_le_g), |
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| 208 | .in3 (byte6[7:0]), .sel3(lsu_st_x_le_g), |
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| 209 | .dout (swap_byte1[7:0])); |
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| 210 | |
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| 211 | // swap byte2 |
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| 212 | //assign swap_byte2[7:0] = //@@ bw_u1_muxi31d_4x |
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| 213 | // lsu_swap_sel_default_g ? byte2[7:0] : |
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| 214 | // lsu_st_w_or_dbl_le_g ? byte1[7:0] : |
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| 215 | // lsu_st_x_le_g ? byte5[7:0] : 8'bxxxx_xxxx ; |
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| 216 | |
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| 217 | mux3ds #(8) swap_byte2_mx ( |
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| 218 | .in0 (byte2[7:0]), .sel0(lsu_swap_sel_default_byte_7_2_g), |
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| 219 | .in1 (byte1[7:0]), .sel1(lsu_st_w_or_dbl_le_g), |
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| 220 | .in2 (byte5[7:0]), .sel2(lsu_st_x_le_g), |
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| 221 | .dout (swap_byte2[7:0])); |
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| 222 | |
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| 223 | // swap byte3 |
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| 224 | //assign swap_byte3[7:0] = //@@ bw_u1_muxi31d_4x |
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| 225 | // lsu_swap_sel_default_g ? byte3[7:0] : |
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| 226 | // lsu_st_w_or_dbl_le_g ? byte0[7:0] : |
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| 227 | // lsu_st_x_le_g ? byte4[7:0] : 8'bxxxx_xxxx ; |
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| 228 | |
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| 229 | mux3ds #(8) swap_byte3_mx ( |
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| 230 | .in0 (byte3[7:0]), .sel0(lsu_swap_sel_default_byte_7_2_g), |
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| 231 | .in1 (byte0[7:0]), .sel1(lsu_st_w_or_dbl_le_g), |
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| 232 | .in2 (byte4[7:0]), .sel2(lsu_st_x_le_g), |
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| 233 | .dout(swap_byte3[7:0])); |
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| 234 | |
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| 235 | // swap byte4 |
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| 236 | //assign swap_byte4[7:0] = //@@ bw_u1_muxi31d_4x |
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| 237 | // lsu_swap_sel_default_g ? byte4[7:0] : |
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| 238 | // lsu_st_w_or_dbl_le_g ? byte7[7:0] : |
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| 239 | // lsu_st_x_le_g ? byte3[7:0] : 8'bxxxx_xxxx ; |
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| 240 | |
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| 241 | mux3ds #(8) swap_byte4_mx ( |
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| 242 | .in0 (byte4[7:0]), .sel0(lsu_swap_sel_default_byte_7_2_g), |
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| 243 | .in1 (byte7[7:0]), .sel1(lsu_st_w_or_dbl_le_g), |
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| 244 | .in2 (byte3[7:0]), .sel2(lsu_st_x_le_g), |
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| 245 | .dout(swap_byte4[7:0])); |
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| 246 | |
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| 247 | // swap byte5 |
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| 248 | //assign swap_byte5[7:0] = //@@ bw_u1_muxi31d_4x |
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| 249 | // lsu_swap_sel_default_g ? byte5[7:0] : |
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| 250 | // lsu_st_w_or_dbl_le_g ? byte6[7:0] : |
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| 251 | // lsu_st_x_le_g ? byte2[7:0] : 8'bxxxx_xxxx ; |
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| 252 | |
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| 253 | mux3ds #(8) swap_byte5_mx ( |
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| 254 | .in0 (byte5[7:0]), .sel0(lsu_swap_sel_default_byte_7_2_g), |
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| 255 | .in1 (byte6[7:0]), .sel1(lsu_st_w_or_dbl_le_g), |
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| 256 | .in2 (byte2[7:0]), .sel2(lsu_st_x_le_g), |
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| 257 | .dout(swap_byte5[7:0])); |
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| 258 | |
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| 259 | // swap byte6 |
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| 260 | //assign swap_byte6[7:0] = //@@ bw_u1_muxi31d_4x |
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| 261 | // lsu_swap_sel_default_g ? byte6[7:0] : |
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| 262 | // lsu_st_w_or_dbl_le_g ? byte5[7:0] : |
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| 263 | // lsu_st_x_le_g ? byte1[7:0] : 8'bxxxx_xxxx ; |
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| 264 | |
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| 265 | mux3ds #(8) swap_byte6_mx ( |
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| 266 | .in0 (byte6[7:0]), .sel0 (lsu_swap_sel_default_byte_7_2_g), |
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| 267 | .in1 (byte5[7:0]), .sel1 (lsu_st_w_or_dbl_le_g), |
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| 268 | .in2 (byte1[7:0]), .sel2 (lsu_st_x_le_g), |
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| 269 | .dout(swap_byte6[7:0])); |
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| 270 | |
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| 271 | // swap byte7 |
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| 272 | //assign swap_byte7[7:0] = //@@ bw_u1_muxi31d_4x |
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| 273 | // lsu_swap_sel_default_g ? byte7[7:0] : |
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| 274 | // lsu_st_w_or_dbl_le_g ? byte4[7:0] : |
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| 275 | // lsu_st_x_le_g ? byte0[7:0] : 8'bxxxx_xxxx ; |
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| 276 | |
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| 277 | mux3ds #(8) swap_byte7_mx ( |
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| 278 | .in0 (byte7[7:0]), .sel0 (lsu_swap_sel_default_byte_7_2_g), |
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| 279 | .in1 (byte4[7:0]), .sel1 (lsu_st_w_or_dbl_le_g), |
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| 280 | .in2 (byte0[7:0]), .sel2 (lsu_st_x_le_g), |
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| 281 | .dout (swap_byte7[7:0])); |
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| 282 | |
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| 283 | // Now replicate date across 8 bytes. |
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| 284 | |
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| 285 | // replicated byte0 |
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| 286 | assign lsu_stb_st_data_g[7:0] = swap_byte0[7:0] ; // all data sizes //@@ bw_u1_inv_8x |
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| 287 | |
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| 288 | // replicated byte1 |
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| 289 | assign lsu_stb_st_data_g[15:8] = //@@ bw_u1_muxi21_6x |
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| 290 | st_sz_b_g ? swap_byte0[7:0] : swap_byte1[7:0] ; |
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| 291 | |
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| 292 | // replicated byte2 |
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| 293 | assign lsu_stb_st_data_g[23:16] = //@@ bw_u1_muxi21_6x |
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| 294 | st_sz_bhw_g ? swap_byte0[7:0] : swap_byte2[7:0] ; |
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| 295 | |
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| 296 | // replicated byte3 |
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| 297 | //assign lsu_stb_st_data_g[31:24] = //@@ bw_u1_muxi31d_6x |
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| 298 | // st_sz_b_g ? swap_byte0 : // swap_byte |
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| 299 | // st_sz_hw_g ? swap_byte1 : // hword |
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| 300 | // st_sz_wdw_g ? swap_byte3 : // dword or word |
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| 301 | // 8'bxxxx_xxxx ; |
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| 302 | |
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| 303 | wire st_sz_b_g_sel, st_sz_hw_g_sel, st_sz_wdw_g_sel; |
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| 304 | assign st_sz_b_g_sel = st_sz_b_g & ~rst_tri_en; |
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| 305 | assign st_sz_hw_g_sel = st_sz_hw_g & ~rst_tri_en; |
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| 306 | assign st_sz_wdw_g_sel = st_sz_wdw_g | rst_tri_en; |
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| 307 | |
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| 308 | mux3ds #(8) rpl_byte3_mx ( |
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| 309 | .in0 (swap_byte0[7:0]), .sel0 (st_sz_b_g_sel), |
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| 310 | .in1 (swap_byte1[7:0]), .sel1 (st_sz_hw_g_sel), |
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| 311 | .in2 (swap_byte3[7:0]), .sel2 (st_sz_wdw_g_sel), |
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| 312 | .dout (lsu_stb_st_data_g[31:24])); |
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| 313 | |
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| 314 | // replicated byte4 |
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| 315 | assign lsu_stb_st_data_g[39:32] = //@@ bw_u1_muxi21_6x |
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| 316 | st_sz_bhww_g ? swap_byte0[7:0] : swap_byte4[7:0] ; // dword |
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| 317 | |
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| 318 | |
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| 319 | // replicated byte5 |
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| 320 | //assign lsu_stb_st_data_g[47:40] = //@@ bw_u1_muxi31d_6x |
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| 321 | // st_sz_b_g ? swap_byte0 : // swap_byte |
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| 322 | // st_sz_hww_g ? swap_byte1 : // hword or word |
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| 323 | // st_sz_dw_g ? swap_byte5 : // dword |
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| 324 | // 8'bxxxx_xxxx ; |
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| 325 | |
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| 326 | wire st_sz_hww_g_sel, st_sz_dw_g_sel; |
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| 327 | assign st_sz_hww_g_sel = st_sz_hww_g & ~rst_tri_en; |
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| 328 | assign st_sz_dw_g_sel = st_sz_dw_g | rst_tri_en; |
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| 329 | |
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| 330 | mux3ds #(8) rpl_byte5_mx ( |
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| 331 | .in0 (swap_byte0[7:0]), .sel0(st_sz_b_g_sel), |
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| 332 | .in1 (swap_byte1[7:0]), .sel1(st_sz_hww_g_sel), |
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| 333 | .in2 (swap_byte5[7:0]), .sel2(st_sz_dw_g_sel), |
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| 334 | .dout(lsu_stb_st_data_g[47:40])); |
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| 335 | |
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| 336 | // replicated byte6 |
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| 337 | //assign lsu_stb_st_data_g[55:48] = //@@ bw_u1_muxi31d_6x |
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| 338 | // st_sz_bhw_g ? swap_byte0 : // swap_byte or hword |
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| 339 | // st_sz_w_g ? swap_byte2 : // word |
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| 340 | // st_sz_wdw_g ? swap_byte6 : // dword |
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| 341 | // 8'bxxxx_xxxx ; |
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| 342 | |
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| 343 | wire st_sz_bhw_g_sel, st_sz_w_g_sel; |
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| 344 | assign st_sz_bhw_g_sel = st_sz_bhw_g & ~rst_tri_en; |
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| 345 | assign st_sz_w_g_sel = st_sz_w_g & ~rst_tri_en; |
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| 346 | |
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| 347 | |
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| 348 | mux3ds #(8) rpl_byte6_mx ( |
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| 349 | .in0 (swap_byte0[7:0]), |
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| 350 | .in1 (swap_byte2[7:0]), |
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| 351 | .in2 (swap_byte6[7:0]), |
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| 352 | .sel0(st_sz_bhw_g_sel), |
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| 353 | .sel1(st_sz_w_g_sel), |
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| 354 | .sel2(st_sz_dw_g_sel), |
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| 355 | .dout(lsu_stb_st_data_g[55:48])); |
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| 356 | |
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| 357 | // replicated byte7 |
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| 358 | //assign lsu_stb_st_data_g[63:56] = //@@ bw_u1_muxi41d_6x |
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| 359 | // st_sz_b_g ? swap_byte0 : // swap_byte |
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| 360 | // st_sz_hw_g ? swap_byte1 : // hword |
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| 361 | // st_sz_w_g ? swap_byte3 : // word |
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| 362 | // st_sz_dw_g ? swap_byte7 : // dword |
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| 363 | // 8'bxxxx_xxxx ; |
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| 364 | |
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| 365 | mux4ds #(8) rpl_byte7_mx ( |
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| 366 | .in0(swap_byte0[7:0]), .sel0(st_sz_b_g_sel), |
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| 367 | .in1(swap_byte1[7:0]), .sel1(st_sz_hw_g_sel), |
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| 368 | .in2(swap_byte3[7:0]), .sel2(st_sz_w_g_sel), |
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| 369 | .in3(swap_byte7[7:0]), .sel3(st_sz_dw_g_sel), |
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| 370 | .dout (lsu_stb_st_data_g[63:56])); |
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| 371 | |
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| 372 | //========================================================= |
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| 373 | //stb rdata buffer |
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| 374 | assign stb_rdata_ramd_buf[69:0] = stb_rdata_ramd[69:0]; |
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| 375 | assign stb_rdata_ramd_b74_buf = stb_rdata_ramd_b74; |
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| 376 | |
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| 377 | endmodule |
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