| [6] | 1 | // ========== Copyright Header Begin ========================================== |
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| 2 | // |
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| 3 | // OpenSPARC T1 Processor File: sparc_mul_top.v |
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| 4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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| 5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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| 6 | // |
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| 7 | // The above named program is free software; you can redistribute it and/or |
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| 8 | // modify it under the terms of the GNU General Public |
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| 9 | // License version 2 as published by the Free Software Foundation. |
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| 10 | // |
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| 11 | // The above named program is distributed in the hope that it will be |
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| 12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | // General Public License for more details. |
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| 15 | // |
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| 16 | // You should have received a copy of the GNU General Public |
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| 17 | // License along with this work; if not, write to the Free Software |
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| 18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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| 19 | // |
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| 20 | // ========== Copyright Header End ============================================ |
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| 21 | module sparc_mul_top(/*AUTOARG*/ |
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| 22 | // Outputs |
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| 23 | mul_exu_ack, mul_spu_ack, mul_spu_shf_ack, mul_data_out, so, |
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| 24 | // Inputs |
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| 25 | rclk, grst_l, arst_l, exu_mul_input_vld, exu_mul_rs1_data, exu_mul_rs2_data, |
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| 26 | spu_mul_req_vld, spu_mul_acc, spu_mul_areg_shf, spu_mul_areg_rst, |
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| 27 | spu_mul_op1_data, spu_mul_op2_data, spu_mul_mulres_lshft, si, se |
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| 28 | ); |
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| 29 | |
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| 30 | input rclk; |
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| 31 | input grst_l; // system reset |
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| 32 | input arst_l; // async reset |
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| 33 | input si; // scan in |
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| 34 | input se; // scan enablen |
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| 35 | input exu_mul_input_vld; // EXU multipler op request |
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| 36 | input [63:0] exu_mul_rs1_data; // EXU multipler Op1 |
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| 37 | input [63:0] exu_mul_rs2_data; // EXU multipler Op2 |
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| 38 | input spu_mul_req_vld; // SPU multipler op request |
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| 39 | input spu_mul_acc; // MAC Op: ACCUM += op1 * op2 if spu_mul_acc=1 |
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| 40 | // Bypass Op: Out = ACCUM * op1 if spu_mul_acc=0 |
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| 41 | input spu_mul_areg_shf; // Shift >> 64 ACCUM register |
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| 42 | input spu_mul_areg_rst; // Reset of ACCUM register (136-bit) |
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| 43 | input [63:0] spu_mul_op1_data; // SPU multiplier Op1 |
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| 44 | input [63:0] spu_mul_op2_data; // SPU multiplier Op2 |
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| 45 | |
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| 46 | input spu_mul_mulres_lshft; |
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| 47 | |
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| 48 | output so; // scan_out |
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| 49 | output mul_exu_ack; // ack signal for EXU mul operation |
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| 50 | output mul_spu_ack; // ack signal for SPU MAC and Bypass mul operation |
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| 51 | output mul_spu_shf_ack; // acl signal for ACCUM >> 64 operation |
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| 52 | output [63:0] mul_data_out; // Shared output data for both EXU and SPU |
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| 53 | |
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| 54 | wire acc_imm, acc_actc2, acc_actc3, acc_actc5, acc_reg_enb; |
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| 55 | wire acc_reg_rst, acc_reg_shf; |
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| 56 | wire byp_sel, byp_imm, spick, x2; |
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| 57 | wire c0_act; |
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| 58 | |
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| 59 | wire rst_l; |
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| 60 | wire clk; |
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| 61 | |
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| 62 | assign clk = rclk ; |
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| 63 | |
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| 64 | dffrl_async rstff ( |
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| 65 | .din (grst_l), |
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| 66 | .clk (clk), |
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| 67 | .rst_l (arst_l), |
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| 68 | .q (rst_l), |
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| 69 | .se (se), |
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| 70 | .si (), |
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| 71 | .so ()); |
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| 72 | |
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| 73 | sparc_mul_cntl control ( |
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| 74 | .ecl_mul_req_vld (exu_mul_input_vld), |
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| 75 | .spu_mul_req_vld (spu_mul_req_vld), |
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| 76 | .spu_mul_acc (spu_mul_acc), |
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| 77 | .spu_mul_areg_shf (spu_mul_areg_shf), |
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| 78 | .spu_mul_areg_rst (spu_mul_areg_rst), |
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| 79 | .spu_mul_mulres_lshft (spu_mul_mulres_lshft), |
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| 80 | .c0_act (c0_act), |
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| 81 | .spick (spick), |
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| 82 | .byp_sel (byp_sel), |
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| 83 | .byp_imm (byp_imm), |
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| 84 | .acc_imm (acc_imm), |
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| 85 | .acc_actc2 (acc_actc2), |
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| 86 | .acc_actc3 (acc_actc3), |
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| 87 | .acc_actc5 (acc_actc5), |
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| 88 | .acc_reg_enb (acc_reg_enb), |
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| 89 | .acc_reg_rst (acc_reg_rst), |
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| 90 | .acc_reg_shf (acc_reg_shf), |
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| 91 | .x2 (x2), |
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| 92 | .mul_ecl_ack (mul_exu_ack), |
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| 93 | .mul_spu_ack (mul_spu_ack), |
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| 94 | .mul_spu_shf_ack (mul_spu_shf_ack), |
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| 95 | .rst_l (rst_l), |
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| 96 | .rclk (clk)); |
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| 97 | |
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| 98 | sparc_mul_dp dpath ( |
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| 99 | .ecl_mul_rs1_data (exu_mul_rs1_data), |
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| 100 | .ecl_mul_rs2_data (exu_mul_rs2_data), |
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| 101 | .spu_mul_op1_data (spu_mul_op1_data), |
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| 102 | .spu_mul_op2_data (spu_mul_op2_data), |
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| 103 | .valid (c0_act), |
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| 104 | .spick (spick), |
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| 105 | .byp_sel (byp_sel), |
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| 106 | .byp_imm (byp_imm), |
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| 107 | .acc_imm (acc_imm), |
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| 108 | .acc_actc2 (acc_actc2), |
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| 109 | .acc_actc3 (acc_actc3), |
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| 110 | .acc_actc5 (acc_actc5), |
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| 111 | .acc_reg_enb (acc_reg_enb), |
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| 112 | .acc_reg_rst (acc_reg_rst), |
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| 113 | .acc_reg_shf (acc_reg_shf), |
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| 114 | .x2 (x2), |
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| 115 | .mul_data_out (mul_data_out), |
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| 116 | .rst_l (rst_l), |
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| 117 | .si (), |
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| 118 | .so (), |
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| 119 | .se (se), |
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| 120 | .rclk (clk)); |
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| 121 | |
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| 122 | endmodule // sparc_mul_top |
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