| 1 | // ========== Copyright Header Begin ========================================== |
|---|
| 2 | // |
|---|
| 3 | // OpenSPARC T1 Processor File: sparc_mul_top.v |
|---|
| 4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
|---|
| 5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
|---|
| 6 | // |
|---|
| 7 | // The above named program is free software; you can redistribute it and/or |
|---|
| 8 | // modify it under the terms of the GNU General Public |
|---|
| 9 | // License version 2 as published by the Free Software Foundation. |
|---|
| 10 | // |
|---|
| 11 | // The above named program is distributed in the hope that it will be |
|---|
| 12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
|---|
| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
|---|
| 14 | // General Public License for more details. |
|---|
| 15 | // |
|---|
| 16 | // You should have received a copy of the GNU General Public |
|---|
| 17 | // License along with this work; if not, write to the Free Software |
|---|
| 18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
|---|
| 19 | // |
|---|
| 20 | // ========== Copyright Header End ============================================ |
|---|
| 21 | module sparc_mul_top(/*AUTOARG*/ |
|---|
| 22 | // Outputs |
|---|
| 23 | mul_exu_ack, mul_spu_ack, mul_spu_shf_ack, mul_data_out, so, |
|---|
| 24 | // Inputs |
|---|
| 25 | rclk, grst_l, arst_l, exu_mul_input_vld, exu_mul_rs1_data, exu_mul_rs2_data, |
|---|
| 26 | spu_mul_req_vld, spu_mul_acc, spu_mul_areg_shf, spu_mul_areg_rst, |
|---|
| 27 | spu_mul_op1_data, spu_mul_op2_data, spu_mul_mulres_lshft, si, se |
|---|
| 28 | ); |
|---|
| 29 | |
|---|
| 30 | input rclk; |
|---|
| 31 | input grst_l; // system reset |
|---|
| 32 | input arst_l; // async reset |
|---|
| 33 | input si; // scan in |
|---|
| 34 | input se; // scan enablen |
|---|
| 35 | input exu_mul_input_vld; // EXU multipler op request |
|---|
| 36 | input [63:0] exu_mul_rs1_data; // EXU multipler Op1 |
|---|
| 37 | input [63:0] exu_mul_rs2_data; // EXU multipler Op2 |
|---|
| 38 | input spu_mul_req_vld; // SPU multipler op request |
|---|
| 39 | input spu_mul_acc; // MAC Op: ACCUM += op1 * op2 if spu_mul_acc=1 |
|---|
| 40 | // Bypass Op: Out = ACCUM * op1 if spu_mul_acc=0 |
|---|
| 41 | input spu_mul_areg_shf; // Shift >> 64 ACCUM register |
|---|
| 42 | input spu_mul_areg_rst; // Reset of ACCUM register (136-bit) |
|---|
| 43 | input [63:0] spu_mul_op1_data; // SPU multiplier Op1 |
|---|
| 44 | input [63:0] spu_mul_op2_data; // SPU multiplier Op2 |
|---|
| 45 | |
|---|
| 46 | input spu_mul_mulres_lshft; |
|---|
| 47 | |
|---|
| 48 | output so; // scan_out |
|---|
| 49 | output mul_exu_ack; // ack signal for EXU mul operation |
|---|
| 50 | output mul_spu_ack; // ack signal for SPU MAC and Bypass mul operation |
|---|
| 51 | output mul_spu_shf_ack; // acl signal for ACCUM >> 64 operation |
|---|
| 52 | output [63:0] mul_data_out; // Shared output data for both EXU and SPU |
|---|
| 53 | |
|---|
| 54 | wire acc_imm, acc_actc2, acc_actc3, acc_actc5, acc_reg_enb; |
|---|
| 55 | wire acc_reg_rst, acc_reg_shf; |
|---|
| 56 | wire byp_sel, byp_imm, spick, x2; |
|---|
| 57 | wire c0_act; |
|---|
| 58 | |
|---|
| 59 | wire rst_l; |
|---|
| 60 | wire clk; |
|---|
| 61 | |
|---|
| 62 | assign clk = rclk ; |
|---|
| 63 | |
|---|
| 64 | dffrl_async rstff ( |
|---|
| 65 | .din (grst_l), |
|---|
| 66 | .clk (clk), |
|---|
| 67 | .rst_l (arst_l), |
|---|
| 68 | .q (rst_l), |
|---|
| 69 | .se (se), |
|---|
| 70 | .si (), |
|---|
| 71 | .so ()); |
|---|
| 72 | |
|---|
| 73 | sparc_mul_cntl control ( |
|---|
| 74 | .ecl_mul_req_vld (exu_mul_input_vld), |
|---|
| 75 | .spu_mul_req_vld (spu_mul_req_vld), |
|---|
| 76 | .spu_mul_acc (spu_mul_acc), |
|---|
| 77 | .spu_mul_areg_shf (spu_mul_areg_shf), |
|---|
| 78 | .spu_mul_areg_rst (spu_mul_areg_rst), |
|---|
| 79 | .spu_mul_mulres_lshft (spu_mul_mulres_lshft), |
|---|
| 80 | .c0_act (c0_act), |
|---|
| 81 | .spick (spick), |
|---|
| 82 | .byp_sel (byp_sel), |
|---|
| 83 | .byp_imm (byp_imm), |
|---|
| 84 | .acc_imm (acc_imm), |
|---|
| 85 | .acc_actc2 (acc_actc2), |
|---|
| 86 | .acc_actc3 (acc_actc3), |
|---|
| 87 | .acc_actc5 (acc_actc5), |
|---|
| 88 | .acc_reg_enb (acc_reg_enb), |
|---|
| 89 | .acc_reg_rst (acc_reg_rst), |
|---|
| 90 | .acc_reg_shf (acc_reg_shf), |
|---|
| 91 | .x2 (x2), |
|---|
| 92 | .mul_ecl_ack (mul_exu_ack), |
|---|
| 93 | .mul_spu_ack (mul_spu_ack), |
|---|
| 94 | .mul_spu_shf_ack (mul_spu_shf_ack), |
|---|
| 95 | .rst_l (rst_l), |
|---|
| 96 | .rclk (clk)); |
|---|
| 97 | |
|---|
| 98 | sparc_mul_dp dpath ( |
|---|
| 99 | .ecl_mul_rs1_data (exu_mul_rs1_data), |
|---|
| 100 | .ecl_mul_rs2_data (exu_mul_rs2_data), |
|---|
| 101 | .spu_mul_op1_data (spu_mul_op1_data), |
|---|
| 102 | .spu_mul_op2_data (spu_mul_op2_data), |
|---|
| 103 | .valid (c0_act), |
|---|
| 104 | .spick (spick), |
|---|
| 105 | .byp_sel (byp_sel), |
|---|
| 106 | .byp_imm (byp_imm), |
|---|
| 107 | .acc_imm (acc_imm), |
|---|
| 108 | .acc_actc2 (acc_actc2), |
|---|
| 109 | .acc_actc3 (acc_actc3), |
|---|
| 110 | .acc_actc5 (acc_actc5), |
|---|
| 111 | .acc_reg_enb (acc_reg_enb), |
|---|
| 112 | .acc_reg_rst (acc_reg_rst), |
|---|
| 113 | .acc_reg_shf (acc_reg_shf), |
|---|
| 114 | .x2 (x2), |
|---|
| 115 | .mul_data_out (mul_data_out), |
|---|
| 116 | .rst_l (rst_l), |
|---|
| 117 | .si (), |
|---|
| 118 | .so (), |
|---|
| 119 | .se (se), |
|---|
| 120 | .rclk (clk)); |
|---|
| 121 | |
|---|
| 122 | endmodule // sparc_mul_top |
|---|
