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spu_ctl.v @ 6

Revision 6, 33.4 KB checked in by pntsvt00, 13 years ago (diff)
versione iniziale opensparc

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1	// ========== Copyright Header Begin ==========================================
2	//
3	// OpenSPARC T1 Processor File: spu_ctl.v
4	// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
5	// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
6	//
7	// The above named program is free software; you can redistribute it and/or
8	// modify it under the terms of the GNU General Public
9	// License version 2 as published by the Free Software Foundation.
10	//
11	// The above named program is distributed in the hope that it will be
12	// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
13	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14	// General Public License for more details.
15	//
16	// You should have received a copy of the GNU General Public
17	// License along with this work; if not, write to the Free Software
18	// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
19	//
20	// ========== Copyright Header End ============================================
21	////////////////////////////////////////////////////////////////////////
22	/*
23	// Description: Stream Processing Unit for Sparc Core
24	*/
25	////////////////////////////////////////////////////////////////////////
26	// Global header file includes
27	////////////////////////////////////////////////////////////////////////
28
29
30	module spu_ctl (
31	//Inputs
32	cpx_spu_data_cx,spu_wen_pckt_req,lsu_spu_ldst_ack,lsu_tlu_st_rs3_data_g,
33	spu_lsurpt1_rsrv_data_e, spu_madp_mpa_addr,
34	ifu_spu_trap_ack,mul_data_out,spu_mul_mulres_lshft,
35	//output
36	spu_mamul_oprnd2_bypass,
37	spu_mactl_ldop,
38	/AUTOARG/
39	// Outputs
40
41	spu_wen_ldst_pcx_vld,
42
43	spu_wen_pcx_wen,
44	spu_wen_pcx_7170_sel,
45
46	spu_ifu_corr_err_w2,
47	spu_ifu_unc_err_w,
48	spu_lsu_unc_error_w,
49
50	spu_ifu_mamem_err_w,
51	spu_ifu_int_w2,
52	spu_lsu_ldxa_illgl_va_w2,
53	cpuid,
54	ifu_spu_nceen,
55
56	spu_tlu_rsrv_illgl_m,
57	spu_mul_req_vld,
58	spu_mul_areg_shf, spu_mul_areg_rst, spu_mul_acc,
59	spu_mared_rdn_wen, spu_mared_data_sel_l,
60	spu_mared_cin_oprnd_sub_mod, spu_mamul_oprnd2_wen,
61	spu_mamul_oprnd1_mxsel_l,spu_mamul_oprnd1_wen, spu_maexp_shift_e,
62	spu_maexp_e_data_wen, spu_mactl_mpa_sel,
63	spu_mactl_memodd_wen, spu_mactl_memmxsel_l, spu_mactl_memeve_wen,
64	spu_mactl_mamem_ren, spu_mactl_mamem_wen,
65	spu_mactl_madp_parflop_wen, spu_mactl_force_perr,
66	spu_maaddr_mpa_wen, spu_maaddr_mpa_incr_val,
67	spu_maaddr_mpa_addrinc, spu_maaddr_memindx, spu_maaddr_mamem_eveodd_sel_l,
68	spu_lsu_stxa_ack_tid, spu_lsu_stxa_ack, spu_lsu_ldxa_tid_w2,
69	spu_lsu_ldxa_data_vld_w2, spu_ifu_ttype_w2, spu_ifu_ttype_vld_w2,
70	spu_ifu_ttype_tid_w,
71	so,
72
73	spu_mactl_mem_reset_l,
74	mux_drive_disable,
75	mem_bypass,
76	sehold,
77
78	spu_mactl_ldxa_data_w_sel_l,
79	spu_mactl_ldxa_data_w_select,
80	spu_mactl_mpa_wen,
81	spu_mactl_maaddr_wen,
82	spu_mactl_manp_wen,
83	spu_wen_maln_wen,
84	spu_mactl_mactl_reg,
85	spu_madp_maaddr_reg,
86
87	// Inputs
88
89
90	lsu_spu_stb_empty,
91
92	lsu_spu_strm_ack_cmplt,
93	lsu_spu_early_flush_g,
94	tlu_spu_flush_w,
95	ifu_spu_flush_w,
96	spu_madp_perr, spu_madp_m_lt_n, spu_madp_m_eq_n, spu_madp_e_eq_one,
97	spu_madp_cout_oprnd_sub_mod, si, se, grst_l, arst_l, mul_spu_shf_ack,
98	mul_spu_ack, lsu_spu_asi_state_e, ifu_tlu_thrid_e,
99	ifu_spu_inst_vld_w, ifu_lsu_st_inst_e, ifu_lsu_ld_inst_e,
100	ifu_lsu_alt_space_e, exu_lsu_ldst_va_e, rclk
101	) ;
102
103	input [3:0] lsu_spu_stb_empty;
104
105	input [134:128] cpx_spu_data_cx;
106	input lsu_spu_ldst_ack;
107	input ifu_spu_trap_ack;
108	input [13:0] lsu_tlu_st_rs3_data_g;
109	input [2:0] spu_lsurpt1_rsrv_data_e;
110	input [3:3] spu_madp_mpa_addr;
111	input [0:0] mul_data_out;
112	output spu_mul_mulres_lshft;
113	output spu_mamul_oprnd2_bypass;// From spu_mamul of spu_mamul.v
114	output spu_mactl_ldop; // From spu_mactl of spu_mactl.v
115
116	output spu_ifu_corr_err_w2;
117	output spu_ifu_unc_err_w;
118	output spu_lsu_unc_error_w;
119
120	output spu_ifu_mamem_err_w;
121	output spu_ifu_int_w2;
122	output spu_lsu_ldxa_illgl_va_w2;
123
124
125	output spu_mactl_mem_reset_l;
126
127	output spu_wen_pcx_7170_sel;
128	output spu_wen_pcx_wen;
129
130	output [122:104] spu_wen_pckt_req;
131	// ------------------------------------------------------------------
132	/AUTOINPUT/
133	// Beginning of automatic inputs (from unused autoinst inputs)
134
135
136	input rclk; // To spu_wen of spu_wen.v, ...
137	input [7:0] exu_lsu_ldst_va_e; // To spu_mactl of spu_mactl.v
138	input ifu_lsu_alt_space_e; // To spu_mactl of spu_mactl.v
139	input ifu_lsu_ld_inst_e; // To spu_mactl of spu_mactl.v
140	input ifu_lsu_st_inst_e; // To spu_mactl of spu_mactl.v
141	input ifu_spu_inst_vld_w; // To spu_mactl of spu_mactl.v
142	input [1:0] ifu_tlu_thrid_e; // To spu_mactl of spu_mactl.v
143	input [7:0] lsu_spu_asi_state_e; // To spu_mactl of spu_mactl.v
144	input mul_spu_ack; // To spu_mamul of spu_mamul.v, ...
145	input mul_spu_shf_ack; // To spu_mamul of spu_mamul.v, ...
146	input grst_l; // To spu_wen of spu_wen.v, ...
147	input arst_l; // To spu_wen of spu_wen.v, ...
148	input se; // To spu_shactl of spu_shactl.v, ...
149	input si; // To spu_shactl of spu_shactl.v, ...
150	input spu_madp_cout_oprnd_sub_mod;// To spu_mared of spu_mared.v
151	input spu_madp_e_eq_one; // To spu_maexp of spu_maexp.v
152	input spu_madp_m_eq_n; // To spu_mared of spu_mared.v
153	input spu_madp_m_lt_n; // To spu_mared of spu_mared.v
154	input spu_madp_perr; // To spu_mactl of spu_mactl.v
155	input lsu_spu_early_flush_g;
156	input tlu_spu_flush_w;
157	input ifu_spu_flush_w;
158	input [2:0] cpuid;
159	input [3:0] ifu_spu_nceen;
160
161
162	input [1:0] lsu_spu_strm_ack_cmplt;
163
164	input mux_drive_disable;
165	input mem_bypass;
166	input sehold;
167
168
169	// End of automatics
170
171	// ------------------------------------------------------------------
172	/AUTOOUTPUT/
173	// Beginning of automatic outputs (from unused autoinst outputs)
174	output so; // From spu_shactl of spu_shactl.v, ...
175	output [1:0] spu_ifu_ttype_tid_w; // From spu_mactl of spu_mactl.v
176	output spu_ifu_ttype_vld_w2; // From spu_mactl of spu_mactl.v
177	output spu_ifu_ttype_w2; // From spu_mactl of spu_mactl.v
178	output spu_lsu_ldxa_data_vld_w2;// From spu_mactl of spu_mactl.v
179	output [1:0] spu_lsu_ldxa_tid_w2; // From spu_mactl of spu_mactl.v
180	output spu_lsu_stxa_ack; // From spu_mactl of spu_mactl.v
181	output [1:0] spu_lsu_stxa_ack_tid; // From spu_mactl of spu_mactl.v
182	output [7:1] spu_maaddr_memindx; // From spu_maaddr of spu_maaddr.v
183	output [3:0] spu_maaddr_mamem_eveodd_sel_l; // From spu_maaddr of spu_maaddr.v
184	output spu_maaddr_mpa_addrinc; // From spu_maaddr of spu_maaddr.v
185	output [4:0] spu_maaddr_mpa_incr_val;// From spu_maaddr of spu_maaddr.v
186	output spu_maaddr_mpa_wen; // From spu_maaddr of spu_maaddr.v
187	output spu_mactl_force_perr; // From spu_mactl of spu_mactl.v
188	output spu_mactl_madp_parflop_wen;// From spu_mactl of spu_mactl.v
189	output spu_mactl_mamem_ren; // From spu_mactl of spu_mactl.v
190	output spu_mactl_mamem_wen; // From spu_mactl of spu_mactl.v
191	output spu_mactl_memeve_wen; // From spu_mactl of spu_mactl.v
192	output [2:0] spu_mactl_memmxsel_l; // From spu_mactl of spu_mactl.v
193	output spu_mactl_memodd_wen; // From spu_mactl of spu_mactl.v
194	output spu_mactl_mpa_sel; // From spu_mactl of spu_mactl.v
195	output spu_maexp_e_data_wen; // From spu_maexp of spu_maexp.v
196	output spu_maexp_shift_e; // From spu_maexp of spu_maexp.v
197	output [2:0] spu_mamul_oprnd1_mxsel_l; // From spu_mamul of spu_mamul.v
198	output spu_mamul_oprnd1_wen; // From spu_mamul of spu_mamul.v
199	output spu_mamul_oprnd2_wen; // From spu_mamul of spu_mamul.v
200	output spu_mared_cin_oprnd_sub_mod;// From spu_mared of spu_mared.v
201	output [3:0] spu_mared_data_sel_l; // From spu_mared of spu_mared.v
202	output spu_mared_rdn_wen; // From spu_mared of spu_mared.v
203	output spu_mul_acc; // From spu_mamul of spu_mamul.v
204	output spu_mul_areg_rst; // From spu_mamul of spu_mamul.v
205	output spu_mul_areg_shf; // From spu_mamul of spu_mamul.v
206	output spu_mul_req_vld; // From spu_mamul of spu_mamul.v
207	output spu_tlu_rsrv_illgl_m; // From spu_mactl of spu_mactl.v
208
209	output spu_wen_ldst_pcx_vld;
210
211	output [3:0] spu_mactl_ldxa_data_w_sel_l;
212	output spu_mactl_ldxa_data_w_select;
213	output spu_mactl_mpa_wen;
214	output spu_mactl_maaddr_wen;
215	output spu_mactl_manp_wen;
216	output spu_wen_maln_wen;
217	output [13:0] spu_mactl_mactl_reg;
218	input [47:0] spu_madp_maaddr_reg;
219
220	// End of automatics
221	// ------------------------------------------------------------------
222
223	/AUTOWIRE/
224	// Beginning of automatic wires (for undeclared instantiated-module outputs)
225	wire [1:0] spu_maaeqb_oprnd1_mxsel; // From spu_maaeqb of spu_maaeqb.v
226	wire [5:0] spu_maaddr_len_cntr;
227	wire [5:0] spu_mactl_mactl_len; // From spu_mactl of spu_mactl.v
228
229	// End of automatics
230
231	// ------------------------------------------------------------------
232
233
234	// ------------------------------------------------------------------
235
236
237	/****************************************************************************/
238
239	// -------------------------------------------------------------------------
240	spu_wen spu_wen (//in
241	.spu_mald_done (spu_mald_ld_done),
242
243	//.lsu_spu_vload_rtntyp (cpx_spu_data_cx[138:135]), //cpx_spc_data_cx[143:140]
244	.lsu_spu_vload_rtntyp (cpx_spu_data_cx[133:130]), //cpx_spc_data_cx[143:140]
245	//.lsu_spu_vload_asop (cpx_spu_data_cx[129]), //cpx_spc_data_cx[130]
246	//.lsu_spu_vload_vld (cpx_spu_data_cx[139]), //cpx_spc_data_cx[144]
247	.lsu_spu_vload_vld (cpx_spu_data_cx[134]), //cpx_spc_data_cx[144]
248	//.lsu_spu_vload_data_tid (cpx_spu_data_cx[131:130]), //cpx_spc_data_cx[135:134]
249	//.lsu_spu_vload_bid (cpx_spu_data_cx[128]), //cpx_spc_data_cx[129]
250	//.l2_miss (cpx_spu_data_cx[134]), //cpx_spc_data_cx[139]
251	//.l2_err (cpx_spu_data_cx[133:132]), //cpx_spc_data_cx[138:137]
252	.l2_err (cpx_spu_data_cx[129:128]), //cpx_spc_data_cx[138:137]
253
254	.lsu_spu_st_ack_tid (spu_wen_pckt_req[113:112]),
255	.lsu_spu_st_asop (spu_wen_pckt_req[108]),
256	.lsu_spu_st_ackvld (lsu_spu_ldst_ack),
257	.lsu_spu_ld_ack_tid (spu_wen_pckt_req[113:112]),
258	.lsu_spu_ld_asop (spu_wen_pckt_req[106]),
259	.lsu_spu_ld_ackvld (lsu_spu_ldst_ack),
260
261	.cpuid (cpuid[2:0]),
262
263	/AUTOINST/
264	// Outputs
265	.spu_wen_pckt_req (spu_wen_pckt_req[122:104]),
266
267	.spu_wen_mast_ack (spu_wen_mast_ack),
268	.spu_wen_maln_wen (spu_wen_maln_wen),
269	.spu_wen_mald_ack (spu_wen_mald_ack),
270	.spu_wen_vld_maln (spu_wen_vld_maln),
271
272	.spu_wen_ldst_pcx_vld (spu_wen_ldst_pcx_vld),
273	.spu_mactl_streq (spu_mactl_streq),
274	.spu_mald_ldreq (spu_mald_ldreq),
275
276	.spu_wen_allma_stacks_ok (spu_wen_allma_stacks_ok),
277
278
279	.spu_wen_ma_unc_err_pulse (spu_wen_ma_unc_err_pulse),
280	.spu_wen_ma_unc_err (spu_wen_ma_unc_err),
281	.spu_wen_ma_cor_err (spu_wen_ma_cor_err),
282
283	// Inputs
284	.spu_mactl_uncerr_rst (spu_mactl_uncerr_rst),
285
286
287	.lsu_spu_strm_ack_cmplt (lsu_spu_strm_ack_cmplt[1:0]),
288	.reset (spu_mactl_ctl_reset),
289	.rclk (rclk),
290	.se (se),
291	.spu_mald_rstln (spu_mald_rstln));
292
293
294	// -------------------------------------------------------------------------
295
296	// -------------------------------------------------------------------------
297
298	// -------------------------------------------------------------------------
299	// -------------------------------------------------------------------------
300	// -------------------------------------------------------------------------
301	// ------------------------ MA STUFF ---------------------------------------
302	// -------------------------------------------------------------------------
303	// -------------------------------------------------------------------------
304	// -------------------------------------------------------------------------
305	spu_mast spu_mast (//in
306	.mactl_stop (spu_mactl_stop),
307	.streq_ack (spu_wen_mast_ack),
308	.len_neqz (spu_maaddr_len_neqz),
309
310	/AUTOINST/
311	// Outputs
312	.spu_mast_maaddr_addrinc(spu_mast_maaddr_addrinc),
313	.spu_mast_memren (spu_mast_memren),
314	.spu_mast_stbuf_wen (spu_mast_stbuf_wen),
315	.spu_mast_mpa_addrinc(spu_mast_mpa_addrinc),
316	.spu_mast_streq (spu_mast_streq),
317	.spu_mast_done_set (spu_mast_done_set),
318
319	.spu_wen_allma_stacks_ok (spu_wen_allma_stacks_ok),
320	// Inputs
321
322	.spu_mactl_stxa_force_abort (spu_mactl_stxa_force_abort),
323	.spu_mactl_perr_set (spu_mactl_perr_set),
324
325	.reset (spu_mactl_ctl_reset),
326	.rclk (rclk),
327	.se (se),
328	.spu_mactl_iss_pulse_dly(spu_mactl_iss_pulse_dly));
329	// -------------------------------------------------------------------------
330	spu_mald spu_mald (//in
331	.ld_inprog (spu_mactl_ldop),
332	.ldreq_ack (spu_wen_mald_ack),
333	.ln_received (spu_wen_vld_maln),
334	.len_neqz (spu_maaddr_len_neqz),
335	.mactl_ldop (spu_mactl_ldop),
336	//out
337	.spu_mald_done (spu_mald_ld_done),
338	/AUTOINST/
339	// Outputs
340	.spu_mald_rstln (spu_mald_rstln),
341	.spu_mald_maaddr_addrinc(spu_mald_maaddr_addrinc),
342	.spu_mald_memwen (spu_mald_memwen),
343	.spu_mald_mpa_addrinc(spu_mald_mpa_addrinc),
344	.spu_mald_ldreq (spu_mald_ldreq),
345	.spu_mald_force_mpa_add16(spu_mald_force_mpa_add16),
346	.spu_mald_done_set (spu_mald_done_set),
347	// Inputs
348	.spu_mactl_stxa_force_abort (spu_mactl_stxa_force_abort),
349	.spu_wen_ma_unc_err_pulse (spu_wen_ma_unc_err_pulse),
350
351	.reset (spu_mactl_ctl_reset),
352	.rclk (rclk),
353	.se (se),
354	.spu_maaddr_mpa1maddr0(spu_maaddr_mpa1maddr0),
355	.spu_mactl_iss_pulse_dly(spu_mactl_iss_pulse_dly));
356
357	// -------------------------------------------------------------------------
358	spu_mactl spu_mactl (//in
359	.spu_maaddr_maaddr_0 (spu_maaddr_wrindx_0),
360	.spu_maaddr_mpa_3 (spu_madp_mpa_addr[3]),
361	.ma_ctl_reg_data (lsu_tlu_st_rs3_data_g[13:0]),
362
363	.ifu_spu_trap_ack (ifu_spu_trap_ack),
364	.spu_mactl_rsrv_data_e (spu_lsurpt1_rsrv_data_e[2:0]),
365
366	.spu_ifu_corr_err_w2 (spu_ifu_corr_err_w2),
367	.spu_ifu_unc_err_w (spu_ifu_unc_err_w),
368	.spu_lsu_unc_error_w (spu_lsu_unc_error_w),
369
370	.spu_ifu_mamem_err_w (spu_ifu_mamem_err_w),
371	.spu_ifu_int_w2 (spu_ifu_int_w2),
372	.spu_lsu_ldxa_illgl_va_w2 (spu_lsu_ldxa_illgl_va_w2),
373
374	.spu_mactl_uncerr_rst (spu_mactl_uncerr_rst),
375
376	.spu_mactl_pcx_wen (spu_wen_pcx_wen),
377	.spu_mactl_pcx_7170_sel (spu_wen_pcx_7170_sel),
378	.spu_mactl_perr_set (spu_mactl_perr_set),
379	/AUTOINST/
380	// Outputs
381	//.so (so),
382
383	.spu_mactl_iss_pulse_pre(spu_mactl_iss_pulse_pre),
384	.spu_mactl_iss_pulse(spu_mactl_iss_pulse),
385	.spu_mactl_mpa_wen (spu_mactl_mpa_wen),
386	.spu_mactl_maaddr_wen(spu_mactl_maaddr_wen),
387	.spu_mactl_manp_wen(spu_mactl_manp_wen),
388	.spu_mactl_ldop (spu_mactl_ldop),
389	.spu_mactl_stop (spu_mactl_stop),
390	.spu_mactl_mulop (spu_mactl_mulop),
391	.spu_mactl_redop (spu_mactl_redop),
392	.spu_mactl_expop (spu_mactl_expop),
393	.spu_mactl_memmxsel_l(spu_mactl_memmxsel_l[2:0]),
394	.spu_mactl_memeve_wen(spu_mactl_memeve_wen),
395	.spu_mactl_memodd_wen(spu_mactl_memodd_wen),
396	.spu_mactl_mamem_ren(spu_mactl_mamem_ren),
397	.spu_mactl_mamem_wen(spu_mactl_mamem_wen),
398	.spu_mactl_iss_pulse_dly(spu_mactl_iss_pulse_dly),
399	.spu_mactl_ldxa_data_w_sel_l(spu_mactl_ldxa_data_w_sel_l[3:0]),
400	.spu_mactl_ldxa_data_w_select(spu_mactl_ldxa_data_w_select),
401	.spu_mactl_mpa_sel (spu_mactl_mpa_sel),
402	.spu_mactl_madp_parflop_wen(spu_mactl_madp_parflop_wen),
403	.spu_lsu_ldxa_data_vld_w2(spu_lsu_ldxa_data_vld_w2),
404	.spu_lsu_ldxa_tid_w2(spu_lsu_ldxa_tid_w2[1:0]),
405	.spu_lsu_stxa_ack (spu_lsu_stxa_ack),
406	.spu_lsu_stxa_ack_tid(spu_lsu_stxa_ack_tid[1:0]),
407	.spu_mactl_ldxa_mactl_reg(spu_mactl_mactl_reg[13:0]),
408	.spu_mactl_mactl_len(spu_mactl_mactl_len[5:0]),
409	.spu_mactl_force_perr(spu_mactl_force_perr),
410	.spu_ifu_ttype_w2 (spu_ifu_ttype_w2),
411	.spu_ifu_ttype_vld_w2(spu_ifu_ttype_vld_w2),
412	.spu_ifu_ttype_tid_w(spu_ifu_ttype_tid_w[1:0]),
413	.spu_tlu_rsrv_illgl_m(spu_tlu_rsrv_illgl_m),
414
415	.spu_mactl_streq (spu_mactl_streq),
416
417	.spu_mactl_ctl_reset (spu_mactl_ctl_reset),
418	.spu_mactl_mem_reset_l (spu_mactl_mem_reset_l),
419
420	.spu_mactl_ma_kill_op (spu_mactl_ma_kill_op),
421	// Inputs
422	.mux_drive_disable (mux_drive_disable),
423	.spu_mactl_stxa_force_abort (spu_mactl_stxa_force_abort),
424	.lsu_spu_ldst_ack (lsu_spu_ldst_ack),
425
426	.spu_wen_ma_unc_err (spu_wen_ma_unc_err),
427	.spu_wen_ma_cor_err (spu_wen_ma_cor_err),
428
429
430
431	.spu_maaddr_len_cntr (spu_maaddr_len_cntr[5:0]),
432	.ifu_spu_nceen (ifu_spu_nceen[3:0]),
433
434	.spu_mast_streq (spu_mast_streq),
435
436	.lsu_spu_stb_empty (lsu_spu_stb_empty[3:0]),
437
438	.grst_l (grst_l),
439	.arst_l (arst_l),
440	.rclk (rclk),
441	.se (se),
442	//.si (si),
443	//.se (se),
444
445
446	.spu_mald_memwen (spu_mald_memwen),
447	.spu_mamul_memwen (spu_mamul_memwen),
448	.spu_mamul_memren (spu_mamul_memren),
449	.spu_maaeqb_memwen (spu_maaeqb_memwen),
450	.spu_maaeqb_memren (spu_maaeqb_memren),
451	.spu_mared_memren (spu_mared_memren),
452	.spu_mared_memwen (spu_mared_memwen),
453	.spu_mast_memren (spu_mast_memren),
454	.lsu_spu_early_flush_g(lsu_spu_early_flush_g),
455	.tlu_spu_flush_w(tlu_spu_flush_w),
456	.ifu_spu_flush_w(ifu_spu_flush_w),
457	.ifu_spu_inst_vld_w(ifu_spu_inst_vld_w),
458	.lsu_spu_asi_state_e(lsu_spu_asi_state_e[7:0]),
459	.ifu_lsu_ld_inst_e (ifu_lsu_ld_inst_e),
460	.ifu_lsu_st_inst_e (ifu_lsu_st_inst_e),
461	.ifu_lsu_alt_space_e(ifu_lsu_alt_space_e),
462	.ifu_tlu_thrid_e (ifu_tlu_thrid_e[1:0]),
463	.exu_lsu_ldst_va_e (exu_lsu_ldst_va_e[7:0]),
464	.spu_mald_done_set (spu_mald_done_set),
465	.spu_mast_done_set (spu_mast_done_set),
466	.spu_mared_done_set(spu_mared_done_set),
467	.spu_maexp_done_set(spu_maexp_done_set),
468	.spu_maexp_memren (spu_maexp_memren),
469	.spu_maaddr_nooddwr_on_leneq1(spu_maaddr_nooddwr_on_leneq1),
470	.spu_mared_not_idle(spu_mared_not_idle),
471	.spu_mamul_oprnd2_bypass(spu_mamul_oprnd2_bypass),
472	.spu_madp_perr(spu_madp_perr));
473
474	// -------------------------------------------------------------------------
475	spu_maaddr spu_maaddr (//in
476	//.lsu_spu_stxa_data (lsu_tlu_st_rs3_data_g[5:0]),
477	.spu_madp_mactl_reg (spu_mactl_mactl_len[5:0]),
478	.spu_madp_mpa_addr_3 (spu_madp_mpa_addr[3]),
479
480
481	/AUTOINST/
482	// Outputs
483	.spu_maaddr_len_neqz(spu_maaddr_len_neqz),
484	.spu_maaddr_mpa1maddr0(spu_maaddr_mpa1maddr0),
485	.spu_maaddr_memindx(spu_maaddr_memindx[7:1]),
486	.spu_maaddr_mamem_eveodd_sel_l(spu_maaddr_mamem_eveodd_sel_l[3:0]),
487	.spu_maaddr_iequtwolenplus2(spu_maaddr_iequtwolenplus2),
488	.spu_maaddr_iequtwolenplus1(spu_maaddr_iequtwolenplus1),
489	.spu_maaddr_jequiminus1(spu_maaddr_jequiminus1),
490	.spu_maaddr_jequlen(spu_maaddr_jequlen),
491	.spu_maaddr_halfpnt_set(spu_maaddr_halfpnt_set),
492	.spu_maaddr_len_eqmax(spu_maaddr_len_eqmax),
493	.spu_maaddr_esmod64(spu_maaddr_esmod64),
494	.spu_maaddr_esmax(spu_maaddr_esmax),
495	.spu_maaddr_nooddwr_on_leneq1(spu_maaddr_nooddwr_on_leneq1),
496	.spu_maaddr_mpa_addrinc(spu_maaddr_mpa_addrinc),
497	.spu_maaddr_mpa_wen(spu_maaddr_mpa_wen),
498	.spu_maaddr_mpa_incr_val(spu_maaddr_mpa_incr_val[4:0]),
499	.spu_maaddr_jequiminus1rshft(spu_maaddr_jequiminus1rshft),
500	.spu_maaddr_iequtwolen(spu_maaddr_iequtwolen),
501	.spu_maaddr_ieven(spu_maaddr_ieven),
502	.spu_maaddr_ieq0 (spu_maaddr_ieq0),
503	.spu_maaddr_aequb(spu_maaddr_aequb),
504	.spu_maaddr_jptr_eqz_mared (spu_maaddr_jptr_eqz_mared),
505	// Inputs
506
507	.spu_mamul_rst (spu_mamul_rst),
508	.mem_bypass(mem_bypass),
509	.sehold(sehold),
510
511	.spu_mamul_jjptr_sel(spu_mamul_jjptr_sel),
512
513	.spu_maaddr_len_cntr(spu_maaddr_len_cntr[5:0]),
514
515	.spu_maaddr_wrindx_0 (spu_maaddr_wrindx_0),
516
517	.reset (spu_mactl_ctl_reset),
518	.rclk (rclk),
519	.se (se),
520	.spu_mald_force_mpa_add16(spu_mald_force_mpa_add16),
521	.spu_mactl_ldop (spu_mactl_ldop),
522	.spu_madp_maaddr_reg_in(spu_madp_maaddr_reg[47:0]),
523	.spu_mald_maaddr_addrinc(spu_mald_maaddr_addrinc),
524	.spu_mald_mpa_addrinc(spu_mald_mpa_addrinc),
525	.spu_mast_maaddr_addrinc(spu_mast_maaddr_addrinc),
526	.spu_mast_mpa_addrinc(spu_mast_mpa_addrinc),
527	.spu_mamul_memwen(spu_mamul_memwen),
528	.spu_mamul_rst_iptr(spu_mamul_rst_iptr),
529	.spu_mamul_rst_jptr(spu_mamul_rst_jptr),
530	.spu_mamul_incr_iptr(spu_mamul_incr_iptr),
531	.spu_mamul_incr_jptr(spu_mamul_incr_jptr),
532	.spu_mamul_a_rd_oprnd_sel(spu_mamul_a_rd_oprnd_sel),
533	.spu_mamul_ax_rd_oprnd_sel(spu_mamul_ax_rd_oprnd_sel),
534	.spu_mamul_b_rd_oprnd_sel(spu_mamul_b_rd_oprnd_sel),
535	.spu_mamul_ba_rd_oprnd_sel(spu_mamul_ba_rd_oprnd_sel),
536	.spu_mamul_m_rd_oprnd_sel(spu_mamul_m_rd_oprnd_sel),
537	.spu_mamul_n_rd_oprnd_sel(spu_mamul_n_rd_oprnd_sel),
538	.spu_mamul_m_wr_oprnd_sel(spu_mamul_m_wr_oprnd_sel),
539	.spu_mared_me_rd_oprnd_sel(spu_mared_me_rd_oprnd_sel),
540	.spu_mared_xe_wr_oprnd_sel(spu_mared_xe_wr_oprnd_sel),
541	.spu_mamul_me_rd_oprnd_sel(spu_mamul_me_rd_oprnd_sel),
542	.spu_mamul_me_wr_oprnd_sel(spu_mamul_me_wr_oprnd_sel),
543	.spu_mamul_i_ptr_sel(spu_mamul_i_ptr_sel),
544	.spu_mamul_iminus1_ptr_sel(spu_mamul_iminus1_ptr_sel),
545	.spu_mamul_j_ptr_sel(spu_mamul_j_ptr_sel),
546	.spu_mamul_iminusj_ptr_sel(spu_mamul_iminusj_ptr_sel),
547	.spu_mamul_iminuslenminus1_sel(spu_mamul_iminuslenminus1_sel),
548	.spu_mamul_jjptr_wen(spu_mamul_jjptr_wen),
549	.spu_mactl_iss_pulse(spu_mactl_iss_pulse),
550	.spu_mactl_iss_pulse_pre(spu_mactl_iss_pulse_pre),
551	.spu_mared_m_rd_oprnd_sel(spu_mared_m_rd_oprnd_sel),
552	.spu_mared_nm_rd_oprnd_sel(spu_mared_nm_rd_oprnd_sel),
553	.spu_mared_x_wr_oprnd_sel(spu_mared_x_wr_oprnd_sel),
554	.spu_mared_a_rd_oprnd_sel(spu_mared_a_rd_oprnd_sel),
555	.spu_mared_nr_rd_oprnd_sel(spu_mared_nr_rd_oprnd_sel),
556	.spu_mared_r_wr_oprnd_sel(spu_mared_r_wr_oprnd_sel),
557	.spu_mared_memwen(spu_mared_memwen),
558	.spu_mared_j_ptr_sel(spu_mared_j_ptr_sel),
559	.spu_mared_update_jptr(spu_mared_update_jptr),
560	.spu_mared_rst_jptr(spu_mared_rst_jptr),
561	.spu_mared_maxlen_wen(spu_mared_maxlen_wen),
562	.spu_mared_cin_set_4sub(spu_mared_cin_set_4sub),
563	.spu_mast_memren (spu_mast_memren),
564	.spu_mared_start_wen(spu_mared_start_wen),
565	.spu_mared_start_sel(spu_mared_start_sel),
566	.spu_maexp_incr_es_ptr(spu_maexp_incr_es_ptr),
567	.spu_maexp_e_rd_oprnd_sel(spu_maexp_e_rd_oprnd_sel),
568	.spu_maexp_es_max_init(spu_maexp_es_max_init),
569	.spu_maexp_es_e_ptr_rst(spu_maexp_es_e_ptr_rst),
570	.spu_maaeqb_memwen(spu_maaeqb_memwen),
571	.spu_maaeqb_irshft_sel(spu_maaeqb_irshft_sel),
572	.spu_mared_update_redwr_jptr(spu_mared_update_redwr_jptr),
573	.spu_mared_jjptr_wen(spu_mared_jjptr_wen));
574
575	// -------------------------------------------------------------------------
576	//spu_mamem spu_mamem (/AUTOINST/);
577
578	// -------------------------------------------------------------------------
579	//spu_madp spu_madp (/AUTOINST/);
580
581	// -------------------------------------------------------------------------
582
583	spu_mamul spu_mamul (//in
584
585	/AUTOINST/
586	// Outputs
587	//.so (so),
588	.spu_mamul_memwen (spu_mamul_memwen),
589	.spu_mamul_memren (spu_mamul_memren),
590	.spu_mamul_rst_iptr(spu_mamul_rst_iptr),
591	.spu_mamul_rst_jptr(spu_mamul_rst_jptr),
592	.spu_mamul_incr_iptr(spu_mamul_incr_iptr),
593	.spu_mamul_incr_jptr(spu_mamul_incr_jptr),
594	.spu_mamul_a_rd_oprnd_sel(spu_mamul_a_rd_oprnd_sel),
595	.spu_mamul_ax_rd_oprnd_sel(spu_mamul_ax_rd_oprnd_sel),
596	.spu_mamul_b_rd_oprnd_sel(spu_mamul_b_rd_oprnd_sel),
597	.spu_mamul_ba_rd_oprnd_sel(spu_mamul_ba_rd_oprnd_sel),
598	.spu_mamul_m_rd_oprnd_sel(spu_mamul_m_rd_oprnd_sel),
599	.spu_mamul_me_rd_oprnd_sel(spu_mamul_me_rd_oprnd_sel),
600	.spu_mamul_n_rd_oprnd_sel(spu_mamul_n_rd_oprnd_sel),
601	.spu_mamul_m_wr_oprnd_sel(spu_mamul_m_wr_oprnd_sel),
602	.spu_mamul_me_wr_oprnd_sel(spu_mamul_me_wr_oprnd_sel),
603	.spu_mamul_i_ptr_sel(spu_mamul_i_ptr_sel),
604	.spu_mamul_iminus1_ptr_sel(spu_mamul_iminus1_ptr_sel),
605	.spu_mamul_j_ptr_sel(spu_mamul_j_ptr_sel),
606	.spu_mamul_iminusj_ptr_sel(spu_mamul_iminusj_ptr_sel),
607	.spu_mamul_iminuslenminus1_sel(spu_mamul_iminuslenminus1_sel),
608	.spu_mamul_jjptr_wen(spu_mamul_jjptr_wen),
609	.spu_mamul_oprnd2_wen(spu_mamul_oprnd2_wen),
610	.spu_mamul_oprnd2_bypass(spu_mamul_oprnd2_bypass),
611	.spu_mamul_oprnd1_mxsel_l(spu_mamul_oprnd1_mxsel_l[2:0]),
612	.spu_mamul_oprnd1_wen (spu_mamul_oprnd1_wen),
613	.spu_mul_req_vld (spu_mul_req_vld),
614	.spu_mul_areg_shf (spu_mul_areg_shf),
615	.spu_mul_acc (spu_mul_acc),
616	.spu_mul_areg_rst (spu_mul_areg_rst),
617	.spu_mamul_rst (spu_mamul_rst),
618	.spu_mamul_mul_done(spu_mamul_mul_done),
619
620	.spu_mamul_jjptr_sel(spu_mamul_jjptr_sel),
621	// Inputs
622
623	.spu_mactl_stxa_force_abort (spu_mactl_stxa_force_abort),
624	.spu_mactl_kill_op (spu_mactl_ma_kill_op),
625
626	.spu_maaeqb_jjptr_sel(spu_maaeqb_jjptr_sel),
627
628	.reset (spu_mactl_ctl_reset),
629	.rclk (rclk),
630	.se (se),
631	//.si (si),
632	//.se (se),
633	.spu_maaddr_iequtwolenplus2(spu_maaddr_iequtwolenplus2),
634	.spu_maaddr_iequtwolenplus1(spu_maaddr_iequtwolenplus1),
635	.spu_maaddr_jequiminus1(spu_maaddr_jequiminus1),
636	.spu_maaddr_jequlen(spu_maaddr_jequlen),
637	.spu_maaddr_halfpnt_set(spu_maaddr_halfpnt_set),
638	.mul_spu_ack (mul_spu_ack),
639	.mul_spu_shf_ack (mul_spu_shf_ack),
640	.spu_mactl_mulop (spu_mactl_mulop),
641	.spu_mactl_iss_pulse_dly(spu_mactl_iss_pulse_dly),
642	.spu_mared_oprnd2_wen(spu_mared_oprnd2_wen),
643	.spu_maexp_start_mulred_anoteqb(spu_maexp_start_mulred_anoteqb),
644	.spu_mactl_expop (spu_mactl_expop),
645	.spu_maaddr_aequb (spu_maaddr_aequb),
646	.spu_maaeqb_rst_iptr(spu_maaeqb_rst_iptr),
647	.spu_maaeqb_rst_jptr(spu_maaeqb_rst_jptr),
648	.spu_maaeqb_incr_iptr(spu_maaeqb_incr_iptr),
649	.spu_maaeqb_incr_jptr(spu_maaeqb_incr_jptr),
650	.spu_maaeqb_a_rd_oprnd_sel(spu_maaeqb_a_rd_oprnd_sel),
651	.spu_maaeqb_ax_rd_oprnd_sel(spu_maaeqb_ax_rd_oprnd_sel),
652	.spu_maaeqb_m_rd_oprnd_sel(spu_maaeqb_m_rd_oprnd_sel),
653	.spu_maaeqb_me_rd_oprnd_sel(spu_maaeqb_me_rd_oprnd_sel),
654	.spu_maaeqb_n_rd_oprnd_sel(spu_maaeqb_n_rd_oprnd_sel),
655	.spu_maaeqb_m_wr_oprnd_sel(spu_maaeqb_m_wr_oprnd_sel),
656	.spu_maaeqb_me_wr_oprnd_sel(spu_maaeqb_me_wr_oprnd_sel),
657	.spu_maaeqb_iminus1_ptr_sel(spu_maaeqb_iminus1_ptr_sel),
658	.spu_maaeqb_j_ptr_sel(spu_maaeqb_j_ptr_sel),
659	.spu_maaeqb_iminusj_ptr_sel(spu_maaeqb_iminusj_ptr_sel),
660	.spu_maaeqb_iminuslenminus1_sel(spu_maaeqb_iminuslenminus1_sel),
661	.spu_maaeqb_jjptr_wen(spu_maaeqb_jjptr_wen),
662	.spu_maaeqb_oprnd2_wen(spu_maaeqb_oprnd2_wen),
663	.spu_maaeqb_oprnd2_bypass(spu_maaeqb_oprnd2_bypass),
664	.spu_maaeqb_oprnd1_mxsel(spu_maaeqb_oprnd1_mxsel[1:0]),
665	.spu_maaeqb_oprnd1_wen(spu_maaeqb_oprnd1_wen),
666	.spu_maaeqb_mul_req_vld(spu_maaeqb_mul_req_vld),
667	.spu_maaeqb_mul_areg_shf(spu_maaeqb_mul_areg_shf),
668	.spu_maaeqb_mul_acc(spu_maaeqb_mul_acc),
669	.spu_maaeqb_mul_areg_rst(spu_maaeqb_mul_areg_rst),
670	.spu_maaeqb_mul_done(spu_maaeqb_mul_done));
671
672	// -------------------------------------------------------------------------
673
674	spu_mared spu_mared (//in
675	.mul_data_out_0 (mul_data_out[0]),
676
677	/AUTOINST/
678	// Outputs
679	.spu_mared_data_sel_l(spu_mared_data_sel_l[3:0]),
680	.spu_mared_j_ptr_sel(spu_mared_j_ptr_sel),
681	.spu_mared_nm_rd_oprnd_sel(spu_mared_nm_rd_oprnd_sel),
682	.spu_mared_m_rd_oprnd_sel(spu_mared_m_rd_oprnd_sel),
683	.spu_mared_me_rd_oprnd_sel(spu_mared_me_rd_oprnd_sel),
684	.spu_mared_x_wr_oprnd_sel(spu_mared_x_wr_oprnd_sel),
685	.spu_mared_xe_wr_oprnd_sel(spu_mared_xe_wr_oprnd_sel),
686	.spu_mared_nr_rd_oprnd_sel(spu_mared_nr_rd_oprnd_sel),
687	.spu_mared_a_rd_oprnd_sel(spu_mared_a_rd_oprnd_sel),
688	.spu_mared_r_wr_oprnd_sel(spu_mared_r_wr_oprnd_sel),
689	.spu_mared_update_jptr(spu_mared_update_jptr),
690	.spu_mared_rst_jptr(spu_mared_rst_jptr),
691	.spu_mared_maxlen_wen(spu_mared_maxlen_wen),
692	.spu_mared_rdn_wen (spu_mared_rdn_wen),
693	.spu_mared_oprnd2_wen(spu_mared_oprnd2_wen),
694	.spu_mared_memren (spu_mared_memren),
695	.spu_mared_memwen (spu_mared_memwen),
696	.spu_mared_cin_set_4sub(spu_mared_cin_set_4sub),
697	.spu_mared_cin_oprnd_sub_mod(spu_mared_cin_oprnd_sub_mod),
698	.spu_mared_done_set(spu_mared_done_set),
699	.spu_mared_start_wen(spu_mared_start_wen),
700	.spu_mared_start_sel(spu_mared_start_sel),
701	.spu_mared_red_done(spu_mared_red_done),
702	.spu_mared_update_redwr_jptr(spu_mared_update_redwr_jptr),
703	.spu_mared_jjptr_wen(spu_mared_jjptr_wen),
704	.spu_mared_not_idle(spu_mared_not_idle),
705	// Inputs
706
707	.spu_mactl_stxa_force_abort (spu_mactl_stxa_force_abort),
708	.spu_mactl_kill_op (spu_mactl_ma_kill_op),
709
710	.reset (spu_mactl_ctl_reset),
711	.rclk (rclk),
712	.se (se),
713	.spu_madp_m_eq_n (spu_madp_m_eq_n),
714	.spu_madp_m_lt_n (spu_madp_m_lt_n),
715	.spu_mactl_expop (spu_mactl_expop),
716	.spu_mactl_mulop (spu_mactl_mulop),
717	.spu_mactl_redop (spu_mactl_redop),
718	.spu_mamul_mul_done(spu_mamul_mul_done),
719	.spu_mactl_iss_pulse_dly(spu_mactl_iss_pulse_dly),
720	.spu_maaddr_jptr_eqz(spu_maaddr_jptr_eqz_mared),
721	.spu_maaddr_len_eqmax(spu_maaddr_len_eqmax),
722	.spu_mast_stbuf_wen(spu_mast_stbuf_wen),
723	.spu_madp_cout_oprnd_sub_mod(spu_madp_cout_oprnd_sub_mod));
724	// -------------------------------------------------------------------------
725
726	spu_maexp spu_maexp (//in
727
728	/AUTOINST/
729	// Outputs
730	.spu_maexp_e_rd_oprnd_sel(spu_maexp_e_rd_oprnd_sel),
731	.spu_maexp_shift_e (spu_maexp_shift_e),
732	.spu_maexp_e_data_wen(spu_maexp_e_data_wen),
733	.spu_maexp_incr_es_ptr(spu_maexp_incr_es_ptr),
734	.spu_maexp_es_max_init(spu_maexp_es_max_init),
735	.spu_maexp_es_e_ptr_rst(spu_maexp_es_e_ptr_rst),
736	.spu_maexp_done_set(spu_maexp_done_set),
737	.spu_maexp_memren (spu_maexp_memren),
738	.spu_maexp_start_mulred_aequb(spu_maexp_start_mulred_aequb),
739	.spu_maexp_start_mulred_anoteqb(spu_maexp_start_mulred_anoteqb),
740	// Inputs
741
742	.spu_mactl_stxa_force_abort (spu_mactl_stxa_force_abort),
743	.spu_mactl_kill_op (spu_mactl_ma_kill_op),
744
745	.reset (spu_mactl_ctl_reset),
746	.rclk (rclk),
747	.se (se),
748	.spu_maaddr_esmax (spu_maaddr_esmax),
749	.spu_maaddr_esmod64(spu_maaddr_esmod64),
750	.spu_madp_e_eq_one (spu_madp_e_eq_one),
751	.spu_mared_red_done(spu_mared_red_done),
752	.spu_mactl_iss_pulse_dly(spu_mactl_iss_pulse_dly),
753	.spu_mactl_expop (spu_mactl_expop));
754
755	// -------------------------------------------------------------------------
756
757
758	spu_maaeqb spu_maaeqb (//out
759	.spu_maaeqb_a_leftshft (spu_mul_mulres_lshft),
760
761	/AUTOINST/
762	// Outputs
763	.spu_maaeqb_memwen(spu_maaeqb_memwen),
764	.spu_maaeqb_memren(spu_maaeqb_memren),
765	.spu_maaeqb_rst_iptr(spu_maaeqb_rst_iptr),
766	.spu_maaeqb_rst_jptr(spu_maaeqb_rst_jptr),
767	.spu_maaeqb_incr_iptr(spu_maaeqb_incr_iptr),
768	.spu_maaeqb_incr_jptr(spu_maaeqb_incr_jptr),
769	.spu_maaeqb_a_rd_oprnd_sel(spu_maaeqb_a_rd_oprnd_sel),
770	.spu_maaeqb_ax_rd_oprnd_sel(spu_maaeqb_ax_rd_oprnd_sel),
771	.spu_maaeqb_m_rd_oprnd_sel(spu_maaeqb_m_rd_oprnd_sel),
772	.spu_maaeqb_me_rd_oprnd_sel(spu_maaeqb_me_rd_oprnd_sel),
773	.spu_maaeqb_n_rd_oprnd_sel(spu_maaeqb_n_rd_oprnd_sel),
774	.spu_maaeqb_m_wr_oprnd_sel(spu_maaeqb_m_wr_oprnd_sel),
775	.spu_maaeqb_me_wr_oprnd_sel(spu_maaeqb_me_wr_oprnd_sel),
776	.spu_maaeqb_iminus1_ptr_sel(spu_maaeqb_iminus1_ptr_sel),
777	.spu_maaeqb_j_ptr_sel(spu_maaeqb_j_ptr_sel),
778	.spu_maaeqb_iminusj_ptr_sel(spu_maaeqb_iminusj_ptr_sel),
779	.spu_maaeqb_iminuslenminus1_sel(spu_maaeqb_iminuslenminus1_sel),
780	.spu_maaeqb_irshft_sel(spu_maaeqb_irshft_sel),
781	.spu_maaeqb_jjptr_wen(spu_maaeqb_jjptr_wen),
782	.spu_maaeqb_oprnd2_wen(spu_maaeqb_oprnd2_wen),
783	.spu_maaeqb_oprnd2_bypass(spu_maaeqb_oprnd2_bypass),
784	.spu_maaeqb_oprnd1_mxsel(spu_maaeqb_oprnd1_mxsel[1:0]),
785	.spu_maaeqb_oprnd1_wen(spu_maaeqb_oprnd1_wen),
786	.spu_maaeqb_mul_req_vld(spu_maaeqb_mul_req_vld),
787	.spu_maaeqb_mul_areg_shf(spu_maaeqb_mul_areg_shf),
788	.spu_maaeqb_mul_acc(spu_maaeqb_mul_acc),
789	.spu_maaeqb_mul_areg_rst(spu_maaeqb_mul_areg_rst),
790	.spu_maaeqb_mul_done(spu_maaeqb_mul_done),
791
792	.spu_maaeqb_jjptr_sel(spu_maaeqb_jjptr_sel),
793
794	// Inputs
795
796	.spu_mactl_stxa_force_abort (spu_mactl_stxa_force_abort),
797	.spu_mactl_kill_op (spu_mactl_ma_kill_op),
798
799	.reset (spu_mactl_ctl_reset),
800	.rclk (rclk),
801	.se (se),
802	.spu_maaddr_iequtwolenplus2(spu_maaddr_iequtwolenplus2),
803	.spu_maaddr_iequtwolenplus1(spu_maaddr_iequtwolenplus1),
804	.spu_maaddr_jequiminus1(spu_maaddr_jequiminus1),
805	.spu_maaddr_jequlen(spu_maaddr_jequlen),
806	.spu_maaddr_halfpnt_set(spu_maaddr_halfpnt_set),
807	.mul_spu_ack (mul_spu_ack),
808	.mul_spu_shf_ack (mul_spu_shf_ack),
809	.spu_mactl_mulop (spu_mactl_mulop),
810	.spu_mactl_iss_pulse_dly(spu_mactl_iss_pulse_dly),
811	.spu_maexp_start_mulred_aequb(spu_maexp_start_mulred_aequb),
812	.spu_mactl_expop (spu_mactl_expop),
813	.spu_maaddr_jequiminus1rshft(spu_maaddr_jequiminus1rshft),
814	.spu_maaddr_iequtwolen(spu_maaddr_iequtwolen),
815	.spu_maaddr_ieven(spu_maaddr_ieven),
816	.spu_maaddr_ieq0 (spu_maaddr_ieq0),
817	.spu_maaddr_aequb(spu_maaddr_aequb));
818
819
820
821	endmodule

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source: XOpenSparcT1/trunk/T1-CPU/spu/spu_ctl.v @ 6

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