1 | // ========== Copyright Header Begin ========================================== |
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2 | // |
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3 | // OpenSPARC T1 Processor File: tlu_hyperv.v |
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4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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6 | // |
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7 | // The above named program is free software; you can redistribute it and/or |
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8 | // modify it under the terms of the GNU General Public |
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9 | // License version 2 as published by the Free Software Foundation. |
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10 | // |
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11 | // The above named program is distributed in the hope that it will be |
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12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | // General Public License for more details. |
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15 | // |
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16 | // You should have received a copy of the GNU General Public |
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17 | // License along with this work; if not, write to the Free Software |
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18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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19 | // |
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20 | // ========== Copyright Header End ============================================ |
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21 | //////////////////////////////////////////////////////////////////////// |
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22 | /* |
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23 | // Description: Block that contain most of the Hypervisor support |
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24 | // additions |
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25 | */ |
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26 | //////////////////////////////////////////////////////////////////////// |
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27 | // Global header file includes |
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28 | //////////////////////////////////////////////////////////////////////// |
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29 | `include "sys.h" // system level definition file which contains the |
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30 | // time scale definition |
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31 | |
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32 | `include "tlu.h" |
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33 | |
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34 | //////////////////////////////////////////////////////////////////////// |
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35 | // Local header file includes / local defines |
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36 | //////////////////////////////////////////////////////////////////////// |
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37 | |
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38 | module tlu_hyperv (/*AUTOARG*/ |
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39 | // outputs |
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40 | tlu_htickcmp_rw_e, tlu_gl_rw_m, tlu_hpstate_din_sel0, tlu_hpstate_din_sel1, |
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41 | tlu_hpstate_din_sel2, tlu_hpstate_din_sel3, tlu_update_hpstate_l_w2, |
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42 | tlu_htickcmp_intdis, tlu_gl_lvl0, tlu_gl_lvl1, tlu_gl_lvl2, tlu_gl_lvl3, |
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43 | tlu_htstate_rw_d, tlu_wr_hintp_g, tlu_htstate_rw_g, tlu_set_hintp_sel_g, |
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44 | tlu_htba_en_l, tlu_scpd_wr_addr_g, tlu_scpd_wr_vld_g, tlu_scpd_rd_vld_m, |
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45 | tlu_scpd_rd_addr_m, tlu_hscpd_dacc_excpt_m, tlu_hyperv_rdpr_sel, |
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46 | tlu_exu_agp_swap, tlu_exu_agp, tlu_cpu_mondo_cmp, tlu_dev_mondo_cmp, |
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47 | tlu_resum_err_cmp, tlu_asi_queue_rd_vld_g, tlu_asi_queue_data_g, tlu_ld_data_vld_g, |
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48 | tlu_va_ill_g, tlu_asi_queue_rdata_g, tlu_qtail_dacc_excpt_m, tlu_asi_write_g, so, |
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49 | inc_ind_asi_wr_indr, inc_ind_asi_wr_inrr, inc_ind_asi_rd_invr, tlu_local_thrid_g, |
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50 | // inputs |
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51 | ifu_tlu_thrid_d, ifu_tlu_sraddr_d, tlu_wsr_data_w_global, tlu_tickcmp_sel, |
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52 | tlu_thrd_traps_w2, tlu_wsr_inst_nq_g, tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g, |
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53 | tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g, tlu_dnrtry_global_g, tlu_tick_ctl_din, |
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54 | tlu_pstate_priv, tlu_select_tba_w2, tlu_hpstate_priv, tlu_hpstate_enb, |
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55 | tlu_asi_state_e, ifu_lsu_alt_space_e, ifu_lsu_ld_inst_e, ifu_lsu_st_inst_e, |
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56 | lsu_tlu_early_flush_w, tlu_por_rstint_g, tlu_agp_tid_w2, // exu_lsu_ldst_va_e, |
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57 | tlu_local_flush_w, ifu_tlu_flush_fd_w, tlu_inst_vld_m, tlu_lsu_int_ldxa_vld_w2, |
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58 | tlu_asi_data_nf_vld_w2, lsu_tlu_ldst_va_m, arst_l, grst_l, rst_tri_en, |
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59 | si, se, rclk); |
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60 | |
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61 | //================================================= |
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62 | // output |
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63 | //================================================= |
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64 | // mux select to tdp to access the hyper-privileged ASR registers |
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65 | output tlu_htickcmp_rw_e; |
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66 | output tlu_gl_rw_m; |
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67 | // output tlu_gl_rw_g; |
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68 | |
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69 | // global switch indicator - used to be in tlu_tcl |
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70 | output [1:0] tlu_exu_agp; |
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71 | // output [1:0] tlu_exu_agp_tid; |
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72 | output tlu_exu_agp_swap; |
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73 | // |
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74 | // global register outputs |
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75 | output [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl0; // global register value t0 |
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76 | output [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl1; // global register value t1 |
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77 | output [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl2; // global register value t2 |
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78 | output [`TSA_GLOBAL_WIDTH-1:0] tlu_gl_lvl3; // global register value t3 |
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79 | |
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80 | // mux selects to choose source of data to store in the hpstate regs |
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81 | output [1:0] tlu_hpstate_din_sel0; |
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82 | output [1:0] tlu_hpstate_din_sel1; |
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83 | output [1:0] tlu_hpstate_din_sel2; |
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84 | output [1:0] tlu_hpstate_din_sel3; |
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85 | // |
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86 | // mux selects to read out the ASR registers |
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87 | // output [3:0] tlu_rdpr_mx5_sel; |
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88 | output [4:0] tlu_hyperv_rdpr_sel; |
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89 | // signal indicating mx5 is used |
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90 | // output tlu_rdpr_mx5_active; |
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91 | // |
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92 | // hpstate write enable |
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93 | // modified for timing |
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94 | // output [`TLU_THRD_NUM-1:0] tlu_update_hpstate_l_g; |
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95 | output [`TLU_THRD_NUM-1:0] tlu_update_hpstate_l_w2; |
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96 | // |
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97 | // htick compare reg write enable |
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98 | // output [`TLU_THRD_NUM-1:0] htickcmp_intdis_en; |
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99 | // htick compare interrupt disable |
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100 | output tlu_htickcmp_intdis; |
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101 | |
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102 | // clock enable for hintp regs. |
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103 | // output [`TLU_THRD_NUM-1:0] tlu_hintp_en_l_g; |
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104 | // wr control for hintp regs. |
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105 | output [`TLU_THRD_NUM-1:0] tlu_wr_hintp_g; |
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106 | // set control for hintp regs. |
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107 | // output [`TLU_THRD_NUM-1:0] tlu_set_hintp_g; |
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108 | output [`TLU_THRD_NUM-1:0] tlu_set_hintp_sel_g; |
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109 | // |
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110 | // update enable for the htba registers |
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111 | output [`TLU_THRD_NUM-1:0] tlu_htba_en_l; |
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112 | // |
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113 | // hypervisor lite indicator |
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114 | // output [`TLU_THRD_NUM-1:0] tlu_hyper_lite; |
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115 | // |
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116 | // hyper-privileged scratch-pad data access exception |
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117 | output tlu_hscpd_dacc_excpt_m; |
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118 | // |
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119 | // store instruction to alt space |
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120 | output tlu_asi_write_g; |
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121 | output [`TLU_THRD_NUM-1:0] inc_ind_asi_wr_indr; |
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122 | output [`TLU_THRD_NUM-1:0] inc_ind_asi_wr_inrr; |
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123 | output [`TLU_THRD_NUM-1:0] inc_ind_asi_rd_invr; |
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124 | output [`TLU_THRD_NUM-1:0] tlu_local_thrid_g; |
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125 | |
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126 | // read and write valids for the scratch-pad |
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127 | output tlu_scpd_rd_vld_m, tlu_scpd_wr_vld_g; |
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128 | output [`SCPD_RW_ADDR_WIDTH-1:0] tlu_scpd_wr_addr_g; |
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129 | output [`SCPD_RW_ADDR_WIDTH-1:0] tlu_scpd_rd_addr_m; |
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130 | // |
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131 | // decode of the htstate register write/read |
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132 | output tlu_htstate_rw_d; |
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133 | output tlu_htstate_rw_g; |
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134 | // |
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135 | // select for rdpr read in tlu_tdp |
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136 | // output tlu_htba_rsr_sel; |
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137 | // |
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138 | // |
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139 | output [`TLU_THRD_NUM-1:0] tlu_cpu_mondo_cmp; |
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140 | output [`TLU_THRD_NUM-1:0] tlu_dev_mondo_cmp; |
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141 | output [`TLU_THRD_NUM-1:0] tlu_resum_err_cmp; |
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142 | output tlu_qtail_dacc_excpt_m; |
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143 | // |
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144 | // asi queue rdata output |
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145 | output [`TLU_ASI_QUE_WIDTH-1:0] tlu_asi_queue_rdata_g; |
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146 | output tlu_asi_queue_rd_vld_g; |
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147 | output tlu_ld_data_vld_g; |
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148 | // output tlu_scpd_rd_vld_g; |
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149 | output tlu_va_ill_g; |
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150 | // output tlu_va_all_zero_g; |
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151 | output tlu_lsu_int_ldxa_vld_w2; |
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152 | // |
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153 | // global nets |
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154 | output so; |
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155 | |
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156 | //================================================= |
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157 | // input |
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158 | //================================================= |
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159 | // non-thread specific por reset indicator |
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160 | // modified for timing |
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161 | // input [1:0] ifu_tlu_thrid_e; |
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162 | input [1:0] ifu_tlu_thrid_d; |
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163 | // |
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164 | // staged write asr instruction |
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165 | // modified for timing |
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166 | // input tlu_wsr_inst_g; |
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167 | input tlu_wsr_inst_nq_g; |
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168 | |
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169 | // non-threaded por instruciton |
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170 | input [`TLU_THRD_NUM-1:0] tlu_por_rstint_g; |
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171 | // |
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172 | // addr of sr(st/pr) |
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173 | input [`TLU_ASR_ADDR_WIDTH-1:0] ifu_tlu_sraddr_d; |
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174 | // |
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175 | // staged pr/st data from irf. |
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176 | input [`TLU_GLOBAL_WIDTH-1:0] tlu_wsr_data_w_global; |
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177 | |
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178 | // restored global value for done/retry instructions |
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179 | input [`TSA_GLOBAL_WIDTH-1:0] tlu_dnrtry_global_g; |
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180 | |
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181 | // thread specific done and retry signals |
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182 | input tlu_dnrtry0_inst_g, tlu_dnrtry1_inst_g; |
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183 | input tlu_dnrtry2_inst_g, tlu_dnrtry3_inst_g; |
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184 | // |
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185 | // thread specific trap assetion signals |
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186 | // modified due to timing |
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187 | // input tlu_thrd0_traps, tlu_thrd1_traps; |
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188 | // input tlu_thrd2_traps, tlu_thrd3_traps; |
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189 | input [`TLU_THRD_NUM-1:0] tlu_thrd_traps_w2; |
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190 | // |
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191 | // indicating whether the trap is supervisor or hypervisor |
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192 | // added for bug 2889 |
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193 | // modified due to timing |
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194 | // input tlu_select_tba_g; |
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195 | input tlu_select_tba_w2; |
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196 | // |
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197 | input tlu_tick_ctl_din; |
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198 | // htick compare match |
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199 | // input tlu_htick_match; |
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200 | // |
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201 | // select src for tickcmp |
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202 | input [`TLU_THRD_NUM-1:0] tlu_tickcmp_sel; |
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203 | // |
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204 | // pstate - supervisor privilege |
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205 | input [`TLU_THRD_NUM-1:0] tlu_pstate_priv; |
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206 | // hpstate - hypervisor privilege |
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207 | input [`TLU_THRD_NUM-1:0] tlu_hpstate_priv; |
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208 | // hpstate - hypervisor lite enb |
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209 | input [`TLU_THRD_NUM-1:0] tlu_hpstate_enb; |
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210 | // thread id for the agp that needs swap |
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211 | // modified for timing |
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212 | // input [1:0] tlu_agp_tid_g; |
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213 | input [1:0] tlu_agp_tid_w2; |
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214 | // ASI addresses and valid bits for decode to |
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215 | // access the ASI registers |
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216 | input ifu_lsu_alt_space_e; // valid bit for the ASI data |
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217 | input ifu_lsu_ld_inst_e; // read enable |
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218 | input ifu_lsu_st_inst_e; // write enable |
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219 | // replaced due to timing violations |
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220 | // input tlu_nlsu_flush_w; // trap flush |
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221 | input tlu_local_flush_w; // trap flush |
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222 | input ifu_tlu_flush_fd_w; // trap flush |
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223 | input lsu_tlu_early_flush_w; // trap flush |
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224 | input tlu_asi_data_nf_vld_w2; // trap flush |
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225 | input tlu_inst_vld_m; // instruciton valid |
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226 | // |
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227 | // asi to be read/written |
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228 | input [`TLU_ASI_STATE_WIDTH-1:0] tlu_asi_state_e; |
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229 | // input [`TLU_ASI_VA_WIDTH-1:0] exu_lsu_ldst_va_e; |
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230 | input [`TLU_ASI_VA_WIDTH-1:0] lsu_tlu_ldst_va_m; |
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231 | // head and tail pointers |
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232 | input [`TLU_ASI_QUE_WIDTH-1:0] tlu_asi_queue_data_g; |
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233 | |
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234 | //reset |
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235 | // input tlu_rst_l; // unit reset |
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236 | input grst_l ; // unit reset |
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237 | input arst_l ; // unit reset |
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238 | input rst_tri_en ; // unit reset |
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239 | //clk |
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240 | input rclk; |
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241 | // |
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242 | // global nets |
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243 | input si, se; |
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244 | |
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245 | /*AUTOOUTPUT*/ |
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246 | // |
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247 | // staged thread id |
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248 | wire [1:0] thrid_e, thrid_m, thrid_g; |
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249 | // decoded thread id |
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250 | wire [`TLU_THRD_NUM-1:0] thread_sel_id_e; |
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251 | wire [`TLU_THRD_NUM-1:0] thread_sel_id_m; |
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252 | wire [`TLU_THRD_NUM-1:0] thread_sel_id_g; |
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253 | wire [`TLU_THRD_NUM-1:0] thread_sel_id_w2; |
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254 | // |
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255 | // flush due to "early traps" |
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256 | wire local_flush_all_w; // trap flush |
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257 | wire local_flush_all_w2; // trap flush |
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258 | // |
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259 | // por indicators generations |
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260 | wire por_rstint0_g, por_rstint1_g; |
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261 | wire por_rstint2_g, por_rstint3_g; |
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262 | // |
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263 | // GL register definitions - one GL register/thread |
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264 | wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl0, gl_lvl1, gl_lvl2, gl_lvl3; |
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265 | // updated value of the GL registers |
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266 | wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl0_new, gl_lvl1_new; |
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267 | wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl2_new, gl_lvl3_new; |
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268 | wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl0_update_g, gl_lvl1_update_g; |
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269 | wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl2_update_g, gl_lvl3_update_g; |
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270 | wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl0_update_w2, gl_lvl1_update_w2; |
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271 | wire [`TSA_GLOBAL_WIDTH-1:0] gl_lvl2_update_w2, gl_lvl3_update_w2; |
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272 | wire [`TSA_GLOBAL_WIDTH-1:0] wsr_gl_lvl0_data, wsr_gl_lvl1_data; |
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273 | wire [`TSA_GLOBAL_WIDTH-1:0] wsr_gl_lvl2_data, wsr_gl_lvl3_data; |
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274 | wire [`TSA_GLOBAL_WIDTH-1:0] dnrtry_gl_lvl0_data, dnrtry_gl_lvl1_data; |
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275 | wire [`TSA_GLOBAL_WIDTH-1:0] dnrtry_gl_lvl2_data, dnrtry_gl_lvl3_data; |
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276 | // value to be incremented for the GL registers |
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277 | // modified due to timing |
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278 | // wire gl0_incr_sel, gl1_incr_sel, gl2_incr_sel, gl3_incr_sel; |
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279 | // wire[1:0] gl_lvl0_incr, gl_lvl1_incr, gl_lvl2_incr, gl_lvl3_incr; |
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280 | // indicators to signal gl is at certain pre-defined values |
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281 | // added for timing |
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282 | wire [`TLU_THRD_NUM-1:0] gl_incr_sel_w2; |
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283 | wire [`TLU_THRD_NUM-1:0] gl_update_sel_g; |
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284 | wire [`TLU_THRD_NUM-1:0] gl_update_sel_w2; |
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285 | wire [`TLU_THRD_NUM-1:0] gl_priv_max_sel_w2; |
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286 | wire gl_lvl0_at_maxgl, gl_lvl1_at_maxgl; |
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287 | wire gl_lvl2_at_maxgl, gl_lvl3_at_maxgl; |
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288 | wire gl_lvl0_at_maxstl, gl_lvl1_at_maxstl; |
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289 | wire gl_lvl2_at_maxstl, gl_lvl3_at_maxstl; |
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290 | // gl write enables |
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291 | wire gl0_en, gl1_en, gl2_en, gl3_en; |
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292 | wire [`TLU_THRD_NUM-1:0] dnrtry_inst_w2; |
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293 | // maxgl control |
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294 | wire [`TLU_THRD_NUM-1:0] maxstl_gl_dnrtry_sel; |
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295 | wire [`TLU_THRD_NUM-1:0] maxstl_gl_wr_sel; |
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296 | wire [`TLU_THRD_NUM-1:0] maxgl_gl_wr_sel; |
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297 | // decoded thread info for agp swap |
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298 | // wire [`TLU_THRD_NUM-1:0] agp_thrid; |
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299 | wire [`TLU_THRD_NUM-1:0] agp_thrid_w2; |
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300 | // modified for for timing fix |
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301 | // wire agp_swap; |
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302 | // wire [1:0] agp_new; |
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303 | wire wsr_inst_g, wsr_inst_w2; |
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304 | wire agp_swap_w2, agp_swap_w3; |
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305 | wire [1:0] agp_new_w2, agp_new_w3; |
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306 | // |
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307 | // hyper-privileged ASR registers |
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308 | wire [`TLU_THRD_NUM-1:0] tlu_wr_hintp_g; |
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309 | wire htba_rw_d, hpstate_rw_d, htstate_rw_d, hintp_rw_d; |
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310 | wire htickcmp_rw_d, gl_rw_d; |
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311 | wire htba_rw_e, hpstate_rw_e, htstate_rw_e, hintp_rw_e; |
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312 | wire htickcmp_rw_e, gl_rw_e; |
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313 | wire htba_rw_m, hpstate_rw_m, htstate_rw_m, hintp_rw_m; |
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314 | wire htickcmp_rw_m, gl_rw_m; |
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315 | wire htba_rw_g, hpstate_rw_g, htstate_rw_g, hintp_rw_g; |
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316 | wire htickcmp_rw_g, gl_rw_g; |
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317 | wire [`TLU_THRD_NUM-1:0] htickcmp_intdis_en; |
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318 | wire hpstate_rw_w2; |
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319 | // |
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320 | // hyper-lite mode indicator |
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321 | wire [`TLU_THRD_NUM-1:0] tlu_hyper_lite; |
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322 | // |
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323 | // contorls to update the hpstate registers |
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324 | // wire update_hpstate0_g, update_hpstate1_g; |
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325 | // wire update_hpstate2_g, update_hpstate3_g; |
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326 | wire [`TLU_THRD_NUM-1:0] update_hpstate_g; |
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327 | wire [`TLU_THRD_NUM-1:0] update_hpstate_w2; |
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328 | // |
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329 | // htick interrupt disable control |
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330 | wire htick_intdis0, htick_intdis1; |
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331 | wire htick_intdis2, htick_intdis3; |
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332 | // |
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333 | // local addr of sr(st/pr) |
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334 | wire [`TLU_ASR_ADDR_WIDTH-3:0] sraddr; |
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335 | |
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336 | // ASI_QUEUE for hyper visor |
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337 | // thread 0 |
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338 | wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo0_head; |
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339 | wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo0_tail; |
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340 | wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo0_head; |
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341 | wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo0_tail; |
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342 | wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err0_head; |
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343 | wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err0_tail; |
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344 | wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err0_head; |
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345 | wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err0_tail; |
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346 | // thread 1 |
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347 | wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo1_head; |
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348 | wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo1_tail; |
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349 | wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo1_head; |
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350 | wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo1_tail; |
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351 | wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err1_head; |
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352 | wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err1_tail; |
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353 | wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err1_head; |
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354 | wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err1_tail; |
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355 | // thread 2 |
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356 | wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo2_head; |
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357 | wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo2_tail; |
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358 | wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo2_head; |
---|
359 | wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo2_tail; |
---|
360 | wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err2_head; |
---|
361 | wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err2_tail; |
---|
362 | wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err2_head; |
---|
363 | wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err2_tail; |
---|
364 | // thread 3 |
---|
365 | wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo3_head; |
---|
366 | wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo3_tail; |
---|
367 | wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo3_head; |
---|
368 | wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo3_tail; |
---|
369 | wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err3_head; |
---|
370 | wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err3_tail; |
---|
371 | wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err3_head; |
---|
372 | wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err3_tail; |
---|
373 | // |
---|
374 | // read asi data from the asi queues |
---|
375 | wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo_hd_rdata; |
---|
376 | wire [`TLU_ASI_QUE_WIDTH-1:0] cpu_mondo_ta_rdata; |
---|
377 | wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo_hd_rdata; |
---|
378 | wire [`TLU_ASI_QUE_WIDTH-1:0] dev_mondo_ta_rdata; |
---|
379 | wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err_hd_rdata; |
---|
380 | wire [`TLU_ASI_QUE_WIDTH-1:0] resum_err_ta_rdata; |
---|
381 | wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err_hd_rdata; |
---|
382 | wire [`TLU_ASI_QUE_WIDTH-1:0] nresum_err_ta_rdata; |
---|
383 | wire [`TLU_ASI_QUE_WIDTH-1:0] asi_queue_rdata1_g; |
---|
384 | wire [`TLU_ASI_QUE_WIDTH-1:0] asi_queue_rdata2_g; |
---|
385 | wire asi_qrdata_mx_sel2; |
---|
386 | // |
---|
387 | // head and tail comparison results |
---|
388 | // modified due to timing violations |
---|
389 | // wire cpu_mondo_head_rw_e, cpu_mondo_tail_rw_e; |
---|
390 | // wire dev_mondo_head_rw_e, dev_mondo_tail_rw_e; |
---|
391 | // wire resum_err_head_rw_e, resum_err_tail_rw_e; |
---|
392 | // wire nresum_err_head_rw_e, nresum_err_tail_rw_e; |
---|
393 | // |
---|
394 | wire cpu_mondo_head_rw_m, cpu_mondo_tail_rw_m; |
---|
395 | wire dev_mondo_head_rw_m, dev_mondo_tail_rw_m; |
---|
396 | wire resum_err_head_rw_m, resum_err_tail_rw_m; |
---|
397 | wire nresum_err_head_rw_m, nresum_err_tail_rw_m; |
---|
398 | // |
---|
399 | wire cpu_mondo_head_rw_g, cpu_mondo_tail_rw_g; |
---|
400 | wire dev_mondo_head_rw_g, dev_mondo_tail_rw_g; |
---|
401 | wire resum_err_head_rw_g, resum_err_tail_rw_g; |
---|
402 | wire nresum_err_head_rw_g, nresum_err_tail_rw_g; |
---|
403 | // creating one-hot selects |
---|
404 | // wire cpu_mondo_hd_onehot_g, cpu_mondo_ta_onehot_g; |
---|
405 | // wire dev_mondo_hd_onehot_g, dev_mondo_ta_onehot_g; |
---|
406 | // wire resum_err_hd_onehot_g, resum_err_ta_onehot_g; |
---|
407 | // wire nresum_err_hd_onehot_g, nresum_err_ta_onehot_g; |
---|
408 | // read |
---|
409 | wire [`TLU_THRD_NUM-1:0] cpu_mondo_head_rd_g; |
---|
410 | wire cpu_mondo_hd_rd_g; |
---|
411 | wire [`TLU_THRD_NUM-1:0] cpu_mondo_tail_rd_g; |
---|
412 | wire cpu_mondo_ta_rd_g; |
---|
413 | wire [`TLU_THRD_NUM-1:0] dev_mondo_head_rd_g; |
---|
414 | wire dev_mondo_hd_rd_g; |
---|
415 | wire [`TLU_THRD_NUM-1:0] dev_mondo_tail_rd_g; |
---|
416 | wire dev_mondo_ta_rd_g; |
---|
417 | wire [`TLU_THRD_NUM-1:0] resum_err_head_rd_g; |
---|
418 | wire resum_err_hd_rd_g; |
---|
419 | wire [`TLU_THRD_NUM-1:0] resum_err_tail_rd_g; |
---|
420 | wire resum_err_ta_rd_g; |
---|
421 | wire [`TLU_THRD_NUM-1:0] nresum_err_head_rd_g; |
---|
422 | wire nresum_err_hd_rd_g; |
---|
423 | wire [`TLU_THRD_NUM-1:0] nresum_err_tail_rd_g; |
---|
424 | wire nresum_err_ta_rd_g; |
---|
425 | wire [3:0] asi_qrdata_mx1_sel; |
---|
426 | wire [3:0] asi_qrdata_mx2_sel; |
---|
427 | // write |
---|
428 | wire [`TLU_THRD_NUM-1:0] cpu_mondo_head_wr_g; |
---|
429 | wire [`TLU_THRD_NUM-1:0] cpu_mondo_tail_wr_g; |
---|
430 | wire [`TLU_THRD_NUM-1:0] dev_mondo_head_wr_g; |
---|
431 | wire [`TLU_THRD_NUM-1:0] dev_mondo_tail_wr_g; |
---|
432 | wire [`TLU_THRD_NUM-1:0] resum_err_head_wr_g; |
---|
433 | wire [`TLU_THRD_NUM-1:0] resum_err_tail_wr_g; |
---|
434 | wire [`TLU_THRD_NUM-1:0] nresum_err_head_wr_g; |
---|
435 | wire [`TLU_THRD_NUM-1:0] nresum_err_tail_wr_g; |
---|
436 | // |
---|
437 | // ASI va address |
---|
438 | // modified due to timing fix |
---|
439 | // wire [`TLU_ASI_VA_WIDTH-1:0] tlu_ldst_va_e; |
---|
440 | wire [`TLU_ASI_VA_WIDTH-1:0] tlu_ldst_va_m; |
---|
441 | // |
---|
442 | // ASI read or write enables |
---|
443 | wire asi_queue_write_e; |
---|
444 | wire asi_queue_read_e; |
---|
445 | wire asi_queue_write_pq_m; |
---|
446 | wire asi_queue_read_pq_m; |
---|
447 | wire asi_queue_write_m; |
---|
448 | wire asi_queue_read_m; |
---|
449 | wire asi_queue_write_uf_g; |
---|
450 | // wire asi_queue_read_uf_g; |
---|
451 | wire asi_queue_write_g; |
---|
452 | wire asi_queue_read_g; |
---|
453 | // |
---|
454 | // decoded ASI addresses |
---|
455 | // ASI QUE |
---|
456 | wire asi_queue_rw_e, asi_queue_rw_m, asi_queue_rw_g; |
---|
457 | wire asi_inrr_rw_e, asi_inrr_rw_m, asi_inrr_rw_g; |
---|
458 | wire asi_indr_rw_e, asi_indr_rw_m, asi_indr_rw_g; |
---|
459 | wire asi_invr_rw_e, asi_invr_rw_m, asi_invr_rw_g; |
---|
460 | // supervisor scratch-pad asi state |
---|
461 | wire asi_scpd_rw_e, asi_scpd_rw_m; |
---|
462 | // hypervisor scratch-pad asi state |
---|
463 | wire asi_hscpd_rw_e, asi_hscpd_rw_m; |
---|
464 | wire asi_scpd_rw_vld_m, asi_scpd_rw_vld_g; |
---|
465 | // legal va addresses |
---|
466 | // modified due to timing |
---|
467 | // wire que_legal_va_e; |
---|
468 | wire que_legal_va_m; |
---|
469 | // modified due to timing |
---|
470 | // illegal va range indicator |
---|
471 | // wire que_ill_va_e, |
---|
472 | wire que_ill_va_m, que_ill_va_g; |
---|
473 | // modified due to timing |
---|
474 | // wire scpd_ill_va_e, |
---|
475 | wire scpd_ill_va_m, scpd_ill_va_g; |
---|
476 | // alignment checking |
---|
477 | wire va_not_baligned_m; |
---|
478 | // no longer necessary |
---|
479 | // wire va_all_zero_e, va_all_zero_m, va_all_zero_g; |
---|
480 | // write operation to queue tails |
---|
481 | wire qtail_write_m; |
---|
482 | // |
---|
483 | // data_access_exception for hyper-privileged scratch-pad |
---|
484 | wire hscpd_data_acc_excpt_m; |
---|
485 | wire hscpd_data_acc_excpt_pq_m; |
---|
486 | // write to hypervisor scratch-pad using 0x20 ASI state |
---|
487 | wire hscpd_priv_asi_acc_m; |
---|
488 | // access hypervisor scratchpad va addresses |
---|
489 | wire hscpd_va_rw_m; |
---|
490 | // |
---|
491 | // relevant portion of the va address for the scratch-pad |
---|
492 | // modified due to timing fix |
---|
493 | // wire [`TLU_ASI_SCPD_VA_HI:0] scpd_addr_va_e; |
---|
494 | wire [`SCPD_ASI_VA_ADDR_WIDTH-1:0] scpd_addr_va_m; |
---|
495 | wire [`SCPD_ASI_VA_ADDR_WIDTH-1:0] scpd_addr_va_g; |
---|
496 | // |
---|
497 | // load instruction data valid |
---|
498 | wire asi_ld_addr_vld_m, asi_ld_addr_vld_g; |
---|
499 | |
---|
500 | // privilege or hyper-privileged address indicators |
---|
501 | wire asr_hyperp, asr_priv; |
---|
502 | // |
---|
503 | // local reset |
---|
504 | wire local_rst_l; |
---|
505 | wire local_rst; |
---|
506 | // local clk |
---|
507 | wire clk; |
---|
508 | |
---|
509 | //////////////////////////////////////////////////////////////////////// |
---|
510 | // local reset |
---|
511 | //////////////////////////////////////////////////////////////////////// |
---|
512 | |
---|
513 | dffrl_async dffrl_local_rst_l( |
---|
514 | .din (grst_l), |
---|
515 | .clk (clk), |
---|
516 | .rst_l(arst_l), |
---|
517 | .q (local_rst_l), |
---|
518 | .se (se), |
---|
519 | .si (), |
---|
520 | .so () |
---|
521 | ); |
---|
522 | |
---|
523 | assign local_rst = ~local_rst_l; |
---|
524 | |
---|
525 | //////////////////////////////////////////////////////////////////////// |
---|
526 | // local clock |
---|
527 | //////////////////////////////////////////////////////////////////////// |
---|
528 | |
---|
529 | assign clk = rclk; |
---|
530 | |
---|
531 | //////////////////////////////////////////////////////////////////////// |
---|
532 | // Hyper-lite mode indicator |
---|
533 | //////////////////////////////////////////////////////////////////////// |
---|
534 | |
---|
535 | assign tlu_hyper_lite[0] = |
---|
536 | tlu_hpstate_priv[0]| (~tlu_hpstate_enb[0] & tlu_pstate_priv[0]); |
---|
537 | assign tlu_hyper_lite[1] = |
---|
538 | tlu_hpstate_priv[1]| (~tlu_hpstate_enb[1] & tlu_pstate_priv[1]); |
---|
539 | assign tlu_hyper_lite[2] = |
---|
540 | tlu_hpstate_priv[2]| (~tlu_hpstate_enb[2] & tlu_pstate_priv[2]); |
---|
541 | assign tlu_hyper_lite[3] = |
---|
542 | tlu_hpstate_priv[3]| (~tlu_hpstate_enb[3] & tlu_pstate_priv[3]); |
---|
543 | |
---|
544 | //////////////////////////////////////////////////////////////////////// |
---|
545 | // Thread ID staging and decoding |
---|
546 | //////////////////////////////////////////////////////////////////////// |
---|
547 | // |
---|
548 | assign thread_sel_id_e[0] = ~thrid_e[1] & ~thrid_e[0]; |
---|
549 | assign thread_sel_id_e[1] = ~thrid_e[1] & thrid_e[0]; |
---|
550 | assign thread_sel_id_e[2] = thrid_e[1] & ~thrid_e[0]; |
---|
551 | assign thread_sel_id_e[3] = thrid_e[1] & thrid_e[0]; |
---|
552 | |
---|
553 | dff_s #(`TLU_THRD_NUM) dff_thread_sel_id_m ( |
---|
554 | .din (thread_sel_id_e[`TLU_THRD_NUM-1:0]), |
---|
555 | .q (thread_sel_id_m[`TLU_THRD_NUM-1:0]), |
---|
556 | .clk (clk), |
---|
557 | .se (se), |
---|
558 | .si (), |
---|
559 | .so () |
---|
560 | ); |
---|
561 | |
---|
562 | dff_s #(`TLU_THRD_NUM) dff_thread_id_sel_g ( |
---|
563 | .din (thread_sel_id_m[`TLU_THRD_NUM-1:0]), |
---|
564 | .q (thread_sel_id_g[`TLU_THRD_NUM-1:0]), |
---|
565 | .clk (clk), |
---|
566 | .se (se), |
---|
567 | .si (), |
---|
568 | .so () |
---|
569 | ); |
---|
570 | |
---|
571 | dff_s #(`TLU_THRD_NUM) dff_thread_id_sel_w2 ( |
---|
572 | .din (thread_sel_id_g[`TLU_THRD_NUM-1:0]), |
---|
573 | .q (thread_sel_id_w2[`TLU_THRD_NUM-1:0]), |
---|
574 | .clk (clk), |
---|
575 | .se (se), |
---|
576 | .si (), |
---|
577 | .so () |
---|
578 | ); |
---|
579 | |
---|
580 | dff_s #(2) dff_thrid_e ( |
---|
581 | .din (ifu_tlu_thrid_d[1:0]), |
---|
582 | .q (thrid_e[1:0]), |
---|
583 | .clk (clk), |
---|
584 | .se (se), |
---|
585 | .si (), |
---|
586 | .so () |
---|
587 | ); |
---|
588 | |
---|
589 | dff_s #(2) dff_thrid_m ( |
---|
590 | .din (thrid_e[1:0]), |
---|
591 | .q (thrid_m[1:0]), |
---|
592 | .clk (clk), |
---|
593 | .se (se), |
---|
594 | .si (), |
---|
595 | .so () |
---|
596 | ); |
---|
597 | |
---|
598 | dff_s #(2) dff_thrid_g ( |
---|
599 | .din (thrid_m[1:0]), |
---|
600 | .q (thrid_g[1:0]), |
---|
601 | .clk (clk), |
---|
602 | .se (se), |
---|
603 | .si (), |
---|
604 | .so () |
---|
605 | ); |
---|
606 | // |
---|
607 | // modified due to rte failure |
---|
608 | assign tlu_local_thrid_g[0] = ~(|thrid_g[1:0]); |
---|
609 | assign tlu_local_thrid_g[1] = ~thrid_g[1] & thrid_g[0]; |
---|
610 | assign tlu_local_thrid_g[2] = thrid_g[1] & ~thrid_g[0]; |
---|
611 | assign tlu_local_thrid_g[3] = (&thrid_g[1:0]); |
---|
612 | |
---|
613 | /* |
---|
614 | assign tlu_local_thrid_g[`TLU_THRD_NUM-1:0] = |
---|
615 | thread_sel_id_g[`TLU_THRD_NUM-1:0]; |
---|
616 | */ |
---|
617 | |
---|
618 | //////////////////////////////////////////////////////////////////////// |
---|
619 | // POR indicator generation |
---|
620 | //////////////////////////////////////////////////////////////////////// |
---|
621 | // |
---|
622 | // modified for bug 1945 |
---|
623 | /* |
---|
624 | assign por_rstint0_g = tlu_por_rstint_g & thread_sel_id_g[0]; |
---|
625 | assign por_rstint1_g = tlu_por_rstint_g & thread_sel_id_g[1]; |
---|
626 | assign por_rstint2_g = tlu_por_rstint_g & thread_sel_id_g[2]; |
---|
627 | assign por_rstint3_g = tlu_por_rstint_g & thread_sel_id_g[3]; |
---|
628 | */ |
---|
629 | assign por_rstint0_g = tlu_por_rstint_g[0]; |
---|
630 | assign por_rstint1_g = tlu_por_rstint_g[1]; |
---|
631 | assign por_rstint2_g = tlu_por_rstint_g[2]; |
---|
632 | assign por_rstint3_g = tlu_por_rstint_g[3]; |
---|
633 | |
---|
634 | //////////////////////////////////////////////////////////////////////// |
---|
635 | // Hyper-privileged ASR decodes |
---|
636 | //////////////////////////////////////////////////////////////////////// |
---|
637 | // |
---|
638 | // flush signal - modified for timing |
---|
639 | // assign local_flush_all_w = tlu_nlsu_flush_w | lsu_tlu_early_flush_w; |
---|
640 | assign local_flush_all_w = |
---|
641 | tlu_local_flush_w | lsu_tlu_early_flush_w | ifu_tlu_flush_fd_w; |
---|
642 | |
---|
643 | dffr_s dffr_local_flush_all_w2 ( |
---|
644 | .din (local_flush_all_w), |
---|
645 | .q (local_flush_all_w2), |
---|
646 | .rst (local_rst), |
---|
647 | .clk (clk), |
---|
648 | .se (se), |
---|
649 | .si (), |
---|
650 | .so () |
---|
651 | ); |
---|
652 | |
---|
653 | // added for timing |
---|
654 | assign tlu_lsu_int_ldxa_vld_w2 = |
---|
655 | tlu_asi_data_nf_vld_w2 & ~local_flush_all_w2; |
---|
656 | |
---|
657 | assign asr_hyperp = ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-1]; |
---|
658 | assign asr_priv = ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-2]; |
---|
659 | |
---|
660 | assign sraddr[`TLU_ASR_ADDR_WIDTH-3:0] = |
---|
661 | ifu_tlu_sraddr_d[`TLU_ASR_ADDR_WIDTH-3:0]; |
---|
662 | |
---|
663 | // hypervisor tick compare - 0x1f - hyper-priviledged |
---|
664 | assign htickcmp_rw_d = sraddr[4] & sraddr[3] & sraddr[2] & sraddr[1] & sraddr[0] & |
---|
665 | asr_hyperp; |
---|
666 | // |
---|
667 | // hypervisor processor state - 0x00 - hyper-priviledged |
---|
668 | assign hpstate_rw_d = ~sraddr[4] & ~sraddr[3] & ~sraddr[2] & ~sraddr[1] & ~sraddr[0] & |
---|
669 | asr_hyperp; |
---|
670 | // |
---|
671 | // hypervisor trap state - 0x01 - hyper-priviledged |
---|
672 | assign htstate_rw_d = ~sraddr[4] & ~sraddr[3] & ~sraddr[2] & ~sraddr[1] & sraddr[0] & |
---|
673 | asr_hyperp; |
---|
674 | |
---|
675 | assign tlu_htstate_rw_d = htstate_rw_d; |
---|
676 | // |
---|
677 | // hypervisor interrupt pending - 0x03 - hyper-priviledged |
---|
678 | assign hintp_rw_d = ~sraddr[4] & ~sraddr[3] & ~sraddr[2] & sraddr[1] & sraddr[0] & |
---|
679 | asr_hyperp; |
---|
680 | // |
---|
681 | // hypervisor trap base address - 0x05 - hyper-priviledged |
---|
682 | assign htba_rw_d = ~sraddr[4] & ~sraddr[3] & sraddr[2] & ~sraddr[1] & sraddr[0] & |
---|
683 | asr_hyperp; |
---|
684 | |
---|
685 | // global register - 0x10 - privileged |
---|
686 | assign gl_rw_d = sraddr[4] & ~sraddr[3] & ~sraddr[2] & ~sraddr[1] & ~sraddr[0] & |
---|
687 | asr_priv; |
---|
688 | // |
---|
689 | // staging of the ASR decoded controls |
---|
690 | // staging from d to e stage |
---|
691 | dff_s dff_htba_rw_d_e ( |
---|
692 | .din (htba_rw_d), |
---|
693 | .q (htba_rw_e), |
---|
694 | .clk (clk), |
---|
695 | .se (se), |
---|
696 | .si (), |
---|
697 | .so () |
---|
698 | ); |
---|
699 | |
---|
700 | dff_s dff_hpstate_rw_d_e ( |
---|
701 | .din (hpstate_rw_d), |
---|
702 | .q (hpstate_rw_e), |
---|
703 | .clk (clk), |
---|
704 | .se (se), |
---|
705 | .si (), |
---|
706 | .so () |
---|
707 | ); |
---|
708 | |
---|
709 | dff_s dff_htstate_rw_d_e ( |
---|
710 | .din (htstate_rw_d), |
---|
711 | .q (htstate_rw_e), |
---|
712 | .clk (clk), |
---|
713 | .se (se), |
---|
714 | .si (), |
---|
715 | .so () |
---|
716 | ); |
---|
717 | |
---|
718 | dff_s dff_hintp_rw_e ( |
---|
719 | .din (hintp_rw_d), |
---|
720 | .q (hintp_rw_e), |
---|
721 | .clk (clk), |
---|
722 | .se (se), |
---|
723 | .si (), |
---|
724 | .so () |
---|
725 | ); |
---|
726 | |
---|
727 | dff_s dff_htickcmp_rw_d_e ( |
---|
728 | .din (htickcmp_rw_d), |
---|
729 | .q (htickcmp_rw_e), |
---|
730 | .clk (clk), |
---|
731 | .se (se), |
---|
732 | .si (), |
---|
733 | .so () |
---|
734 | ); |
---|
735 | |
---|
736 | dff_s dff_gl_rw_d_e ( |
---|
737 | .din (gl_rw_d), |
---|
738 | .q (gl_rw_e), |
---|
739 | .clk (clk), |
---|
740 | .se (se), |
---|
741 | .si (), |
---|
742 | .so () |
---|
743 | ); |
---|
744 | |
---|
745 | // staging from e to m stage |
---|
746 | dff_s dff_htba_rw_m_m ( |
---|
747 | .din (htba_rw_e), |
---|
748 | .q (htba_rw_m), |
---|
749 | .clk (clk), |
---|
750 | .se (se), |
---|
751 | .si (), |
---|
752 | .so () |
---|
753 | ); |
---|
754 | |
---|
755 | dff_s dff_hpstate_rw_m_m ( |
---|
756 | .din (hpstate_rw_e), |
---|
757 | .q (hpstate_rw_m), |
---|
758 | .clk (clk), |
---|
759 | .se (se), |
---|
760 | .si (), |
---|
761 | .so () |
---|
762 | ); |
---|
763 | |
---|
764 | dff_s dff_htstate_rw_m_m ( |
---|
765 | .din (htstate_rw_e), |
---|
766 | .q (htstate_rw_m), |
---|
767 | .clk (clk), |
---|
768 | .se (se), |
---|
769 | .si (), |
---|
770 | .so () |
---|
771 | ); |
---|
772 | |
---|
773 | dff_s dff_hintp_rw_m_m ( |
---|
774 | .din (hintp_rw_e), |
---|
775 | .q (hintp_rw_m), |
---|
776 | .clk (clk), |
---|
777 | .se (se), |
---|
778 | .si (), |
---|
779 | .so () |
---|
780 | ); |
---|
781 | |
---|
782 | dff_s dff_htickcmp_rw_m_m ( |
---|
783 | .din (htickcmp_rw_e), |
---|
784 | .q (htickcmp_rw_m), |
---|
785 | .clk (clk), |
---|
786 | .se (se), |
---|
787 | .si (), |
---|
788 | .so () |
---|
789 | ); |
---|
790 | |
---|
791 | dff_s dff_gl_rw_m_m ( |
---|
792 | .din (gl_rw_e), |
---|
793 | .q (gl_rw_m), |
---|
794 | .clk (clk), |
---|
795 | .se (se), |
---|
796 | .si (), |
---|
797 | .so () |
---|
798 | ); |
---|
799 | |
---|
800 | // staging from e to g stage |
---|
801 | dff_s dff_gl_rw_m_g ( |
---|
802 | .din (gl_rw_m), |
---|
803 | .q (gl_rw_g), |
---|
804 | .clk (clk), |
---|
805 | .se (se), |
---|
806 | .si (), |
---|
807 | .so () |
---|
808 | ); |
---|
809 | |
---|
810 | dff_s dff_hpstate_rw_m_g ( |
---|
811 | .din (hpstate_rw_m), |
---|
812 | .q (hpstate_rw_g), |
---|
813 | .clk (clk), |
---|
814 | .se (se), |
---|
815 | .si (), |
---|
816 | .so () |
---|
817 | ); |
---|
818 | |
---|
819 | dff_s dff_htickcmp_rw_m_g ( |
---|
820 | .din (htickcmp_rw_m), |
---|
821 | .q (htickcmp_rw_g), |
---|
822 | .clk (clk), |
---|
823 | .se (se), |
---|
824 | .si (), |
---|
825 | .so () |
---|
826 | ); |
---|
827 | |
---|
828 | dff_s dff_htba_rw_m_g ( |
---|
829 | .din (htba_rw_m), |
---|
830 | .q (htba_rw_g), |
---|
831 | .clk (clk), |
---|
832 | .se (se), |
---|
833 | .si (), |
---|
834 | .so () |
---|
835 | ); |
---|
836 | |
---|
837 | dff_s dff_hintp_rw_g ( |
---|
838 | .din (hintp_rw_m), |
---|
839 | .q (hintp_rw_g), |
---|
840 | .clk (clk), |
---|
841 | .se (se), |
---|
842 | .si (), |
---|
843 | .so () |
---|
844 | ); |
---|
845 | |
---|
846 | dff_s dff_htstate_rw_m_g ( |
---|
847 | .din (htstate_rw_m), |
---|
848 | .q (htstate_rw_g), |
---|
849 | .clk (clk), |
---|
850 | .se (se), |
---|
851 | .si (), |
---|
852 | .so () |
---|
853 | ); |
---|
854 | // |
---|
855 | // stage to w2 |
---|
856 | dff_s dff_hpstate_rw_m_w2 ( |
---|
857 | .din (hpstate_rw_g), |
---|
858 | .q (hpstate_rw_w2), |
---|
859 | .clk (clk), |
---|
860 | .se (se), |
---|
861 | .si (), |
---|
862 | .so () |
---|
863 | ); |
---|
864 | |
---|
865 | // constructing the mux select to access the |
---|
866 | // hyper-privileged ASR registers |
---|
867 | // |
---|
868 | assign tlu_htickcmp_rw_e = htickcmp_rw_e; |
---|
869 | assign tlu_htstate_rw_g = htstate_rw_g; |
---|
870 | // |
---|
871 | // using htba_rw_e as one of the selects for rdpr read in tlu_tdp |
---|
872 | // assign tlu_htba_rsr_sel = htba_rw_e; |
---|
873 | // |
---|
874 | // construciton mux selects for tlu_rdpr_mx5 in tlu_tdp to read out |
---|
875 | // the ASR information |
---|
876 | // |
---|
877 | assign tlu_hyperv_rdpr_sel[0] = gl_rw_e; |
---|
878 | assign tlu_hyperv_rdpr_sel[1] = hintp_rw_e; |
---|
879 | assign tlu_hyperv_rdpr_sel[2] = hpstate_rw_e; |
---|
880 | assign tlu_hyperv_rdpr_sel[3] = htstate_rw_e; |
---|
881 | assign tlu_hyperv_rdpr_sel[4] = htba_rw_e; |
---|
882 | // assign tlu_rdpr_mx5_active = |(tlu_rdpr_mx5_sel[3:0]); |
---|
883 | // |
---|
884 | // buffer gl_rw_g for agp_tid_sel in tlu_tcl |
---|
885 | // modified for timing |
---|
886 | // assign tlu_gl_rw_g = gl_rw_g; |
---|
887 | assign tlu_gl_rw_m = gl_rw_m; |
---|
888 | |
---|
889 | //////////////////////////////////////////////////////////////////////// |
---|
890 | // GL register controls |
---|
891 | //////////////////////////////////////////////////////////////////////// |
---|
892 | |
---|
893 | dffr_s #(`TLU_THRD_NUM) dffr_gl_update_sel_w2 ( |
---|
894 | .din (gl_update_sel_g[`TLU_THRD_NUM-1:0]), |
---|
895 | .q (gl_update_sel_w2[`TLU_THRD_NUM-1:0]), |
---|
896 | .rst (local_rst), |
---|
897 | .clk (clk), |
---|
898 | .se (se), |
---|
899 | .si (), |
---|
900 | .so () |
---|
901 | ); |
---|
902 | |
---|
903 | dffr_s #(`TLU_THRD_NUM) dffr_dnrtry_inst_w2 ( |
---|
904 | .din ({tlu_dnrtry3_inst_g, tlu_dnrtry2_inst_g, |
---|
905 | tlu_dnrtry1_inst_g,tlu_dnrtry0_inst_g}), |
---|
906 | .q (dnrtry_inst_w2[`TLU_THRD_NUM-1:0]), |
---|
907 | .rst (local_rst), |
---|
908 | .clk (clk), |
---|
909 | .se (se), |
---|
910 | .si (), |
---|
911 | .so () |
---|
912 | ); |
---|
913 | // |
---|
914 | // added for timing |
---|
915 | assign wsr_inst_g = tlu_wsr_inst_nq_g & ~ifu_tlu_flush_fd_w; |
---|
916 | |
---|
917 | dffr_s dffr_wsr_inst_w2 ( |
---|
918 | .din (wsr_inst_g), |
---|
919 | .q (wsr_inst_w2), |
---|
920 | .rst (local_rst), |
---|
921 | .clk (clk), |
---|
922 | .se (se), |
---|
923 | .si (), |
---|
924 | .so () |
---|
925 | ); |
---|
926 | |
---|
927 | // THREAD0 |
---|
928 | |
---|
929 | assign gl_lvl0_at_maxgl = (gl_lvl0[`TSA_GLOBAL_WIDTH-1:0] == `MAXGL_GL); |
---|
930 | assign gl_lvl0_at_maxstl = (gl_lvl0[`TSA_GLOBAL_WIDTH-1:0] == `MAXSTL_GL); |
---|
931 | // |
---|
932 | // generate the control to prevent writing beyond maxstl or maxgl |
---|
933 | |
---|
934 | assign maxstl_gl_wr_sel[0] = |
---|
935 | ~tlu_hyper_lite[0] & |
---|
936 | (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > {1'b0,`MAXSTL}); |
---|
937 | assign maxstl_gl_wr_sel[1] = |
---|
938 | ~tlu_hyper_lite[1] & |
---|
939 | (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > {1'b0,`MAXSTL}); |
---|
940 | assign maxstl_gl_wr_sel[2] = |
---|
941 | ~tlu_hyper_lite[2] & |
---|
942 | (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > {1'b0,`MAXSTL}); |
---|
943 | assign maxstl_gl_wr_sel[3] = |
---|
944 | ~tlu_hyper_lite[3] & |
---|
945 | (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > {1'b0,`MAXSTL}); |
---|
946 | // |
---|
947 | // added for bug 79252 |
---|
948 | assign maxstl_gl_dnrtry_sel[0] = |
---|
949 | ~tlu_hyper_lite[0] & |
---|
950 | (&tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]); |
---|
951 | assign maxstl_gl_dnrtry_sel[1] = |
---|
952 | ~tlu_hyper_lite[1] & |
---|
953 | (&tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]); |
---|
954 | assign maxstl_gl_dnrtry_sel[2] = |
---|
955 | ~tlu_hyper_lite[2] & |
---|
956 | (&tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]); |
---|
957 | assign maxstl_gl_dnrtry_sel[3] = |
---|
958 | ~tlu_hyper_lite[3] & |
---|
959 | (&tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]); |
---|
960 | // |
---|
961 | // added for bug 79252 |
---|
962 | assign dnrtry_gl_lvl0_data[`TSA_GLOBAL_WIDTH-1:0] = |
---|
963 | (maxstl_gl_dnrtry_sel[0])? `MAXSTL_GL: |
---|
964 | tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]; |
---|
965 | assign dnrtry_gl_lvl1_data[`TSA_GLOBAL_WIDTH-1:0] = |
---|
966 | (maxstl_gl_dnrtry_sel[1])? `MAXSTL_GL: |
---|
967 | tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]; |
---|
968 | assign dnrtry_gl_lvl2_data[`TSA_GLOBAL_WIDTH-1:0] = |
---|
969 | (maxstl_gl_dnrtry_sel[2])? `MAXSTL_GL: |
---|
970 | tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]; |
---|
971 | assign dnrtry_gl_lvl3_data[`TSA_GLOBAL_WIDTH-1:0] = |
---|
972 | (maxstl_gl_dnrtry_sel[3])? `MAXSTL_GL: |
---|
973 | tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]; |
---|
974 | |
---|
975 | // |
---|
976 | // maxgl cap |
---|
977 | assign maxgl_gl_wr_sel[0] = |
---|
978 | tlu_hyper_lite[0] & |
---|
979 | (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > `MAXGL); |
---|
980 | assign maxgl_gl_wr_sel[1] = |
---|
981 | tlu_hyper_lite[1] & |
---|
982 | (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > `MAXGL); |
---|
983 | assign maxgl_gl_wr_sel[2] = |
---|
984 | tlu_hyper_lite[2] & |
---|
985 | (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > `MAXGL); |
---|
986 | assign maxgl_gl_wr_sel[3] = |
---|
987 | tlu_hyper_lite[3] & |
---|
988 | (tlu_wsr_data_w_global[`TLU_GLOBAL_WIDTH-1:0] > `MAXGL); |
---|
989 | // |
---|
990 | // trap level to be incremented if thread not at MAXGL and not in redmode |
---|
991 | // modified for bug 2889 |
---|
992 | // modified due to timing |
---|
993 | /* |
---|
994 | assign gl0_incr_sel = |
---|
995 | tlu_thrd0_traps & (~(gl_lvl0_at_maxgl | tlu_select_tba_g) | |
---|
996 | (~gl_lvl0_at_maxstl & tlu_select_tba_g)); |
---|
997 | |
---|
998 | assign gl_lvl0_incr[1:0] = {1'b0, gl0_incr_sel}; |
---|
999 | |
---|
1000 | assign gl0_en = (gl_rw_g & wsr_inst_g & thread_sel_id_g[0]) | |
---|
1001 | gl0_incr_sel | local_rst | por_rstint0_g | |
---|
1002 | tlu_dnrtry0_inst_g; |
---|
1003 | |
---|
1004 | assign gl_lvl0_new[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1005 | (gl_rw_g & wsr_inst_g & thread_sel_id_g[0]) ? |
---|
1006 | wsr_gl_lvl0_data[`TSA_GLOBAL_WIDTH-1:0] : |
---|
1007 | ((local_rst | por_rstint0_g) ? `MAXGL_GL : |
---|
1008 | ((tlu_dnrtry0_inst_g) ? |
---|
1009 | tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0] : // done/retry restore |
---|
1010 | gl_lvl0[`TSA_GLOBAL_WIDTH-1:0] + gl_lvl0_incr[1:0])); // trap increments |
---|
1011 | */ |
---|
1012 | // modified for bug 79252 |
---|
1013 | assign wsr_gl_lvl0_data[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1014 | (maxstl_gl_wr_sel[0])? `MAXSTL_GL: |
---|
1015 | ((maxgl_gl_wr_sel[0]) ? `MAXGL_GL : |
---|
1016 | tlu_wsr_data_w_global[`TSA_GLOBAL_WIDTH-1:0]); |
---|
1017 | assign gl_lvl0_update_g[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1018 | (gl_rw_g & wsr_inst_g & thread_sel_id_g[0]) ? |
---|
1019 | wsr_gl_lvl0_data[`TSA_GLOBAL_WIDTH-1:0] : |
---|
1020 | ((local_rst | por_rstint0_g) ? `MAXGL_GL : |
---|
1021 | dnrtry_gl_lvl0_data[`TSA_GLOBAL_WIDTH-1:0]); // done/retry restore |
---|
1022 | // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]); // done/retry restore |
---|
1023 | |
---|
1024 | dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl_lvl0_update_w2 ( |
---|
1025 | .din (gl_lvl0_update_g[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1026 | .q (gl_lvl0_update_w2[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1027 | .en (gl_update_sel_g[0]), |
---|
1028 | .clk (clk), |
---|
1029 | .se (se), |
---|
1030 | .si (), |
---|
1031 | .so () |
---|
1032 | ); |
---|
1033 | // |
---|
1034 | // modified for bug3468 and bug3505 |
---|
1035 | assign gl_incr_sel_w2[0] = |
---|
1036 | tlu_thrd_traps_w2[0] & ~(gl_lvl0_at_maxgl | |
---|
1037 | (gl_lvl0_at_maxstl & tlu_select_tba_w2)); |
---|
1038 | // tlu_thrd_traps_w2[0] & (~(gl_lvl0_at_maxgl | tlu_select_tba_w2) | |
---|
1039 | assign gl_update_sel_g[0] = |
---|
1040 | (gl_rw_g & wsr_inst_g & thread_sel_id_g[0]) | |
---|
1041 | local_rst | por_rstint0_g | tlu_dnrtry0_inst_g; |
---|
1042 | // |
---|
1043 | // modified for bug3468 |
---|
1044 | assign gl_priv_max_sel_w2[0] = |
---|
1045 | (gl_lvl0_at_maxgl & tlu_select_tba_w2) & tlu_thrd_traps_w2[0]; |
---|
1046 | assign gl0_en = |
---|
1047 | gl_incr_sel_w2[0] | gl_update_sel_w2[0] | gl_priv_max_sel_w2[0]; |
---|
1048 | // assign gl0_en = gl_incr_sel_w2[0] | gl_update_sel_w2[0]; |
---|
1049 | |
---|
1050 | assign gl_lvl0_new[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1051 | (gl_update_sel_w2[0]) ? gl_lvl0_update_w2: |
---|
1052 | (~gl_update_sel_w2[0] & gl_priv_max_sel_w2[0]) ? |
---|
1053 | `MAXSTL_GL: |
---|
1054 | gl_lvl0[`TSA_GLOBAL_WIDTH-1:0] + 2'b01; |
---|
1055 | |
---|
1056 | // Reset required as processor will start out at gl=1 after reset. |
---|
1057 | /**************************** |
---|
1058 | to fix bug 6028 manually in the gate netlist, the following needs |
---|
1059 | to be a mux_flop with recirculating path from q to d0 input. But |
---|
1060 | to make it resetable, need to brake this recirculating path and |
---|
1061 | insert an AND gate such that local_rst_l is ANDed with the q output. |
---|
1062 | |
---|
1063 | dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl0 ( |
---|
1064 | .din (gl_lvl0_new[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1065 | .q (gl_lvl0[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1066 | .en (gl0_en), |
---|
1067 | .clk (clk), |
---|
1068 | .se (se), |
---|
1069 | .si (), |
---|
1070 | .so () |
---|
1071 | ); |
---|
1072 | ******************************/ |
---|
1073 | |
---|
1074 | wire [1:0] gl_lvl0_or_rst, gl_lvl0_or_rst_or_new; |
---|
1075 | |
---|
1076 | assign gl_lvl0_or_rst[1:0] = gl_lvl0[1:0] & {2{~local_rst}}; |
---|
1077 | |
---|
1078 | assign gl_lvl0_or_rst_or_new[1:0] = (gl0_en&~local_rst) ? gl_lvl0_new[1:0] : gl_lvl0_or_rst[1:0]; |
---|
1079 | |
---|
1080 | dff_s #(2) dffe_gl0 ( |
---|
1081 | .din(gl_lvl0_or_rst_or_new[1:0]) , |
---|
1082 | .q(gl_lvl0[1:0]), |
---|
1083 | .clk (clk), .se(se), .si(), .so()); |
---|
1084 | |
---|
1085 | /******************************/ |
---|
1086 | |
---|
1087 | |
---|
1088 | assign tlu_gl_lvl0[`TSA_GLOBAL_WIDTH-1:0] = gl_lvl0[`TSA_GLOBAL_WIDTH-1:0]; |
---|
1089 | |
---|
1090 | `ifdef FPGA_SYN_1THREAD |
---|
1091 | `else |
---|
1092 | |
---|
1093 | // THREAD1 |
---|
1094 | |
---|
1095 | assign gl_lvl1_at_maxgl = (gl_lvl1[`TSA_GLOBAL_WIDTH-1:0] == `MAXGL_GL); |
---|
1096 | assign gl_lvl1_at_maxstl = (gl_lvl1[`TSA_GLOBAL_WIDTH-1:0] == `MAXSTL_GL); |
---|
1097 | // |
---|
1098 | // trap level to be incremented if thread not at MAXGL and not in redmode |
---|
1099 | // modified for bug 2889 |
---|
1100 | // modified due to timing |
---|
1101 | /* |
---|
1102 | assign gl1_incr_sel = |
---|
1103 | tlu_thrd1_traps & (~(gl_lvl1_at_maxgl | tlu_select_tba_g) | |
---|
1104 | (~gl_lvl1_at_maxstl & tlu_select_tba_g)); |
---|
1105 | |
---|
1106 | assign gl_lvl1_incr[1:0] = {1'b0, gl1_incr_sel}; |
---|
1107 | |
---|
1108 | assign gl1_en = (gl_rw_g & wsr_inst_g & thread_sel_id_g[1]) | |
---|
1109 | gl1_incr_sel | local_rst | por_rstint1_g | |
---|
1110 | tlu_dnrtry1_inst_g; |
---|
1111 | |
---|
1112 | assign gl_lvl1_new[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1113 | (gl_rw_g & wsr_inst_g & thread_sel_id_g[1])? |
---|
1114 | wsr_gl_lvl1_data[`TSA_GLOBAL_WIDTH-1:0] : |
---|
1115 | ((local_rst | por_rstint1_g) ? `MAXGL_GL : |
---|
1116 | ((tlu_dnrtry1_inst_g) ? |
---|
1117 | dnrtry_gl_lvl1_data[`TSA_GLOBAL_WIDTH-1:0] : // done/retry restore |
---|
1118 | // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0] : // done/retry restore |
---|
1119 | gl_lvl1[`TSA_GLOBAL_WIDTH-1:0] + gl_lvl1_incr[1:0])); // trap increments |
---|
1120 | |
---|
1121 | */ |
---|
1122 | assign wsr_gl_lvl1_data[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1123 | (maxstl_gl_wr_sel[1])? `MAXSTL_GL: |
---|
1124 | ((maxgl_gl_wr_sel[1]) ? `MAXGL_GL : |
---|
1125 | tlu_wsr_data_w_global[`TSA_GLOBAL_WIDTH-1:0]); |
---|
1126 | assign gl_lvl1_update_g[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1127 | (gl_rw_g & wsr_inst_g & thread_sel_id_g[1]) ? |
---|
1128 | wsr_gl_lvl1_data[`TSA_GLOBAL_WIDTH-1:0] : |
---|
1129 | ((local_rst | por_rstint1_g) ? `MAXGL_GL : |
---|
1130 | dnrtry_gl_lvl1_data[`TSA_GLOBAL_WIDTH-1:0]); // done/retry restore |
---|
1131 | // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]); // done/retry restore |
---|
1132 | |
---|
1133 | dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl_lvl1_update_w2 ( |
---|
1134 | .din (gl_lvl1_update_g[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1135 | .q (gl_lvl1_update_w2[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1136 | .en (gl_update_sel_g[1]), |
---|
1137 | .clk (clk), |
---|
1138 | .se (se), |
---|
1139 | .si (), |
---|
1140 | .so () |
---|
1141 | ); |
---|
1142 | // |
---|
1143 | // modified for bug3468 and bug3505 |
---|
1144 | assign gl_incr_sel_w2[1] = |
---|
1145 | tlu_thrd_traps_w2[1] & ~(gl_lvl1_at_maxgl | |
---|
1146 | (gl_lvl1_at_maxstl & tlu_select_tba_w2)); |
---|
1147 | // tlu_thrd_traps_w2[1] & (~(gl_lvl1_at_maxgl | tlu_select_tba_w2) | |
---|
1148 | assign gl_update_sel_g[1] = |
---|
1149 | (gl_rw_g & wsr_inst_g & thread_sel_id_g[1]) | |
---|
1150 | local_rst | por_rstint1_g | tlu_dnrtry1_inst_g; |
---|
1151 | // |
---|
1152 | // modified for bug3468 |
---|
1153 | assign gl_priv_max_sel_w2[1] = |
---|
1154 | (gl_lvl1_at_maxgl & tlu_select_tba_w2) & tlu_thrd_traps_w2[1]; |
---|
1155 | // |
---|
1156 | assign gl1_en = |
---|
1157 | gl_incr_sel_w2[1] | gl_update_sel_w2[1] | gl_priv_max_sel_w2[1]; |
---|
1158 | // assign gl1_en = gl_incr_sel_w2[1] | gl_update_sel_w2[1]; |
---|
1159 | |
---|
1160 | assign gl_lvl1_new[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1161 | (gl_update_sel_w2[1]) ? gl_lvl1_update_w2: |
---|
1162 | (~gl_update_sel_w2[1] & gl_priv_max_sel_w2[1]) ? |
---|
1163 | `MAXSTL_GL: |
---|
1164 | gl_lvl1[`TSA_GLOBAL_WIDTH-1:0] + 2'b01; |
---|
1165 | |
---|
1166 | // Reset required as processor will start out at gl=1 after reset. |
---|
1167 | /**************************** |
---|
1168 | to fix bug 6028 manually in the gate netlist, the following needs |
---|
1169 | to be a mux_flop with recirculating path from q to d0 input. But |
---|
1170 | to make it resetable, need to brake this recirculating path and |
---|
1171 | insert an AND gate such that local_rst_l is ANDed with the q output. |
---|
1172 | dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl1 ( |
---|
1173 | .din (gl_lvl1_new[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1174 | .q (gl_lvl1[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1175 | .en (gl1_en), |
---|
1176 | .clk (clk), |
---|
1177 | .se (se), |
---|
1178 | .si (), |
---|
1179 | .so () |
---|
1180 | ); |
---|
1181 | ******************************/ |
---|
1182 | |
---|
1183 | wire [1:0] gl_lvl1_or_rst, gl_lvl1_or_rst_or_new; |
---|
1184 | |
---|
1185 | assign gl_lvl1_or_rst[1:0] = gl_lvl1[1:0] & {2{~local_rst}}; |
---|
1186 | |
---|
1187 | assign gl_lvl1_or_rst_or_new[1:0] = (gl1_en&~local_rst) ? gl_lvl1_new[1:0] : gl_lvl1_or_rst[1:0]; |
---|
1188 | |
---|
1189 | dff_s #(2) dffe_gl1 ( |
---|
1190 | .din(gl_lvl1_or_rst_or_new[1:0]) , |
---|
1191 | .q(gl_lvl1[1:0]), |
---|
1192 | .clk (clk), .se(se), .si(), .so()); |
---|
1193 | |
---|
1194 | /******************************/ |
---|
1195 | |
---|
1196 | |
---|
1197 | assign tlu_gl_lvl1[`TSA_GLOBAL_WIDTH-1:0] = gl_lvl1[`TSA_GLOBAL_WIDTH-1:0]; |
---|
1198 | |
---|
1199 | // THREAD2 |
---|
1200 | |
---|
1201 | assign gl_lvl2_at_maxgl = (gl_lvl2[`TSA_GLOBAL_WIDTH-1:0] == `MAXGL_GL); |
---|
1202 | assign gl_lvl2_at_maxstl = (gl_lvl2[`TSA_GLOBAL_WIDTH-1:0] == `MAXSTL_GL); |
---|
1203 | // |
---|
1204 | // trap level to be incremented if thread not at MAXGL and not in redmode |
---|
1205 | // modified for bug 2889 |
---|
1206 | // modified due to timing |
---|
1207 | /* |
---|
1208 | assign gl2_incr_sel = |
---|
1209 | tlu_thrd2_traps & (~(gl_lvl2_at_maxgl | tlu_select_tba_g) | |
---|
1210 | (~gl_lvl2_at_maxstl & tlu_select_tba_g)); |
---|
1211 | |
---|
1212 | assign gl_lvl2_incr[1:0] = {1'b0, gl2_incr_sel}; |
---|
1213 | |
---|
1214 | assign gl2_en = (gl_rw_g & wsr_inst_g & thread_sel_id_g[2]) | |
---|
1215 | gl2_incr_sel | local_rst | por_rstint2_g | |
---|
1216 | tlu_dnrtry2_inst_g; |
---|
1217 | |
---|
1218 | assign gl_lvl2_new[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1219 | (gl_rw_g & wsr_inst_g & thread_sel_id_g[2])? |
---|
1220 | wsr_gl_lvl2_data[`TSA_GLOBAL_WIDTH-1:0] : |
---|
1221 | ((local_rst | por_rstint2_g) ? `MAXGL_GL : |
---|
1222 | ((tlu_dnrtry2_inst_g) ? |
---|
1223 | tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0] : // done/retry restore |
---|
1224 | gl_lvl2[`TSA_GLOBAL_WIDTH-1:0] + gl_lvl2_incr[1:0])); // trap increments |
---|
1225 | */ |
---|
1226 | assign wsr_gl_lvl2_data[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1227 | (maxstl_gl_wr_sel[2])? `MAXSTL_GL: |
---|
1228 | ((maxgl_gl_wr_sel[2]) ? `MAXGL_GL : |
---|
1229 | tlu_wsr_data_w_global[`TSA_GLOBAL_WIDTH-1:0]); |
---|
1230 | assign gl_lvl2_update_g[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1231 | (gl_rw_g & wsr_inst_g & thread_sel_id_g[2]) ? |
---|
1232 | wsr_gl_lvl2_data[`TSA_GLOBAL_WIDTH-1:0] : |
---|
1233 | ((local_rst | por_rstint2_g) ? `MAXGL_GL : |
---|
1234 | dnrtry_gl_lvl2_data[`TSA_GLOBAL_WIDTH-1:0]); // done/retry restore |
---|
1235 | // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]); // done/retry restore |
---|
1236 | |
---|
1237 | dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl_lvl2_update_w2 ( |
---|
1238 | .din (gl_lvl2_update_g[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1239 | .q (gl_lvl2_update_w2[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1240 | .en (gl_update_sel_g[2]), |
---|
1241 | .clk (clk), |
---|
1242 | .se (se), |
---|
1243 | .si (), |
---|
1244 | .so () |
---|
1245 | ); |
---|
1246 | // |
---|
1247 | // modified for bug3468 and bug3505 |
---|
1248 | assign gl_incr_sel_w2[2] = |
---|
1249 | tlu_thrd_traps_w2[2] & ~(gl_lvl2_at_maxgl | |
---|
1250 | (gl_lvl2_at_maxstl & tlu_select_tba_w2)); |
---|
1251 | // tlu_thrd_traps_w2[2] & (~(gl_lvl2_at_maxgl | tlu_select_tba_w2) | |
---|
1252 | assign gl_update_sel_g[2] = |
---|
1253 | (gl_rw_g & wsr_inst_g & thread_sel_id_g[2]) | |
---|
1254 | local_rst | por_rstint2_g | tlu_dnrtry2_inst_g; |
---|
1255 | // |
---|
1256 | // modified for bug3468 |
---|
1257 | assign gl_priv_max_sel_w2[2] = |
---|
1258 | (gl_lvl2_at_maxgl & tlu_select_tba_w2) & tlu_thrd_traps_w2[2]; |
---|
1259 | // |
---|
1260 | assign gl2_en = |
---|
1261 | gl_incr_sel_w2[2] | gl_update_sel_w2[2] | gl_priv_max_sel_w2[2]; |
---|
1262 | // assign gl2_en = gl_incr_sel_w2[2] | gl_update_sel_w2[2]; |
---|
1263 | |
---|
1264 | assign gl_lvl2_new[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1265 | (gl_update_sel_w2[2]) ? gl_lvl2_update_w2: |
---|
1266 | (~gl_update_sel_w2[2] & gl_priv_max_sel_w2[2]) ? |
---|
1267 | `MAXSTL_GL: |
---|
1268 | gl_lvl2[`TSA_GLOBAL_WIDTH-1:0] + 2'b01; |
---|
1269 | |
---|
1270 | // Reset required as processor will start out at gl=1 after reset. |
---|
1271 | /**************************** |
---|
1272 | to fix bug 6028 manually in the gate netlist, the following needs |
---|
1273 | to be a mux_flop with recirculating path from q to d0 input. But |
---|
1274 | to make it resetable, need to brake this recirculating path and |
---|
1275 | insert an AND gate such that local_rst_l is ANDed with the q output. |
---|
1276 | dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl2 ( |
---|
1277 | .din (gl_lvl2_new[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1278 | .q (gl_lvl2[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1279 | .en (gl2_en), |
---|
1280 | .clk (clk), |
---|
1281 | .se (se), |
---|
1282 | .si (), |
---|
1283 | .so () |
---|
1284 | ); |
---|
1285 | ******************************/ |
---|
1286 | |
---|
1287 | wire [1:0] gl_lvl2_or_rst, gl_lvl2_or_rst_or_new; |
---|
1288 | |
---|
1289 | assign gl_lvl2_or_rst[1:0] = gl_lvl2[1:0] & {2{~local_rst}}; |
---|
1290 | |
---|
1291 | assign gl_lvl2_or_rst_or_new[1:0] = (gl2_en&~local_rst) ? gl_lvl2_new[1:0] : gl_lvl2_or_rst[1:0]; |
---|
1292 | |
---|
1293 | dff_s #(2) dffe_gl2 ( |
---|
1294 | .din(gl_lvl2_or_rst_or_new[1:0]) , |
---|
1295 | .q(gl_lvl2[1:0]), |
---|
1296 | .clk (clk), .se(se), .si(), .so()); |
---|
1297 | |
---|
1298 | /******************************/ |
---|
1299 | |
---|
1300 | assign tlu_gl_lvl2[`TSA_GLOBAL_WIDTH-1:0] = gl_lvl2[`TSA_GLOBAL_WIDTH-1:0]; |
---|
1301 | |
---|
1302 | // THREAD3 |
---|
1303 | |
---|
1304 | assign gl_lvl3_at_maxgl = (gl_lvl3[`TSA_GLOBAL_WIDTH-1:0] == `MAXGL_GL); |
---|
1305 | assign gl_lvl3_at_maxstl = (gl_lvl3[`TSA_GLOBAL_WIDTH-1:0] == `MAXSTL_GL); |
---|
1306 | // |
---|
1307 | // trap level to be incremented if thread not at MAXGL and not in redmode |
---|
1308 | // modified for bug 2889 |
---|
1309 | // modified due to timing |
---|
1310 | /* |
---|
1311 | assign gl3_incr_sel = |
---|
1312 | tlu_thrd3_traps & (~(gl_lvl3_at_maxgl | tlu_select_tba_g) | |
---|
1313 | (~gl_lvl3_at_maxstl & tlu_select_tba_g)); |
---|
1314 | |
---|
1315 | assign gl_lvl3_incr = {1'b0, gl3_incr_sel}; |
---|
1316 | |
---|
1317 | assign gl3_en = (gl_rw_g & wsr_inst_g & thread_sel_id_g[3]) | |
---|
1318 | gl3_incr_sel | local_rst | por_rstint3_g | |
---|
1319 | tlu_dnrtry3_inst_g; |
---|
1320 | |
---|
1321 | assign gl_lvl3_new[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1322 | (gl_rw_g & wsr_inst_g & thread_sel_id_g[3])? |
---|
1323 | wsr_gl_lvl3_data[`TSA_GLOBAL_WIDTH-1:0] : |
---|
1324 | ((local_rst | por_rstint3_g) ? `MAXGL_GL : |
---|
1325 | ((tlu_dnrtry3_inst_g) ? |
---|
1326 | tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0] : // done/retry restore |
---|
1327 | gl_lvl3[`TSA_GLOBAL_WIDTH-1:0] + gl_lvl3_incr[1:0])); // trap increments |
---|
1328 | */ |
---|
1329 | assign wsr_gl_lvl3_data[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1330 | (maxstl_gl_wr_sel[3])? `MAXSTL_GL: |
---|
1331 | ((maxgl_gl_wr_sel[3]) ? `MAXGL_GL : |
---|
1332 | tlu_wsr_data_w_global[`TSA_GLOBAL_WIDTH-1:0]); |
---|
1333 | assign gl_lvl3_update_g[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1334 | (gl_rw_g & wsr_inst_g & thread_sel_id_g[3]) ? |
---|
1335 | wsr_gl_lvl3_data[`TSA_GLOBAL_WIDTH-1:0] : |
---|
1336 | ((local_rst | por_rstint3_g) ? `MAXGL_GL : |
---|
1337 | dnrtry_gl_lvl3_data[`TSA_GLOBAL_WIDTH-1:0]); // done/retry restore |
---|
1338 | // tlu_dnrtry_global_g[`TSA_GLOBAL_WIDTH-1:0]); // done/retry restore |
---|
1339 | |
---|
1340 | dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl_lvl3_update_w2 ( |
---|
1341 | .din (gl_lvl3_update_g[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1342 | .q (gl_lvl3_update_w2[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1343 | .en (gl_update_sel_g[3]), |
---|
1344 | .clk (clk), |
---|
1345 | .se (se), |
---|
1346 | .si (), |
---|
1347 | .so () |
---|
1348 | ); |
---|
1349 | // |
---|
1350 | // modified for bug3468 |
---|
1351 | assign gl_incr_sel_w2[3] = |
---|
1352 | tlu_thrd_traps_w2[3] & ~(gl_lvl3_at_maxgl | |
---|
1353 | (gl_lvl3_at_maxstl & tlu_select_tba_w2)); |
---|
1354 | // tlu_thrd_traps_w2[3] & (~(gl_lvl3_at_maxgl | tlu_select_tba_w2) | |
---|
1355 | assign gl_update_sel_g[3] = |
---|
1356 | (gl_rw_g & wsr_inst_g & thread_sel_id_g[3]) | |
---|
1357 | local_rst | por_rstint3_g | tlu_dnrtry3_inst_g; |
---|
1358 | // |
---|
1359 | // modified for bug3468 |
---|
1360 | assign gl_priv_max_sel_w2[3] = |
---|
1361 | (gl_lvl3_at_maxgl & tlu_select_tba_w2) & tlu_thrd_traps_w2[3]; |
---|
1362 | // |
---|
1363 | assign gl3_en = |
---|
1364 | gl_incr_sel_w2[3] | gl_update_sel_w2[3] | gl_priv_max_sel_w2[3]; |
---|
1365 | // assign gl3_en = gl_incr_sel_w2[3] | gl_update_sel_w2[3]; |
---|
1366 | |
---|
1367 | assign gl_lvl3_new[`TSA_GLOBAL_WIDTH-1:0] = |
---|
1368 | (gl_update_sel_w2[3]) ? gl_lvl3_update_w2: |
---|
1369 | (~gl_update_sel_w2[3] & gl_priv_max_sel_w2[3]) ? |
---|
1370 | `MAXSTL_GL: |
---|
1371 | gl_lvl3[`TSA_GLOBAL_WIDTH-1:0] + 2'b01; |
---|
1372 | |
---|
1373 | // Reset required as processor will start out at gl1 after reset. |
---|
1374 | /**************************** |
---|
1375 | to fix bug 6028 manually in the gate netlist, the following needs |
---|
1376 | to be a mux_flop with recirculating path from q to d0 input. But |
---|
1377 | to make it resetable, need to brake this recirculating path and |
---|
1378 | insert an AND gate such that local_rst_l is ANDed with the q output. |
---|
1379 | dffe_s #(`TSA_GLOBAL_WIDTH) dffe_gl3 ( |
---|
1380 | .din (gl_lvl3_new[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1381 | .q (gl_lvl3[`TSA_GLOBAL_WIDTH-1:0]), |
---|
1382 | .en (gl3_en), |
---|
1383 | .clk (clk), |
---|
1384 | .se (se), |
---|
1385 | .si (), |
---|
1386 | .so () |
---|
1387 | ); |
---|
1388 | ******************************/ |
---|
1389 | |
---|
1390 | wire [1:0] gl_lvl3_or_rst, gl_lvl3_or_rst_or_new; |
---|
1391 | |
---|
1392 | assign gl_lvl3_or_rst[1:0] = gl_lvl3[1:0] & {2{~local_rst}}; |
---|
1393 | |
---|
1394 | assign gl_lvl3_or_rst_or_new[1:0] = (gl3_en&~local_rst) ? gl_lvl3_new[1:0] : gl_lvl3_or_rst[1:0]; |
---|
1395 | |
---|
1396 | dff_s #(2) dffe_gl3 ( |
---|
1397 | .din(gl_lvl3_or_rst_or_new[1:0]) , |
---|
1398 | .q(gl_lvl3[1:0]), |
---|
1399 | .clk (clk), .se(se), .si(), .so()); |
---|
1400 | |
---|
1401 | /******************************/ |
---|
1402 | |
---|
1403 | assign tlu_gl_lvl3[`TSA_GLOBAL_WIDTH-1:0] = gl_lvl3[`TSA_GLOBAL_WIDTH-1:0]; |
---|
1404 | |
---|
1405 | `endif // !`ifdef FPGA_SYN_1THREAD |
---|
1406 | |
---|
1407 | //////////////////////////////////////////////////////////////////////// |
---|
1408 | // Global swap |
---|
1409 | //////////////////////////////////////////////////////////////////////// |
---|
1410 | // modified due to timing |
---|
1411 | /* |
---|
1412 | assign agp_thrid[0] = ~tlu_agp_tid_g[0] & ~tlu_agp_tid_g[1] & gl0_en; |
---|
1413 | assign agp_thrid[1] = tlu_agp_tid_g[0] & ~tlu_agp_tid_g[1] & gl1_en; |
---|
1414 | assign agp_thrid[2] = ~tlu_agp_tid_g[0] & tlu_agp_tid_g[1] & gl2_en; |
---|
1415 | assign agp_thrid[3] = tlu_agp_tid_g[0] & tlu_agp_tid_g[1] & gl3_en; |
---|
1416 | |
---|
1417 | assign agp_swap = |
---|
1418 | (agp_thrid[0])? |
---|
1419 | |(gl_lvl0_new[1:0] ^ gl_lvl0[1:0]): |
---|
1420 | ((agp_thrid[1])? |
---|
1421 | |(gl_lvl1_new[1:0] ^ gl_lvl1[1:0]): |
---|
1422 | ((agp_thrid[2])? |
---|
1423 | |(gl_lvl2_new[1:0] ^ gl_lvl2[1:0]): |
---|
1424 | ((agp_thrid[3])? |
---|
1425 | |(gl_lvl3_new[1:0] ^ gl_lvl3[1:0]):1'b0))); |
---|
1426 | |
---|
1427 | assign agp_new[1:0] = |
---|
1428 | (agp_thrid[1])? gl_lvl1_new[1:0] : |
---|
1429 | ((agp_thrid[2])? gl_lvl2_new[1:0] : |
---|
1430 | ((agp_thrid[3])? gl_lvl3_new[1:0] : |
---|
1431 | gl_lvl0_new[1:0])); |
---|
1432 | |
---|
1433 | dffr_s dffr_tlu_exu_agp_swap ( |
---|
1434 | .din (agp_swap), |
---|
1435 | .q (tlu_exu_agp_swap), |
---|
1436 | .clk (clk), |
---|
1437 | .rst (local_rst), |
---|
1438 | .se (se), |
---|
1439 | .si (), |
---|
1440 | .so () |
---|
1441 | ); |
---|
1442 | |
---|
1443 | dff_s #(2) dff_tlu_exu_agp ( |
---|
1444 | .din (agp_new[1:0]), |
---|
1445 | .q (tlu_exu_agp[1:0]), |
---|
1446 | .clk (clk), |
---|
1447 | .se (se), |
---|
1448 | .si (), |
---|
1449 | .so () |
---|
1450 | ); |
---|
1451 | |
---|
1452 | dff_s #(2) dff_tlu_exu_agp_tid ( |
---|
1453 | .din (tlu_agp_tid_g[1:0]), |
---|
1454 | .q (tlu_exu_agp_tid[1:0]), |
---|
1455 | .clk (clk), |
---|
1456 | .se (se), |
---|
1457 | .si (), |
---|
1458 | .so () |
---|
1459 | ); |
---|
1460 | */ |
---|
1461 | |
---|
1462 | assign agp_thrid_w2[0] = ~tlu_agp_tid_w2[0] & ~tlu_agp_tid_w2[1] & gl0_en; |
---|
1463 | |
---|
1464 | `ifdef FPGA_SYN_1THREAD |
---|
1465 | assign agp_thrid_w2[1] = 1'b0; |
---|
1466 | assign agp_thrid_w2[2] = 1'b0; |
---|
1467 | assign agp_thrid_w2[3] = 1'b0; |
---|
1468 | assign agp_swap_w2 = (agp_thrid_w2[0])? |
---|
1469 | |(gl_lvl0_new[1:0] ^ gl_lvl0[1:0]):1'b0; |
---|
1470 | dffr_s dffr_agp_swap_w3 ( |
---|
1471 | .din (agp_swap_w2), |
---|
1472 | .q (agp_swap_w3), |
---|
1473 | .rst (local_rst), |
---|
1474 | .clk (clk), |
---|
1475 | .se (se), |
---|
1476 | .si (), |
---|
1477 | .so () |
---|
1478 | ); |
---|
1479 | |
---|
1480 | assign agp_new_w2[1:0] = gl_lvl0_new[1:0]; |
---|
1481 | |
---|
1482 | `else |
---|
1483 | |
---|
1484 | assign agp_thrid_w2[1] = tlu_agp_tid_w2[0] & ~tlu_agp_tid_w2[1] & gl1_en; |
---|
1485 | assign agp_thrid_w2[2] = ~tlu_agp_tid_w2[0] & tlu_agp_tid_w2[1] & gl2_en; |
---|
1486 | assign agp_thrid_w2[3] = tlu_agp_tid_w2[0] & tlu_agp_tid_w2[1] & gl3_en; |
---|
1487 | |
---|
1488 | assign agp_swap_w2 = |
---|
1489 | (agp_thrid_w2[0])? |
---|
1490 | |(gl_lvl0_new[1:0] ^ gl_lvl0[1:0]): |
---|
1491 | ((agp_thrid_w2[1])? |
---|
1492 | |(gl_lvl1_new[1:0] ^ gl_lvl1[1:0]): |
---|
1493 | ((agp_thrid_w2[2])? |
---|
1494 | |(gl_lvl2_new[1:0] ^ gl_lvl2[1:0]): |
---|
1495 | ((agp_thrid_w2[3])? |
---|
1496 | |(gl_lvl3_new[1:0] ^ gl_lvl3[1:0]):1'b0))); |
---|
1497 | |
---|
1498 | dffr_s dffr_agp_swap_w3 ( |
---|
1499 | .din (agp_swap_w2), |
---|
1500 | .q (agp_swap_w3), |
---|
1501 | .rst (local_rst), |
---|
1502 | .clk (clk), |
---|
1503 | .se (se), |
---|
1504 | .si (), |
---|
1505 | .so () |
---|
1506 | ); |
---|
1507 | |
---|
1508 | assign agp_new_w2[1:0] = |
---|
1509 | (agp_thrid_w2[1])? gl_lvl1_new[1:0] : |
---|
1510 | ((agp_thrid_w2[2])? gl_lvl2_new[1:0] : |
---|
1511 | ((agp_thrid_w2[3])? gl_lvl3_new[1:0] : |
---|
1512 | gl_lvl0_new[1:0])); |
---|
1513 | `endif // !`ifdef FPGA_SYN_1THREAD |
---|
1514 | |
---|
1515 | // |
---|
1516 | // added for timing fixes |
---|
1517 | dff_s #(2) dff_agp_new_w3 ( |
---|
1518 | .din (agp_new_w2[1:0]), |
---|
1519 | .q (agp_new_w3[1:0]), |
---|
1520 | .clk (clk), |
---|
1521 | .se (se), |
---|
1522 | .si (), |
---|
1523 | .so () |
---|
1524 | ); |
---|
1525 | assign tlu_exu_agp_swap = agp_swap_w3; |
---|
1526 | assign tlu_exu_agp[1:0] = agp_new_w3[1:0]; |
---|
1527 | |
---|
1528 | //////////////////////////////////////////////////////////////////////// |
---|
1529 | // HPSTATE register controls |
---|
1530 | //////////////////////////////////////////////////////////////////////// |
---|
1531 | // |
---|
1532 | // added for timing |
---|
1533 | dffr_s #(`TLU_THRD_NUM) dffr_update_hpstate_w2 ( |
---|
1534 | .din (update_hpstate_g[`TLU_THRD_NUM-1:0]), |
---|
1535 | .q (update_hpstate_w2[`TLU_THRD_NUM-1:0]), |
---|
1536 | .rst (local_rst), |
---|
1537 | .clk (clk), |
---|
1538 | .se (se), |
---|
1539 | .si (), |
---|
1540 | .so () |
---|
1541 | ); |
---|
1542 | |
---|
1543 | // thread 0 |
---|
1544 | assign tlu_hpstate_din_sel0[0] = dnrtry_inst_w2[0] & ~rst_tri_en; |
---|
1545 | assign tlu_hpstate_din_sel0[1] = (hpstate_rw_w2 & wsr_inst_w2) & |
---|
1546 | ~rst_tri_en & |
---|
1547 | ~tlu_hpstate_din_sel0[0] & |
---|
1548 | thread_sel_id_w2[0]; |
---|
1549 | // |
---|
1550 | // generating write enables to update the hpstate registers |
---|
1551 | // modified for timing |
---|
1552 | /* |
---|
1553 | assign tlu_hpstate_din_sel0[0] = tlu_dnrtry0_inst_g; |
---|
1554 | assign tlu_hpstate_din_sel0[1] = (hpstate_rw_g & wsr_inst_g) & |
---|
1555 | ~tlu_hpstate_din_sel0[0] & |
---|
1556 | thread_sel_id_g[0]; |
---|
1557 | assign update_hpstate0_g = tlu_thrd0_traps | tlu_dnrtry0_inst_g | |
---|
1558 | ((hpstate_rw_g & wsr_inst_g) & |
---|
1559 | thread_sel_id_g[0]); |
---|
1560 | |
---|
1561 | assign tlu_update_hpstate_l_g[0] = ~(update_hpstate0_g | local_rst); |
---|
1562 | */ |
---|
1563 | assign update_hpstate_g[0] = |
---|
1564 | tlu_dnrtry0_inst_g | ((hpstate_rw_g & wsr_inst_g) & |
---|
1565 | thread_sel_id_g[0]); |
---|
1566 | |
---|
1567 | assign tlu_update_hpstate_l_w2[0] = |
---|
1568 | ~(update_hpstate_w2[0] | local_rst | tlu_thrd_traps_w2[0]); |
---|
1569 | // |
---|
1570 | // thread 1 |
---|
1571 | assign tlu_hpstate_din_sel1[0] = dnrtry_inst_w2[1] & ~rst_tri_en; |
---|
1572 | assign tlu_hpstate_din_sel1[1] = (hpstate_rw_w2 & wsr_inst_w2) & |
---|
1573 | ~rst_tri_en & |
---|
1574 | ~tlu_hpstate_din_sel1[0] & |
---|
1575 | thread_sel_id_w2[1]; |
---|
1576 | // |
---|
1577 | // generating write enables to update the hpstate registers |
---|
1578 | // modified for timing |
---|
1579 | /* |
---|
1580 | assign tlu_hpstate_din_sel1[0] = tlu_dnrtry1_inst_g; |
---|
1581 | assign tlu_hpstate_din_sel1[1] = (hpstate_rw_g & wsr_inst_g) & |
---|
1582 | ~tlu_hpstate_din_sel1[0] & |
---|
1583 | thread_sel_id_g[1]; |
---|
1584 | assign update_hpstate1_g = tlu_thrd1_traps | tlu_dnrtry1_inst_g | |
---|
1585 | ((hpstate_rw_g & wsr_inst_g) & |
---|
1586 | thread_sel_id_g[1]); |
---|
1587 | |
---|
1588 | assign tlu_update_hpstate_l_g[1] = ~(update_hpstate1_g | local_rst); |
---|
1589 | */ |
---|
1590 | assign update_hpstate_g[1] = |
---|
1591 | tlu_dnrtry1_inst_g | ((hpstate_rw_g & wsr_inst_g) & |
---|
1592 | thread_sel_id_g[1]); |
---|
1593 | |
---|
1594 | assign tlu_update_hpstate_l_w2[1] = |
---|
1595 | ~(update_hpstate_w2[1] | local_rst | tlu_thrd_traps_w2[1]); |
---|
1596 | // |
---|
1597 | // thread 2 |
---|
1598 | assign tlu_hpstate_din_sel2[0] = dnrtry_inst_w2[2] & ~rst_tri_en; |
---|
1599 | assign tlu_hpstate_din_sel2[1] = (hpstate_rw_w2 & wsr_inst_w2) & |
---|
1600 | ~rst_tri_en & |
---|
1601 | ~tlu_hpstate_din_sel2[0] & |
---|
1602 | thread_sel_id_w2[2]; |
---|
1603 | // |
---|
1604 | // generating write enables to update the hpstate registers |
---|
1605 | // modified for timing |
---|
1606 | /* |
---|
1607 | assign tlu_hpstate_din_sel2[0] = tlu_dnrtry2_inst_g; |
---|
1608 | assign tlu_hpstate_din_sel2[1] = (hpstate_rw_g & wsr_inst_g) & |
---|
1609 | ~tlu_hpstate_din_sel2[0] & |
---|
1610 | thread_sel_id_g[2]; |
---|
1611 | assign update_hpstate2_g = tlu_thrd2_traps | tlu_dnrtry2_inst_g | |
---|
1612 | ((hpstate_rw_g & wsr_inst_g) & |
---|
1613 | thread_sel_id_g[2]); |
---|
1614 | |
---|
1615 | assign tlu_update_hpstate_l_g[2] = ~(update_hpstate2_g | local_rst); |
---|
1616 | */ |
---|
1617 | assign update_hpstate_g[2] = |
---|
1618 | tlu_dnrtry2_inst_g | ((hpstate_rw_g & wsr_inst_g) & |
---|
1619 | thread_sel_id_g[2]); |
---|
1620 | |
---|
1621 | assign tlu_update_hpstate_l_w2[2] = |
---|
1622 | ~(update_hpstate_w2[2] | local_rst | tlu_thrd_traps_w2[2]); |
---|
1623 | // |
---|
1624 | // thread 3 |
---|
1625 | assign tlu_hpstate_din_sel3[0] = dnrtry_inst_w2[3] & ~rst_tri_en; |
---|
1626 | assign tlu_hpstate_din_sel3[1] = (hpstate_rw_w2 & wsr_inst_w2) & |
---|
1627 | ~tlu_hpstate_din_sel3[0] & |
---|
1628 | ~rst_tri_en & |
---|
1629 | thread_sel_id_w2[3]; |
---|
1630 | // |
---|
1631 | // generating write enables to update the hpstate registers |
---|
1632 | // modified for timing |
---|
1633 | /* |
---|
1634 | assign tlu_hpstate_din_sel3[0] = tlu_dnrtry3_inst_g; |
---|
1635 | assign tlu_hpstate_din_sel3[1] = (hpstate_rw_g & wsr_inst_g) & |
---|
1636 | ~tlu_hpstate_din_sel3[0] & |
---|
1637 | thread_sel_id_g[3]; |
---|
1638 | assign update_hpstate3_g = tlu_thrd3_traps | tlu_dnrtry3_inst_g | |
---|
1639 | ((hpstate_rw_g & wsr_inst_g) & |
---|
1640 | thread_sel_id_g[3]); |
---|
1641 | |
---|
1642 | assign tlu_update_hpstate_l_g[3] = ~(update_hpstate3_g | local_rst); |
---|
1643 | */ |
---|
1644 | assign update_hpstate_g[3] = |
---|
1645 | tlu_dnrtry3_inst_g | ((hpstate_rw_g & wsr_inst_g) & |
---|
1646 | thread_sel_id_g[3]); |
---|
1647 | |
---|
1648 | assign tlu_update_hpstate_l_w2[3] = |
---|
1649 | ~(update_hpstate_w2[3] | local_rst | tlu_thrd_traps_w2[3]); |
---|
1650 | |
---|
1651 | //////////////////////////////////////////////////////////////////////// |
---|
1652 | // HTICKCMP register controls |
---|
1653 | //////////////////////////////////////////////////////////////////////// |
---|
1654 | // thread 0 |
---|
1655 | assign htickcmp_intdis_en[0] = |
---|
1656 | (htickcmp_rw_g & wsr_inst_g & thread_sel_id_g[0]) | |
---|
1657 | local_rst | por_rstint0_g; |
---|
1658 | // |
---|
1659 | // HTICK_CMP.INT_DIS |
---|
1660 | dffe_s dffe_hintdis0 ( |
---|
1661 | .din (tlu_tick_ctl_din), |
---|
1662 | .q (htick_intdis0), |
---|
1663 | .en (htickcmp_intdis_en[0]), |
---|
1664 | .clk (clk), |
---|
1665 | .se (se), |
---|
1666 | .si (), |
---|
1667 | .so () |
---|
1668 | ); |
---|
1669 | |
---|
1670 | // thread 1 |
---|
1671 | assign htickcmp_intdis_en[1] = |
---|
1672 | (htickcmp_rw_g & wsr_inst_g & thread_sel_id_g[1]) | |
---|
1673 | local_rst | por_rstint1_g; |
---|
1674 | // |
---|
1675 | // HTICK_CMP.INT_DIS |
---|
1676 | dffe_s dffe_hintdis1 ( |
---|
1677 | .din (tlu_tick_ctl_din), |
---|
1678 | .q (htick_intdis1), |
---|
1679 | .en (htickcmp_intdis_en[1]), |
---|
1680 | .clk (clk), |
---|
1681 | .se (se), |
---|
1682 | .si (), |
---|
1683 | .so () |
---|
1684 | ); |
---|
1685 | |
---|
1686 | // thread 2 |
---|
1687 | assign htickcmp_intdis_en[2] = |
---|
1688 | (htickcmp_rw_g & wsr_inst_g & thread_sel_id_g[2]) | |
---|
1689 | local_rst | por_rstint2_g; |
---|
1690 | // |
---|
1691 | // HTICK_CMP.INT_DIS |
---|
1692 | dffe_s dffe_hintdis2 ( |
---|
1693 | .din (tlu_tick_ctl_din), |
---|
1694 | .q (htick_intdis2), |
---|
1695 | .en (htickcmp_intdis_en[2]), |
---|
1696 | .clk (clk), |
---|
1697 | .se (se), |
---|
1698 | .si (), |
---|
1699 | .so () |
---|
1700 | ); |
---|
1701 | |
---|
1702 | // thread 3 |
---|
1703 | assign htickcmp_intdis_en[3] = |
---|
1704 | (htickcmp_rw_g & wsr_inst_g & thread_sel_id_g[3]) | |
---|
1705 | local_rst | por_rstint3_g; |
---|
1706 | // HTICK_CMP.INT_DIS |
---|
1707 | // |
---|
1708 | dffe_s dffe_hintdis3 ( |
---|
1709 | .din (tlu_tick_ctl_din), |
---|
1710 | .q (htick_intdis3), |
---|
1711 | .en (htickcmp_intdis_en[3]), |
---|
1712 | .clk (clk), |
---|
1713 | .se (se), |
---|
1714 | .si (), |
---|
1715 | .so () |
---|
1716 | ); |
---|
1717 | // |
---|
1718 | // generating for the non-thread specific htick_cmp |
---|
1719 | // interrupt disable |
---|
1720 | assign tlu_htickcmp_intdis = |
---|
1721 | (thread_sel_id_e[0] & htick_intdis0) | (thread_sel_id_e[1] & htick_intdis1) | |
---|
1722 | (thread_sel_id_e[2] & htick_intdis2) | (thread_sel_id_e[3] & htick_intdis3); |
---|
1723 | |
---|
1724 | //////////////////////////////////////////////////////////////////////// |
---|
1725 | // HINTP register controls |
---|
1726 | //////////////////////////////////////////////////////////////////////// |
---|
1727 | // thread 0 |
---|
1728 | // |
---|
1729 | // modified for timing |
---|
1730 | // assign tlu_set_hintp_g[0] = |
---|
1731 | // (~htick_intdis0 & tlu_tickcmp_sel[0])? tlu_htick_match: 1'b0; |
---|
1732 | assign tlu_set_hintp_sel_g[0] = ~htick_intdis0 & tlu_tickcmp_sel[0]; |
---|
1733 | // modified for bug 4886 |
---|
1734 | assign tlu_wr_hintp_g[0] = |
---|
1735 | (hintp_rw_g & wsr_inst_g & thread_sel_id_g[0]) | local_rst; |
---|
1736 | // |
---|
1737 | // modified for timing - moved to tlu_tdp |
---|
1738 | // assign tlu_hintp_en_l_g[0] = |
---|
1739 | // ~(tlu_set_hintp_g[0] | tlu_wr_hintp_g[0]); |
---|
1740 | // |
---|
1741 | // thread 1 |
---|
1742 | // |
---|
1743 | // modified for timing |
---|
1744 | // assign tlu_set_hintp_g[1] = |
---|
1745 | // (~htick_intdis1 & tlu_tickcmp_sel[1])? tlu_htick_match: 1'b0; |
---|
1746 | assign tlu_set_hintp_sel_g[1] = ~htick_intdis1 & tlu_tickcmp_sel[1]; |
---|
1747 | assign tlu_wr_hintp_g[1] = |
---|
1748 | (hintp_rw_g & wsr_inst_g & thread_sel_id_g[1]) | local_rst; |
---|
1749 | // |
---|
1750 | // modified for timing - moved to tlu_tdp |
---|
1751 | // assign tlu_hintp_en_l_g[1] = |
---|
1752 | // ~(tlu_set_hintp_g[1] | tlu_wr_hintp_g[1]); |
---|
1753 | // |
---|
1754 | // thread 2 |
---|
1755 | // |
---|
1756 | // modified for timing |
---|
1757 | // assign tlu_set_hintp_g[2] = |
---|
1758 | // (~htick_intdis2 & tlu_tickcmp_sel[2])? tlu_htick_match: 1'b0; |
---|
1759 | assign tlu_set_hintp_sel_g[2] = ~htick_intdis2 & tlu_tickcmp_sel[2]; |
---|
1760 | assign tlu_wr_hintp_g[2] = |
---|
1761 | (hintp_rw_g & wsr_inst_g & thread_sel_id_g[2]) | local_rst; |
---|
1762 | // |
---|
1763 | // modified for timing - moved to tlu_tdp |
---|
1764 | // assign tlu_hintp_en_l_g[2] = |
---|
1765 | // ~(tlu_set_hintp_g[2] | tlu_wr_hintp_g[2]); |
---|
1766 | // |
---|
1767 | // thread 3 |
---|
1768 | // |
---|
1769 | // modified for timing |
---|
1770 | // assign tlu_set_hintp_g[3] = |
---|
1771 | // (~htick_intdis3 & tlu_tickcmp_sel[3])? tlu_htick_match: 1'b0; |
---|
1772 | assign tlu_set_hintp_sel_g[3] = ~htick_intdis3 & tlu_tickcmp_sel[3]; |
---|
1773 | assign tlu_wr_hintp_g[3] = |
---|
1774 | (hintp_rw_g & wsr_inst_g & thread_sel_id_g[3]) | local_rst; |
---|
1775 | // |
---|
1776 | // modified for timing - moved to tlu_tdp |
---|
1777 | // assign tlu_hintp_en_l_g[3] = |
---|
1778 | // ~(tlu_set_hintp_g[3] | tlu_wr_hintp_g[3]); |
---|
1779 | |
---|
1780 | //////////////////////////////////////////////////////////////////////// |
---|
1781 | // HTBA register controls |
---|
1782 | //////////////////////////////////////////////////////////////////////// |
---|
1783 | |
---|
1784 | assign tlu_htba_en_l[0] = ~(htba_rw_g & wsr_inst_g & thread_sel_id_g[0]); |
---|
1785 | assign tlu_htba_en_l[1] = ~(htba_rw_g & wsr_inst_g & thread_sel_id_g[1]); |
---|
1786 | assign tlu_htba_en_l[2] = ~(htba_rw_g & wsr_inst_g & thread_sel_id_g[2]); |
---|
1787 | assign tlu_htba_en_l[3] = ~(htba_rw_g & wsr_inst_g & thread_sel_id_g[3]); |
---|
1788 | |
---|
1789 | //////////////////////////////////////////////////////////////////////// |
---|
1790 | // ASI QUEUE register controls and data |
---|
1791 | //////////////////////////////////////////////////////////////////////// |
---|
1792 | // ASI read or write op |
---|
1793 | // |
---|
1794 | assign asi_queue_write_e = ifu_lsu_alt_space_e & ifu_lsu_st_inst_e; |
---|
1795 | assign asi_queue_read_e = ifu_lsu_alt_space_e & ifu_lsu_ld_inst_e; |
---|
1796 | // |
---|
1797 | // qualify the asi write and read controls |
---|
1798 | assign asi_queue_write_m = tlu_inst_vld_m & asi_queue_write_pq_m; |
---|
1799 | assign asi_queue_read_m = tlu_inst_vld_m & asi_queue_read_pq_m; |
---|
1800 | // |
---|
1801 | // modified due to timing violations |
---|
1802 | // assign asi_queue_write_g = |
---|
1803 | // ~(tlu_flush_pipe_w | ifu_tlu_flush_w) & asi_queue_write_uf_g; |
---|
1804 | assign asi_queue_write_g = |
---|
1805 | ~local_flush_all_w & asi_queue_write_uf_g; |
---|
1806 | assign tlu_asi_write_g = asi_queue_write_g; |
---|
1807 | |
---|
1808 | // assign asi_queue_read_g = |
---|
1809 | // ~(tlu_flush_pipe_w | ifu_tlu_flush_w) & asi_queue_read_uf_g; |
---|
1810 | // |
---|
1811 | // staging the asi controls |
---|
1812 | dffr_s #(2) dffr_asi_ctl_m ( |
---|
1813 | .din ({asi_queue_write_e, asi_queue_read_e}), |
---|
1814 | .q ({asi_queue_write_pq_m, asi_queue_read_pq_m}), |
---|
1815 | .rst (local_rst), |
---|
1816 | .clk (clk), |
---|
1817 | .se (se), |
---|
1818 | .si (), |
---|
1819 | .so () |
---|
1820 | ); |
---|
1821 | |
---|
1822 | dffr_s #(2) dffr_asi_ctl_g ( |
---|
1823 | .din ({asi_queue_write_m, asi_queue_read_m}), |
---|
1824 | .q ({asi_queue_write_uf_g, asi_queue_read_g}), |
---|
1825 | .rst (local_rst), |
---|
1826 | .clk (clk), |
---|
1827 | .se (se), |
---|
1828 | .si (), |
---|
1829 | .so () |
---|
1830 | ); |
---|
1831 | // |
---|
1832 | // ASI address decode |
---|
1833 | // decoding the ASI state 0x25 for the ASI_QUEUES |
---|
1834 | assign asi_queue_rw_e = |
---|
1835 | (ifu_lsu_alt_space_e)? |
---|
1836 | (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]==`TLU_ASI_QUE_ASI): |
---|
1837 | 1'b0; |
---|
1838 | // |
---|
1839 | // staging the asi controls |
---|
1840 | dffr_s dffr_asi_queue_rw_m ( |
---|
1841 | .din (asi_queue_rw_e), |
---|
1842 | .q (asi_queue_rw_m), |
---|
1843 | .rst (local_rst), |
---|
1844 | .clk (clk), |
---|
1845 | .se (se), |
---|
1846 | .si (), |
---|
1847 | .so () |
---|
1848 | ); |
---|
1849 | |
---|
1850 | dffr_s dffr_asi_queue_rw_g ( |
---|
1851 | .din (asi_queue_rw_m), |
---|
1852 | .q (asi_queue_rw_g), |
---|
1853 | .rst (local_rst), |
---|
1854 | .clk (clk), |
---|
1855 | .se (se), |
---|
1856 | .si (), |
---|
1857 | .so () |
---|
1858 | ); |
---|
1859 | // |
---|
1860 | // modified due to timing violations |
---|
1861 | /* |
---|
1862 | // assign tlu_ldst_va_e[`TLU_ASI_VA_WIDTH-1:0] = |
---|
1863 | // exu_lsu_ldst_va_e[`TLU_ASI_VA_WIDTH-1:0]; |
---|
1864 | dff_s #(`TLU_ASI_VA_WIDTH) dff_tlu_ldst_va_m ( |
---|
1865 | .din (exu_lsu_ldst_va_e[`TLU_ASI_VA_WIDTH-1:0]), |
---|
1866 | .q (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]), |
---|
1867 | .clk (clk), |
---|
1868 | .se (se), |
---|
1869 | .si (), |
---|
1870 | .so () |
---|
1871 | ); |
---|
1872 | |
---|
1873 | // modified for timing |
---|
1874 | assign que_legal_va_e = |
---|
1875 | cpu_mondo_head_rw_e | cpu_mondo_tail_rw_e | |
---|
1876 | dev_mondo_head_rw_e | dev_mondo_tail_rw_e | |
---|
1877 | resum_err_head_rw_e | resum_err_tail_rw_e | |
---|
1878 | nresum_err_head_rw_e | nresum_err_tail_rw_e; |
---|
1879 | |
---|
1880 | assign que_ill_va_e = |
---|
1881 | (ifu_lsu_alt_space_e)? |
---|
1882 | (((|exu_lsu_ldst_va_e[`ASI_VA_WIDTH-1:`TLU_ASI_QUE_VA_HI+1]) | |
---|
1883 | (|exu_lsu_ldst_va_e[`TLU_ASI_QUE_VA_LO-1:0]) | ~que_legal_va_e) & |
---|
1884 | asi_queue_pq_rw_e): 1'b0; |
---|
1885 | */ |
---|
1886 | assign tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0] = |
---|
1887 | lsu_tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]; |
---|
1888 | |
---|
1889 | assign que_legal_va_m = |
---|
1890 | cpu_mondo_head_rw_m | cpu_mondo_tail_rw_m | |
---|
1891 | dev_mondo_head_rw_m | dev_mondo_tail_rw_m | |
---|
1892 | resum_err_head_rw_m | resum_err_tail_rw_m | |
---|
1893 | nresum_err_head_rw_m | nresum_err_tail_rw_m; |
---|
1894 | |
---|
1895 | // |
---|
1896 | // illegal range check for queue va |
---|
1897 | assign que_ill_va_m = |
---|
1898 | (asi_queue_rw_m)? ~que_legal_va_m : 1'b0; |
---|
1899 | // |
---|
1900 | // staged illegal va range |
---|
1901 | // |
---|
1902 | dffr_s dffr_que_ill_va_g ( |
---|
1903 | .din (que_ill_va_m), |
---|
1904 | .q (que_ill_va_g), |
---|
1905 | .rst (local_rst), |
---|
1906 | .clk (clk), |
---|
1907 | .se (se), |
---|
1908 | .si (), |
---|
1909 | .so () |
---|
1910 | ); |
---|
1911 | // |
---|
1912 | // added for timing - interrupt register decodes |
---|
1913 | // interrupt receiver registers |
---|
1914 | assign asi_inrr_rw_e = |
---|
1915 | (ifu_lsu_alt_space_e)? |
---|
1916 | (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]==`TLU_INRR_ASI): |
---|
1917 | 1'b0; |
---|
1918 | |
---|
1919 | dffr_s dffr_asi_inrr_rw_m ( |
---|
1920 | .din (asi_inrr_rw_e), |
---|
1921 | .q (asi_inrr_rw_m), |
---|
1922 | .rst (local_rst), |
---|
1923 | .clk (clk), |
---|
1924 | .se (se), |
---|
1925 | .si (), |
---|
1926 | .so () |
---|
1927 | ); |
---|
1928 | |
---|
1929 | dffr_s dffr_asi_inrr_rw_g ( |
---|
1930 | .din (asi_inrr_rw_m), |
---|
1931 | .q (asi_inrr_rw_g), |
---|
1932 | .rst (local_rst), |
---|
1933 | .clk (clk), |
---|
1934 | .se (se), |
---|
1935 | .si (), |
---|
1936 | .so () |
---|
1937 | ); |
---|
1938 | |
---|
1939 | assign inc_ind_asi_wr_inrr[0] = |
---|
1940 | (asi_inrr_rw_g & asi_queue_write_uf_g & |
---|
1941 | ~local_flush_all_w & thread_sel_id_g[0]); |
---|
1942 | assign inc_ind_asi_wr_inrr[1] = |
---|
1943 | (asi_inrr_rw_g & asi_queue_write_uf_g & |
---|
1944 | ~local_flush_all_w & thread_sel_id_g[1]); |
---|
1945 | assign inc_ind_asi_wr_inrr[2] = |
---|
1946 | (asi_inrr_rw_g & asi_queue_write_uf_g & |
---|
1947 | ~local_flush_all_w & thread_sel_id_g[2]); |
---|
1948 | assign inc_ind_asi_wr_inrr[3] = |
---|
1949 | (asi_inrr_rw_g & asi_queue_write_uf_g & |
---|
1950 | ~local_flush_all_w & thread_sel_id_g[3]); |
---|
1951 | // |
---|
1952 | // interrupt dispatch registers |
---|
1953 | assign asi_indr_rw_e = |
---|
1954 | (ifu_lsu_alt_space_e)? |
---|
1955 | (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]==`TLU_INDR_ASI): |
---|
1956 | 1'b0; |
---|
1957 | |
---|
1958 | dffr_s dffr_asi_indr_rw_m ( |
---|
1959 | .din (asi_indr_rw_e), |
---|
1960 | .q (asi_indr_rw_m), |
---|
1961 | .rst (local_rst), |
---|
1962 | .clk (clk), |
---|
1963 | .se (se), |
---|
1964 | .si (), |
---|
1965 | .so () |
---|
1966 | ); |
---|
1967 | |
---|
1968 | dffr_s dffr_asi_indr_rw_g ( |
---|
1969 | .din (asi_indr_rw_m), |
---|
1970 | .q (asi_indr_rw_g), |
---|
1971 | .rst (local_rst), |
---|
1972 | .clk (clk), |
---|
1973 | .se (se), |
---|
1974 | .si (), |
---|
1975 | .so () |
---|
1976 | ); |
---|
1977 | |
---|
1978 | assign inc_ind_asi_wr_indr[0] = |
---|
1979 | asi_indr_rw_g & ~local_flush_all_w & asi_queue_write_uf_g & |
---|
1980 | thread_sel_id_g[0]; |
---|
1981 | assign inc_ind_asi_wr_indr[1] = |
---|
1982 | asi_indr_rw_g & ~local_flush_all_w & asi_queue_write_uf_g & |
---|
1983 | thread_sel_id_g[1]; |
---|
1984 | assign inc_ind_asi_wr_indr[2] = |
---|
1985 | asi_indr_rw_g & ~local_flush_all_w & asi_queue_write_uf_g & |
---|
1986 | thread_sel_id_g[2]; |
---|
1987 | assign inc_ind_asi_wr_indr[3] = |
---|
1988 | asi_indr_rw_g & ~local_flush_all_w & asi_queue_write_uf_g & |
---|
1989 | thread_sel_id_g[3]; |
---|
1990 | |
---|
1991 | // |
---|
1992 | // interrupt vector registers |
---|
1993 | assign asi_invr_rw_e = |
---|
1994 | (ifu_lsu_alt_space_e)? |
---|
1995 | (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]==`TLU_INVR_ASI): |
---|
1996 | 1'b0; |
---|
1997 | |
---|
1998 | dffr_s dffr_asi_invr_rw_m ( |
---|
1999 | .din (asi_invr_rw_e), |
---|
2000 | .q (asi_invr_rw_m), |
---|
2001 | .rst (local_rst), |
---|
2002 | .clk (clk), |
---|
2003 | .se (se), |
---|
2004 | .si (), |
---|
2005 | .so () |
---|
2006 | ); |
---|
2007 | |
---|
2008 | dffr_s dffr_asi_invr_rw_g ( |
---|
2009 | .din (asi_invr_rw_m), |
---|
2010 | .q (asi_invr_rw_g), |
---|
2011 | .rst (local_rst), |
---|
2012 | .clk (clk), |
---|
2013 | .se (se), |
---|
2014 | .si (), |
---|
2015 | .so () |
---|
2016 | ); |
---|
2017 | |
---|
2018 | assign inc_ind_asi_rd_invr[0] = |
---|
2019 | (asi_invr_rw_g & asi_queue_read_g & |
---|
2020 | ~local_flush_all_w & thread_sel_id_g[0]); |
---|
2021 | assign inc_ind_asi_rd_invr[1] = |
---|
2022 | (asi_invr_rw_g & asi_queue_read_g & |
---|
2023 | ~local_flush_all_w & thread_sel_id_g[1]); |
---|
2024 | assign inc_ind_asi_rd_invr[2] = |
---|
2025 | (asi_invr_rw_g & asi_queue_read_g & |
---|
2026 | ~local_flush_all_w & thread_sel_id_g[2]); |
---|
2027 | assign inc_ind_asi_rd_invr[3] = |
---|
2028 | (asi_invr_rw_g & asi_queue_read_g & |
---|
2029 | ~local_flush_all_w & thread_sel_id_g[3]); |
---|
2030 | // |
---|
2031 | // timing changes: all va e stage signals have been moved to m-stage |
---|
2032 | // decoding the VA portion of the ASI address |
---|
2033 | // cpu_mondo_head: 0x3c0 |
---|
2034 | assign cpu_mondo_head_rw_m = |
---|
2035 | (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`CPU_MONDO_HEAD); |
---|
2036 | // |
---|
2037 | // cpu_mondo_tail: 0x3c8 |
---|
2038 | assign cpu_mondo_tail_rw_m = |
---|
2039 | (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`CPU_MONDO_TAIL); |
---|
2040 | // |
---|
2041 | // dev_mondo_head: 0x3d0 |
---|
2042 | assign dev_mondo_head_rw_m = |
---|
2043 | (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`DEV_MONDO_HEAD); |
---|
2044 | // |
---|
2045 | // dev_mondo_tail: 0x3d8 |
---|
2046 | assign dev_mondo_tail_rw_m = |
---|
2047 | (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`DEV_MONDO_TAIL); |
---|
2048 | // |
---|
2049 | // resum_err_head: 0x3e0 |
---|
2050 | assign resum_err_head_rw_m = |
---|
2051 | (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`RESUM_ERR_HEAD); |
---|
2052 | // |
---|
2053 | // resum_err_tail: 0x3e8 |
---|
2054 | assign resum_err_tail_rw_m = |
---|
2055 | (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`RESUM_ERR_TAIL); |
---|
2056 | // |
---|
2057 | // nresum_err_head: 0x3f0 |
---|
2058 | assign nresum_err_head_rw_m = |
---|
2059 | (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`NRESUM_ERR_HEAD); |
---|
2060 | // |
---|
2061 | // nresum_err_tail: 0x3f8 |
---|
2062 | assign nresum_err_tail_rw_m = |
---|
2063 | (tlu_ldst_va_m[`TLU_ASI_VA_WIDTH-1:0]==`NRESUM_ERR_TAIL); |
---|
2064 | // |
---|
2065 | // timing change: replaced by flopped tlu_ldst_va_m decodes |
---|
2066 | // staging the ASI queue rw decodes |
---|
2067 | // cpu_mondo_head |
---|
2068 | /* |
---|
2069 | dff_s dff_cpu_mondo_head_rw_m ( |
---|
2070 | .din (cpu_mondo_head_rw_e), |
---|
2071 | .q (cpu_mondo_head_rw_m), |
---|
2072 | .clk (clk), |
---|
2073 | .se (se), |
---|
2074 | .si (), |
---|
2075 | .so () |
---|
2076 | ); |
---|
2077 | |
---|
2078 | dff_s dff_dev_mondo_head_rw_m ( |
---|
2079 | .din (dev_mondo_head_rw_e), |
---|
2080 | .q (dev_mondo_head_rw_m), |
---|
2081 | .clk (clk), |
---|
2082 | .se (se), |
---|
2083 | .si (), |
---|
2084 | .so () |
---|
2085 | ); |
---|
2086 | |
---|
2087 | dff_s dff_resum_err_head_rw_m ( |
---|
2088 | .din (resum_err_head_rw_e), |
---|
2089 | .q (resum_err_head_rw_m), |
---|
2090 | .clk (clk), |
---|
2091 | .se (se), |
---|
2092 | .si (), |
---|
2093 | .so () |
---|
2094 | ); |
---|
2095 | |
---|
2096 | dff_s dff_nresum_err_head_rw_m ( |
---|
2097 | .din (nresum_err_head_rw_e), |
---|
2098 | .q (nresum_err_head_rw_m), |
---|
2099 | .clk (clk), |
---|
2100 | .se (se), |
---|
2101 | .si (), |
---|
2102 | .so () |
---|
2103 | ); |
---|
2104 | |
---|
2105 | dff_s dff_cpu_mondo_tail_rw_m ( |
---|
2106 | .din (cpu_mondo_tail_rw_e), |
---|
2107 | .q (cpu_mondo_tail_rw_m), |
---|
2108 | .clk (clk), |
---|
2109 | .se (se), |
---|
2110 | .si (), |
---|
2111 | .so () |
---|
2112 | ); |
---|
2113 | |
---|
2114 | dff_s dff_dev_mondo_tail_rw_m ( |
---|
2115 | .din (dev_mondo_tail_rw_e), |
---|
2116 | .q (dev_mondo_tail_rw_m), |
---|
2117 | .clk (clk), |
---|
2118 | .se (se), |
---|
2119 | .si (), |
---|
2120 | .so () |
---|
2121 | ); |
---|
2122 | |
---|
2123 | dff_s dff_resum_err_tail_rw_m ( |
---|
2124 | .din (resum_err_tail_rw_e), |
---|
2125 | .q (resum_err_tail_rw_m), |
---|
2126 | .clk (clk), |
---|
2127 | .se (se), |
---|
2128 | .si (), |
---|
2129 | .so () |
---|
2130 | ); |
---|
2131 | |
---|
2132 | dff_s dff_nresum_err_tail_rw_m ( |
---|
2133 | .din (nresum_err_tail_rw_e), |
---|
2134 | .q (nresum_err_tail_rw_m), |
---|
2135 | .clk (clk), |
---|
2136 | .se (se), |
---|
2137 | .si (), |
---|
2138 | .so () |
---|
2139 | ); |
---|
2140 | // |
---|
2141 | // illegal range check |
---|
2142 | dffr_s dffr_que_ill_va_m ( |
---|
2143 | .din (que_ill_va_e), |
---|
2144 | .q (que_ill_va_m), |
---|
2145 | .rst (local_rst), |
---|
2146 | .clk (clk), |
---|
2147 | .se (se), |
---|
2148 | .si (), |
---|
2149 | .so () |
---|
2150 | ); |
---|
2151 | */ |
---|
2152 | |
---|
2153 | // staging the ASI queue rw decodes |
---|
2154 | // cpu_mondo_head |
---|
2155 | dff_s dff_cpu_mondo_head_rw_g ( |
---|
2156 | .din (cpu_mondo_head_rw_m), |
---|
2157 | .q (cpu_mondo_head_rw_g), |
---|
2158 | .clk (clk), |
---|
2159 | .se (se), |
---|
2160 | .si (), |
---|
2161 | .so () |
---|
2162 | ); |
---|
2163 | // |
---|
2164 | // dev_mondo_head |
---|
2165 | dff_s dff_dev_mondo_head_rw_g ( |
---|
2166 | .din (dev_mondo_head_rw_m), |
---|
2167 | .q (dev_mondo_head_rw_g), |
---|
2168 | .clk (clk), |
---|
2169 | .se (se), |
---|
2170 | .si (), |
---|
2171 | .so () |
---|
2172 | ); |
---|
2173 | // |
---|
2174 | // resum_err_head |
---|
2175 | dff_s dff_resum_err_head_rw_g ( |
---|
2176 | .din (resum_err_head_rw_m), |
---|
2177 | .q (resum_err_head_rw_g), |
---|
2178 | .clk (clk), |
---|
2179 | .se (se), |
---|
2180 | .si (), |
---|
2181 | .so () |
---|
2182 | ); |
---|
2183 | // |
---|
2184 | // nresum_err_head |
---|
2185 | dff_s dff_nresum_err_head_rw_g ( |
---|
2186 | .din (nresum_err_head_rw_m), |
---|
2187 | .q (nresum_err_head_rw_g), |
---|
2188 | .clk (clk), |
---|
2189 | .se (se), |
---|
2190 | .si (), |
---|
2191 | .so () |
---|
2192 | ); |
---|
2193 | // |
---|
2194 | // cpu_mondo_tail |
---|
2195 | // |
---|
2196 | dff_s dff_cpu_mondo_tail_rw_g ( |
---|
2197 | .din (cpu_mondo_tail_rw_m), |
---|
2198 | .q (cpu_mondo_tail_rw_g), |
---|
2199 | .clk (clk), |
---|
2200 | .se (se), |
---|
2201 | .si (), |
---|
2202 | .so () |
---|
2203 | ); |
---|
2204 | // |
---|
2205 | // dev_mondo_tail |
---|
2206 | // |
---|
2207 | dff_s dff_dev_mondo_tail_rw_g ( |
---|
2208 | .din (dev_mondo_tail_rw_m), |
---|
2209 | .q (dev_mondo_tail_rw_g), |
---|
2210 | .clk (clk), |
---|
2211 | .se (se), |
---|
2212 | .si (), |
---|
2213 | .so () |
---|
2214 | ); |
---|
2215 | // |
---|
2216 | // resum_err_tail |
---|
2217 | // |
---|
2218 | dff_s dff_resum_err_tail_rw_g ( |
---|
2219 | .din (resum_err_tail_rw_m), |
---|
2220 | .q (resum_err_tail_rw_g), |
---|
2221 | .clk (clk), |
---|
2222 | .se (se), |
---|
2223 | .si (), |
---|
2224 | .so () |
---|
2225 | ); |
---|
2226 | // |
---|
2227 | // nresum_err_tail |
---|
2228 | // |
---|
2229 | dff_s dff_nresum_err_tail_rw_g ( |
---|
2230 | .din (nresum_err_tail_rw_m), |
---|
2231 | .q (nresum_err_tail_rw_g), |
---|
2232 | .clk (clk), |
---|
2233 | .se (se), |
---|
2234 | .si (), |
---|
2235 | .so () |
---|
2236 | ); |
---|
2237 | // |
---|
2238 | // generating thread specific read and write enables |
---|
2239 | // |
---|
2240 | // cpu_mondo_head read |
---|
2241 | // assign cpu_mondo_head_rd_g[0] = |
---|
2242 | // asi_queue_read_g & cpu_mondo_head_rw_g & |
---|
2243 | // asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2244 | assign cpu_mondo_head_rd_g[0] = |
---|
2245 | ~(|cpu_mondo_head_rd_g[3:1]); |
---|
2246 | assign cpu_mondo_head_rd_g[1] = |
---|
2247 | asi_queue_read_g & cpu_mondo_head_rw_g & |
---|
2248 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2249 | assign cpu_mondo_head_rd_g[2] = |
---|
2250 | asi_queue_read_g & cpu_mondo_head_rw_g & |
---|
2251 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2252 | assign cpu_mondo_head_rd_g[3] = |
---|
2253 | asi_queue_read_g & cpu_mondo_head_rw_g & |
---|
2254 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2255 | // |
---|
2256 | // non-thread specific read |
---|
2257 | assign cpu_mondo_hd_rd_g = |
---|
2258 | asi_queue_read_g & cpu_mondo_head_rw_g & |
---|
2259 | asi_queue_rw_g; |
---|
2260 | // |
---|
2261 | // cpu_mondo_head write |
---|
2262 | // |
---|
2263 | assign cpu_mondo_head_wr_g[0] = |
---|
2264 | ~local_flush_all_w & asi_queue_write_uf_g & cpu_mondo_head_rw_g & |
---|
2265 | asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2266 | assign cpu_mondo_head_wr_g[1] = |
---|
2267 | ~local_flush_all_w & asi_queue_write_uf_g & cpu_mondo_head_rw_g & |
---|
2268 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2269 | assign cpu_mondo_head_wr_g[2] = |
---|
2270 | ~local_flush_all_w & asi_queue_write_uf_g & cpu_mondo_head_rw_g & |
---|
2271 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2272 | assign cpu_mondo_head_wr_g[3] = |
---|
2273 | ~local_flush_all_w & asi_queue_write_uf_g & cpu_mondo_head_rw_g & |
---|
2274 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2275 | // |
---|
2276 | // cpu_mondo_tail read |
---|
2277 | // assign cpu_mondo_tail_rd_g[0] = |
---|
2278 | // asi_queue_read_g & cpu_mondo_tail_rw_g & |
---|
2279 | // asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2280 | assign cpu_mondo_tail_rd_g[0] = |
---|
2281 | ~(|cpu_mondo_tail_rd_g[3:1]); |
---|
2282 | assign cpu_mondo_tail_rd_g[1] = |
---|
2283 | asi_queue_read_g & cpu_mondo_tail_rw_g & |
---|
2284 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2285 | assign cpu_mondo_tail_rd_g[2] = |
---|
2286 | asi_queue_read_g & cpu_mondo_tail_rw_g & |
---|
2287 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2288 | assign cpu_mondo_tail_rd_g[3] = |
---|
2289 | asi_queue_read_g & cpu_mondo_tail_rw_g & |
---|
2290 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2291 | // |
---|
2292 | // non-thread specific read |
---|
2293 | assign cpu_mondo_ta_rd_g = |
---|
2294 | asi_queue_read_g & cpu_mondo_tail_rw_g & |
---|
2295 | asi_queue_rw_g; |
---|
2296 | // |
---|
2297 | // cpu_mondo_tail write |
---|
2298 | // |
---|
2299 | assign cpu_mondo_tail_wr_g[0] = |
---|
2300 | ~local_flush_all_w & asi_queue_write_uf_g & cpu_mondo_tail_rw_g & |
---|
2301 | asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2302 | assign cpu_mondo_tail_wr_g[1] = |
---|
2303 | ~local_flush_all_w & asi_queue_write_uf_g & cpu_mondo_tail_rw_g & |
---|
2304 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2305 | assign cpu_mondo_tail_wr_g[2] = |
---|
2306 | ~local_flush_all_w & asi_queue_write_uf_g & cpu_mondo_tail_rw_g & |
---|
2307 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2308 | assign cpu_mondo_tail_wr_g[3] = |
---|
2309 | ~local_flush_all_w & asi_queue_write_uf_g & cpu_mondo_tail_rw_g & |
---|
2310 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2311 | // |
---|
2312 | // dev_mondo_head read |
---|
2313 | // assign dev_mondo_head_rd_g[0] = |
---|
2314 | // asi_queue_read_g & dev_mondo_head_rw_g & |
---|
2315 | // asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2316 | assign dev_mondo_head_rd_g[0] = |
---|
2317 | ~(|dev_mondo_head_rd_g[3:1]); |
---|
2318 | assign dev_mondo_head_rd_g[1] = |
---|
2319 | asi_queue_read_g & dev_mondo_head_rw_g & |
---|
2320 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2321 | assign dev_mondo_head_rd_g[2] = |
---|
2322 | asi_queue_read_g & dev_mondo_head_rw_g & |
---|
2323 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2324 | assign dev_mondo_head_rd_g[3] = |
---|
2325 | asi_queue_read_g & dev_mondo_head_rw_g & |
---|
2326 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2327 | // |
---|
2328 | // non-thread specific read |
---|
2329 | assign dev_mondo_hd_rd_g = |
---|
2330 | asi_queue_read_g & dev_mondo_head_rw_g & |
---|
2331 | asi_queue_rw_g; |
---|
2332 | // |
---|
2333 | // dev_mondo_head write |
---|
2334 | // |
---|
2335 | assign dev_mondo_head_wr_g[0] = |
---|
2336 | ~local_flush_all_w & asi_queue_write_uf_g & dev_mondo_head_rw_g & |
---|
2337 | asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2338 | assign dev_mondo_head_wr_g[1] = |
---|
2339 | ~local_flush_all_w & asi_queue_write_uf_g & dev_mondo_head_rw_g & |
---|
2340 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2341 | assign dev_mondo_head_wr_g[2] = |
---|
2342 | ~local_flush_all_w & asi_queue_write_uf_g & dev_mondo_head_rw_g & |
---|
2343 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2344 | assign dev_mondo_head_wr_g[3] = |
---|
2345 | ~local_flush_all_w & asi_queue_write_uf_g & dev_mondo_head_rw_g & |
---|
2346 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2347 | // |
---|
2348 | // dev_mondo_tail read |
---|
2349 | // assign dev_mondo_tail_rd_g[0] = |
---|
2350 | // asi_queue_read_g & dev_mondo_tail_rw_g & |
---|
2351 | // asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2352 | assign dev_mondo_tail_rd_g[0] = |
---|
2353 | ~(|dev_mondo_tail_rd_g[3:1]); |
---|
2354 | assign dev_mondo_tail_rd_g[1] = |
---|
2355 | asi_queue_read_g & dev_mondo_tail_rw_g & |
---|
2356 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2357 | assign dev_mondo_tail_rd_g[2] = |
---|
2358 | asi_queue_read_g & dev_mondo_tail_rw_g & |
---|
2359 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2360 | assign dev_mondo_tail_rd_g[3] = |
---|
2361 | asi_queue_read_g & dev_mondo_tail_rw_g & |
---|
2362 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2363 | // |
---|
2364 | // non-thread specific read |
---|
2365 | assign dev_mondo_ta_rd_g = |
---|
2366 | asi_queue_read_g & dev_mondo_tail_rw_g & |
---|
2367 | asi_queue_rw_g; |
---|
2368 | // |
---|
2369 | // dev_mondo_tail write |
---|
2370 | // |
---|
2371 | assign dev_mondo_tail_wr_g[0] = |
---|
2372 | ~local_flush_all_w & asi_queue_write_uf_g & dev_mondo_tail_rw_g & |
---|
2373 | asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2374 | assign dev_mondo_tail_wr_g[1] = |
---|
2375 | ~local_flush_all_w & asi_queue_write_uf_g & dev_mondo_tail_rw_g & |
---|
2376 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2377 | assign dev_mondo_tail_wr_g[2] = |
---|
2378 | ~local_flush_all_w & asi_queue_write_uf_g & dev_mondo_tail_rw_g & |
---|
2379 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2380 | assign dev_mondo_tail_wr_g[3] = |
---|
2381 | ~local_flush_all_w & asi_queue_write_uf_g & dev_mondo_tail_rw_g & |
---|
2382 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2383 | // |
---|
2384 | // resum_err_head read |
---|
2385 | // assign resum_err_head_rd_g[0] = |
---|
2386 | // asi_queue_read_g & resum_err_head_rw_g & |
---|
2387 | // asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2388 | assign resum_err_head_rd_g[0] = |
---|
2389 | ~(|resum_err_head_rd_g[3:1]); |
---|
2390 | assign resum_err_head_rd_g[1] = |
---|
2391 | asi_queue_read_g & resum_err_head_rw_g & |
---|
2392 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2393 | assign resum_err_head_rd_g[2] = |
---|
2394 | asi_queue_read_g & resum_err_head_rw_g & |
---|
2395 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2396 | assign resum_err_head_rd_g[3] = |
---|
2397 | asi_queue_read_g & resum_err_head_rw_g & |
---|
2398 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2399 | // |
---|
2400 | // non-thread specific read |
---|
2401 | assign resum_err_hd_rd_g = |
---|
2402 | asi_queue_read_g & resum_err_head_rw_g & |
---|
2403 | asi_queue_rw_g; |
---|
2404 | // |
---|
2405 | // resum_err_head write |
---|
2406 | // |
---|
2407 | assign resum_err_head_wr_g[0] = |
---|
2408 | asi_queue_write_g & resum_err_head_rw_g & |
---|
2409 | asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2410 | assign resum_err_head_wr_g[1] = |
---|
2411 | asi_queue_write_g & resum_err_head_rw_g & |
---|
2412 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2413 | assign resum_err_head_wr_g[2] = |
---|
2414 | asi_queue_write_g & resum_err_head_rw_g & |
---|
2415 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2416 | assign resum_err_head_wr_g[3] = |
---|
2417 | asi_queue_write_g & resum_err_head_rw_g & |
---|
2418 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2419 | // |
---|
2420 | // resum_err_tail read |
---|
2421 | // assign resum_err_tail_rd_g[0] = |
---|
2422 | // asi_queue_read_g & resum_err_tail_rw_g & |
---|
2423 | // asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2424 | assign resum_err_tail_rd_g[0] = |
---|
2425 | ~(|resum_err_tail_rd_g[3:1]); |
---|
2426 | assign resum_err_tail_rd_g[1] = |
---|
2427 | asi_queue_read_g & resum_err_tail_rw_g & |
---|
2428 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2429 | assign resum_err_tail_rd_g[2] = |
---|
2430 | asi_queue_read_g & resum_err_tail_rw_g & |
---|
2431 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2432 | assign resum_err_tail_rd_g[3] = |
---|
2433 | asi_queue_read_g & resum_err_tail_rw_g & |
---|
2434 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2435 | // |
---|
2436 | // non-thread specific read |
---|
2437 | assign resum_err_ta_rd_g = |
---|
2438 | asi_queue_read_g & resum_err_tail_rw_g & |
---|
2439 | asi_queue_rw_g; |
---|
2440 | // |
---|
2441 | // resum_err_tail write |
---|
2442 | // |
---|
2443 | assign resum_err_tail_wr_g[0] = |
---|
2444 | asi_queue_write_g & resum_err_tail_rw_g & |
---|
2445 | asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2446 | assign resum_err_tail_wr_g[1] = |
---|
2447 | asi_queue_write_g & resum_err_tail_rw_g & |
---|
2448 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2449 | assign resum_err_tail_wr_g[2] = |
---|
2450 | asi_queue_write_g & resum_err_tail_rw_g & |
---|
2451 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2452 | assign resum_err_tail_wr_g[3] = |
---|
2453 | asi_queue_write_g & resum_err_tail_rw_g & |
---|
2454 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2455 | // |
---|
2456 | // nresum_err_head read |
---|
2457 | // assign nresum_err_head_rd_g[0] = |
---|
2458 | // asi_queue_read_g & nresum_err_head_rw_g & |
---|
2459 | // asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2460 | assign nresum_err_head_rd_g[0] = |
---|
2461 | ~(|nresum_err_head_rd_g[3:1]); |
---|
2462 | assign nresum_err_head_rd_g[1] = |
---|
2463 | asi_queue_read_g & nresum_err_head_rw_g & |
---|
2464 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2465 | assign nresum_err_head_rd_g[2] = |
---|
2466 | asi_queue_read_g & nresum_err_head_rw_g & |
---|
2467 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2468 | assign nresum_err_head_rd_g[3] = |
---|
2469 | asi_queue_read_g & nresum_err_head_rw_g & |
---|
2470 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2471 | // |
---|
2472 | // non-thread specific read |
---|
2473 | assign nresum_err_hd_rd_g = |
---|
2474 | asi_queue_read_g & nresum_err_head_rw_g & |
---|
2475 | asi_queue_rw_g; |
---|
2476 | // |
---|
2477 | // nresum_err_head write |
---|
2478 | // |
---|
2479 | assign nresum_err_head_wr_g[0] = |
---|
2480 | asi_queue_write_g & nresum_err_head_rw_g & |
---|
2481 | asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2482 | assign nresum_err_head_wr_g[1] = |
---|
2483 | asi_queue_write_g & nresum_err_head_rw_g & |
---|
2484 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2485 | assign nresum_err_head_wr_g[2] = |
---|
2486 | asi_queue_write_g & nresum_err_head_rw_g & |
---|
2487 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2488 | assign nresum_err_head_wr_g[3] = |
---|
2489 | asi_queue_write_g & nresum_err_head_rw_g & |
---|
2490 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2491 | // |
---|
2492 | // nresum_err_tail read |
---|
2493 | // assign nresum_err_tail_rd_g[0] = |
---|
2494 | // asi_queue_read_g & nresum_err_tail_rw_g & |
---|
2495 | // asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2496 | assign nresum_err_tail_rd_g[0] = |
---|
2497 | ~(|nresum_err_tail_rd_g[3:1]); |
---|
2498 | assign nresum_err_tail_rd_g[1] = |
---|
2499 | asi_queue_read_g & nresum_err_tail_rw_g & |
---|
2500 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2501 | assign nresum_err_tail_rd_g[2] = |
---|
2502 | asi_queue_read_g & nresum_err_tail_rw_g & |
---|
2503 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2504 | assign nresum_err_tail_rd_g[3] = |
---|
2505 | asi_queue_read_g & nresum_err_tail_rw_g & |
---|
2506 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2507 | // |
---|
2508 | // non-thread specific read |
---|
2509 | assign nresum_err_ta_rd_g = |
---|
2510 | asi_queue_read_g & nresum_err_tail_rw_g & |
---|
2511 | asi_queue_rw_g; |
---|
2512 | // |
---|
2513 | // nresum_err_tail write |
---|
2514 | // |
---|
2515 | assign nresum_err_tail_wr_g[0] = |
---|
2516 | asi_queue_write_g & nresum_err_tail_rw_g & |
---|
2517 | asi_queue_rw_g & thread_sel_id_g[0]; |
---|
2518 | assign nresum_err_tail_wr_g[1] = |
---|
2519 | asi_queue_write_g & nresum_err_tail_rw_g & |
---|
2520 | asi_queue_rw_g & thread_sel_id_g[1]; |
---|
2521 | assign nresum_err_tail_wr_g[2] = |
---|
2522 | asi_queue_write_g & nresum_err_tail_rw_g & |
---|
2523 | asi_queue_rw_g & thread_sel_id_g[2]; |
---|
2524 | assign nresum_err_tail_wr_g[3] = |
---|
2525 | asi_queue_write_g & nresum_err_tail_rw_g & |
---|
2526 | asi_queue_rw_g & thread_sel_id_g[3]; |
---|
2527 | // |
---|
2528 | // storing the head and pointers for the queues |
---|
2529 | // thread 0 |
---|
2530 | // |
---|
2531 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo0_head ( |
---|
2532 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2533 | .q (cpu_mondo0_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2534 | .en (cpu_mondo_head_wr_g[0]), |
---|
2535 | .clk (clk), |
---|
2536 | .se (se), |
---|
2537 | .si (), |
---|
2538 | .so () |
---|
2539 | ); |
---|
2540 | |
---|
2541 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo0_tail ( |
---|
2542 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2543 | .q (cpu_mondo0_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2544 | .en (cpu_mondo_tail_wr_g[0]), |
---|
2545 | .clk (clk), |
---|
2546 | .se (se), |
---|
2547 | .si (), |
---|
2548 | .so () |
---|
2549 | ); |
---|
2550 | |
---|
2551 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo0_head ( |
---|
2552 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2553 | .q (dev_mondo0_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2554 | .en (dev_mondo_head_wr_g[0]), |
---|
2555 | .clk (clk), |
---|
2556 | .se (se), |
---|
2557 | .si (), |
---|
2558 | .so () |
---|
2559 | ); |
---|
2560 | |
---|
2561 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo0_tail ( |
---|
2562 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2563 | .q (dev_mondo0_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2564 | .en (dev_mondo_tail_wr_g[0]), |
---|
2565 | .clk (clk), |
---|
2566 | .se (se), |
---|
2567 | .si (), |
---|
2568 | .so () |
---|
2569 | ); |
---|
2570 | |
---|
2571 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err0_head ( |
---|
2572 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2573 | .q (resum_err0_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2574 | .en (resum_err_head_wr_g[0]), |
---|
2575 | .clk (clk), |
---|
2576 | .se (se), |
---|
2577 | .si (), |
---|
2578 | .so () |
---|
2579 | ); |
---|
2580 | |
---|
2581 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err0_tail ( |
---|
2582 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2583 | .q (resum_err0_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2584 | .en (resum_err_tail_wr_g[0]), |
---|
2585 | .clk (clk), |
---|
2586 | .se (se), |
---|
2587 | .si (), |
---|
2588 | .so () |
---|
2589 | ); |
---|
2590 | |
---|
2591 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err0_head ( |
---|
2592 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2593 | .q (nresum_err0_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2594 | .en (nresum_err_head_wr_g[0]), |
---|
2595 | .clk (clk), |
---|
2596 | .se (se), |
---|
2597 | .si (), |
---|
2598 | .so () |
---|
2599 | ); |
---|
2600 | |
---|
2601 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err0_tail ( |
---|
2602 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2603 | .q (nresum_err0_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2604 | .en (nresum_err_tail_wr_g[0]), |
---|
2605 | .clk (clk), |
---|
2606 | .se (se), |
---|
2607 | .si (), |
---|
2608 | .so () |
---|
2609 | ); |
---|
2610 | // |
---|
2611 | // thread 1 |
---|
2612 | // |
---|
2613 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo1_head ( |
---|
2614 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2615 | .q (cpu_mondo1_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2616 | .en (cpu_mondo_head_wr_g[1]), |
---|
2617 | .clk (clk), |
---|
2618 | .se (se), |
---|
2619 | .si (), |
---|
2620 | .so () |
---|
2621 | ); |
---|
2622 | |
---|
2623 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo1_tail ( |
---|
2624 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2625 | .q (cpu_mondo1_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2626 | .en (cpu_mondo_tail_wr_g[1]), |
---|
2627 | .clk (clk), |
---|
2628 | .se (se), |
---|
2629 | .si (), |
---|
2630 | .so () |
---|
2631 | ); |
---|
2632 | |
---|
2633 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo1_head ( |
---|
2634 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2635 | .q (dev_mondo1_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2636 | .en (dev_mondo_head_wr_g[1]), |
---|
2637 | .clk (clk), |
---|
2638 | .se (se), |
---|
2639 | .si (), |
---|
2640 | .so () |
---|
2641 | ); |
---|
2642 | |
---|
2643 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo1_tail ( |
---|
2644 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2645 | .q (dev_mondo1_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2646 | .en (dev_mondo_tail_wr_g[1]), |
---|
2647 | .clk (clk), |
---|
2648 | .se (se), |
---|
2649 | .si (), |
---|
2650 | .so () |
---|
2651 | ); |
---|
2652 | |
---|
2653 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err1_head ( |
---|
2654 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2655 | .q (resum_err1_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2656 | .en (resum_err_head_wr_g[1]), |
---|
2657 | .clk (clk), |
---|
2658 | .se (se), |
---|
2659 | .si (), |
---|
2660 | .so () |
---|
2661 | ); |
---|
2662 | |
---|
2663 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err1_tail ( |
---|
2664 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2665 | .q (resum_err1_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2666 | .en (resum_err_tail_wr_g[1]), |
---|
2667 | .clk (clk), |
---|
2668 | .se (se), |
---|
2669 | .si (), |
---|
2670 | .so () |
---|
2671 | ); |
---|
2672 | |
---|
2673 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err1_head ( |
---|
2674 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2675 | .q (nresum_err1_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2676 | .en (nresum_err_head_wr_g[1]), |
---|
2677 | .clk (clk), |
---|
2678 | .se (se), |
---|
2679 | .si (), |
---|
2680 | .so () |
---|
2681 | ); |
---|
2682 | |
---|
2683 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err1_tail ( |
---|
2684 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2685 | .q (nresum_err1_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2686 | .en (nresum_err_tail_wr_g[1]), |
---|
2687 | .clk (clk), |
---|
2688 | .se (se), |
---|
2689 | .si (), |
---|
2690 | .so () |
---|
2691 | ); |
---|
2692 | // |
---|
2693 | // thread 2 |
---|
2694 | // |
---|
2695 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo2_head ( |
---|
2696 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2697 | .q (cpu_mondo2_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2698 | .en (cpu_mondo_head_wr_g[2]), |
---|
2699 | .clk (clk), |
---|
2700 | .se (se), |
---|
2701 | .si (), |
---|
2702 | .so () |
---|
2703 | ); |
---|
2704 | |
---|
2705 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo2_tail ( |
---|
2706 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2707 | .q (cpu_mondo2_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2708 | .en (cpu_mondo_tail_wr_g[2]), |
---|
2709 | .clk (clk), |
---|
2710 | .se (se), |
---|
2711 | .si (), |
---|
2712 | .so () |
---|
2713 | ); |
---|
2714 | |
---|
2715 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo2_head ( |
---|
2716 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2717 | .q (dev_mondo2_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2718 | .en (dev_mondo_head_wr_g[2]), |
---|
2719 | .clk (clk), |
---|
2720 | .se (se), |
---|
2721 | .si (), |
---|
2722 | .so () |
---|
2723 | ); |
---|
2724 | |
---|
2725 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo2_tail ( |
---|
2726 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2727 | .q (dev_mondo2_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2728 | .en (dev_mondo_tail_wr_g[2]), |
---|
2729 | .clk (clk), |
---|
2730 | .se (se), |
---|
2731 | .si (), |
---|
2732 | .so () |
---|
2733 | ); |
---|
2734 | |
---|
2735 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err2_head ( |
---|
2736 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2737 | .q (resum_err2_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2738 | .en (resum_err_head_wr_g[2]), |
---|
2739 | .clk (clk), |
---|
2740 | .se (se), |
---|
2741 | .si (), |
---|
2742 | .so () |
---|
2743 | ); |
---|
2744 | |
---|
2745 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err2_tail ( |
---|
2746 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2747 | .q (resum_err2_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2748 | .en (resum_err_tail_wr_g[2]), |
---|
2749 | .clk (clk), |
---|
2750 | .se (se), |
---|
2751 | .si (), |
---|
2752 | .so () |
---|
2753 | ); |
---|
2754 | |
---|
2755 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err2_head ( |
---|
2756 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2757 | .q (nresum_err2_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2758 | .en (nresum_err_head_wr_g[2]), |
---|
2759 | .clk (clk), |
---|
2760 | .se (se), |
---|
2761 | .si (), |
---|
2762 | .so () |
---|
2763 | ); |
---|
2764 | |
---|
2765 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err2_tail ( |
---|
2766 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2767 | .q (nresum_err2_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2768 | .en (nresum_err_tail_wr_g[2]), |
---|
2769 | .clk (clk), |
---|
2770 | .se (se), |
---|
2771 | .si (), |
---|
2772 | .so () |
---|
2773 | ); |
---|
2774 | // |
---|
2775 | // thread 3 |
---|
2776 | // |
---|
2777 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo3_head ( |
---|
2778 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2779 | .q (cpu_mondo3_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2780 | .en (cpu_mondo_head_wr_g[3]), |
---|
2781 | .clk (clk), |
---|
2782 | .se (se), |
---|
2783 | .si (), |
---|
2784 | .so () |
---|
2785 | ); |
---|
2786 | |
---|
2787 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_cpu_mondo3_tail ( |
---|
2788 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2789 | .q (cpu_mondo3_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2790 | .en (cpu_mondo_tail_wr_g[3]), |
---|
2791 | .clk (clk), |
---|
2792 | .se (se), |
---|
2793 | .si (), |
---|
2794 | .so () |
---|
2795 | ); |
---|
2796 | |
---|
2797 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo3_head ( |
---|
2798 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2799 | .q (dev_mondo3_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2800 | .en (dev_mondo_head_wr_g[3]), |
---|
2801 | .clk (clk), |
---|
2802 | .se (se), |
---|
2803 | .si (), |
---|
2804 | .so () |
---|
2805 | ); |
---|
2806 | |
---|
2807 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_dev_mondo3_tail ( |
---|
2808 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2809 | .q (dev_mondo3_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2810 | .en (dev_mondo_tail_wr_g[3]), |
---|
2811 | .clk (clk), |
---|
2812 | .se (se), |
---|
2813 | .si (), |
---|
2814 | .so () |
---|
2815 | ); |
---|
2816 | |
---|
2817 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err3_head ( |
---|
2818 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2819 | .q (resum_err3_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2820 | .en (resum_err_head_wr_g[3]), |
---|
2821 | .clk (clk), |
---|
2822 | .se (se), |
---|
2823 | .si (), |
---|
2824 | .so () |
---|
2825 | ); |
---|
2826 | |
---|
2827 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_resum_err3_tail ( |
---|
2828 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2829 | .q (resum_err3_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2830 | .en (resum_err_tail_wr_g[3]), |
---|
2831 | .clk (clk), |
---|
2832 | .se (se), |
---|
2833 | .si (), |
---|
2834 | .so () |
---|
2835 | ); |
---|
2836 | |
---|
2837 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err3_head ( |
---|
2838 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2839 | .q (nresum_err3_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2840 | .en (nresum_err_head_wr_g[3]), |
---|
2841 | .clk (clk), |
---|
2842 | .se (se), |
---|
2843 | .si (), |
---|
2844 | .so () |
---|
2845 | ); |
---|
2846 | |
---|
2847 | dffe_s #(`TLU_ASI_QUE_WIDTH) dffe_nresum_err3_tail ( |
---|
2848 | .din (tlu_asi_queue_data_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2849 | .q (nresum_err3_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2850 | .en (nresum_err_tail_wr_g[3]), |
---|
2851 | .clk (clk), |
---|
2852 | .se (se), |
---|
2853 | .si (), |
---|
2854 | .so () |
---|
2855 | ); |
---|
2856 | // |
---|
2857 | // reading out the asi queues |
---|
2858 | // |
---|
2859 | // added for bug2332 |
---|
2860 | // assign cpu_mondo_hd_onehot_g = |
---|
2861 | // ~(|cpu_mondo_head_rd_g[3:1]); |
---|
2862 | // cpu_mondo_head |
---|
2863 | mux4ds #(`TLU_ASI_QUE_WIDTH) mx_cpu_mondo_head ( |
---|
2864 | .in0 (cpu_mondo0_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2865 | .in1 (cpu_mondo1_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2866 | .in2 (cpu_mondo2_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2867 | .in3 (cpu_mondo3_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2868 | .sel0 (cpu_mondo_head_rd_g[0]), |
---|
2869 | .sel1 (cpu_mondo_head_rd_g[1]), |
---|
2870 | .sel2 (cpu_mondo_head_rd_g[2]), |
---|
2871 | .sel3 (cpu_mondo_head_rd_g[3]), |
---|
2872 | .dout (cpu_mondo_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0]) |
---|
2873 | ); |
---|
2874 | // |
---|
2875 | // added for bug2332 |
---|
2876 | // assign cpu_mondo_ta_onehot_g = |
---|
2877 | // ~(|cpu_mondo_tail_rd_g[3:1]); |
---|
2878 | // cpu_mondo_tail |
---|
2879 | mux4ds #(`TLU_ASI_QUE_WIDTH) mx_cpu_mondo_tail ( |
---|
2880 | .in0 (cpu_mondo0_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2881 | .in1 (cpu_mondo1_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2882 | .in2 (cpu_mondo2_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2883 | .in3 (cpu_mondo3_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2884 | .sel0 (cpu_mondo_tail_rd_g[0]), |
---|
2885 | .sel1 (cpu_mondo_tail_rd_g[1]), |
---|
2886 | .sel2 (cpu_mondo_tail_rd_g[2]), |
---|
2887 | .sel3 (cpu_mondo_tail_rd_g[3]), |
---|
2888 | .dout (cpu_mondo_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0]) |
---|
2889 | ); |
---|
2890 | // |
---|
2891 | // added for bug2332 |
---|
2892 | // assign dev_mondo_hd_onehot_g = |
---|
2893 | // ~(|dev_mondo_head_rd_g[3:1]); |
---|
2894 | // dev_mondo_head |
---|
2895 | mux4ds #(`TLU_ASI_QUE_WIDTH) mx_dev_mondo_head ( |
---|
2896 | .in0 (dev_mondo0_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2897 | .in1 (dev_mondo1_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2898 | .in2 (dev_mondo2_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2899 | .in3 (dev_mondo3_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2900 | .sel0 (dev_mondo_head_rd_g[0]), |
---|
2901 | .sel1 (dev_mondo_head_rd_g[1]), |
---|
2902 | .sel2 (dev_mondo_head_rd_g[2]), |
---|
2903 | .sel3 (dev_mondo_head_rd_g[3]), |
---|
2904 | .dout (dev_mondo_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0]) |
---|
2905 | ); |
---|
2906 | // |
---|
2907 | // added for bug2332 |
---|
2908 | // assign dev_mondo_ta_onehot_g = |
---|
2909 | // ~(|dev_mondo_tail_rd_g[3:1]); |
---|
2910 | // dev_mondo_tail |
---|
2911 | mux4ds #(`TLU_ASI_QUE_WIDTH) mx_dev_mondo_tail ( |
---|
2912 | .in0 (dev_mondo0_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2913 | .in1 (dev_mondo1_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2914 | .in2 (dev_mondo2_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2915 | .in3 (dev_mondo3_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2916 | .sel0 (dev_mondo_tail_rd_g[0]), |
---|
2917 | .sel1 (dev_mondo_tail_rd_g[1]), |
---|
2918 | .sel2 (dev_mondo_tail_rd_g[2]), |
---|
2919 | .sel3 (dev_mondo_tail_rd_g[3]), |
---|
2920 | .dout (dev_mondo_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0]) |
---|
2921 | ); |
---|
2922 | // |
---|
2923 | // added for bug2332 |
---|
2924 | // assign resum_err_hd_onehot_g = |
---|
2925 | // ~(|resum_err_head_rd_g[3:1]); |
---|
2926 | // resum_err_head |
---|
2927 | mux4ds #(`TLU_ASI_QUE_WIDTH) mx_resum_err_head ( |
---|
2928 | .in0 (resum_err0_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2929 | .in1 (resum_err1_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2930 | .in2 (resum_err2_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2931 | .in3 (resum_err3_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2932 | .sel0 (resum_err_head_rd_g[0]), |
---|
2933 | .sel1 (resum_err_head_rd_g[1]), |
---|
2934 | .sel2 (resum_err_head_rd_g[2]), |
---|
2935 | .sel3 (resum_err_head_rd_g[3]), |
---|
2936 | .dout (resum_err_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0]) |
---|
2937 | ); |
---|
2938 | // |
---|
2939 | // added for bug2332 |
---|
2940 | // assign resum_err_ta_onehot_g = |
---|
2941 | // ~(|resum_err_tail_rd_g[3:1]); |
---|
2942 | // resum_err_tail |
---|
2943 | mux4ds #(`TLU_ASI_QUE_WIDTH) mx_resum_err_tail ( |
---|
2944 | .in0 (resum_err0_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2945 | .in1 (resum_err1_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2946 | .in2 (resum_err2_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2947 | .in3 (resum_err3_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2948 | .sel0 (resum_err_tail_rd_g[0]), |
---|
2949 | .sel1 (resum_err_tail_rd_g[1]), |
---|
2950 | .sel2 (resum_err_tail_rd_g[2]), |
---|
2951 | .sel3 (resum_err_tail_rd_g[3]), |
---|
2952 | .dout (resum_err_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0]) |
---|
2953 | ); |
---|
2954 | // |
---|
2955 | // added for bug2332 |
---|
2956 | // assign nresum_err_hd_onehot_g = |
---|
2957 | // ~(|nresum_err_head_rd_g[3:1]); |
---|
2958 | // nresum_err_head |
---|
2959 | mux4ds #(`TLU_ASI_QUE_WIDTH) mx_nresum_err_head ( |
---|
2960 | .in0 (nresum_err0_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2961 | .in1 (nresum_err1_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2962 | .in2 (nresum_err2_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2963 | .in3 (nresum_err3_head[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2964 | .sel0 (nresum_err_head_rd_g[0]), |
---|
2965 | .sel1 (nresum_err_head_rd_g[1]), |
---|
2966 | .sel2 (nresum_err_head_rd_g[2]), |
---|
2967 | .sel3 (nresum_err_head_rd_g[3]), |
---|
2968 | .dout (nresum_err_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0]) |
---|
2969 | ); |
---|
2970 | // |
---|
2971 | // added for bug2332 |
---|
2972 | // assign nresum_err_ta_onehot_g = |
---|
2973 | // ~(|nresum_err_tail_rd_g[3:1]); |
---|
2974 | // nresum_err_tail |
---|
2975 | mux4ds #(`TLU_ASI_QUE_WIDTH) mx_nresum_err_tail ( |
---|
2976 | .in0 (nresum_err0_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2977 | .in1 (nresum_err1_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2978 | .in2 (nresum_err2_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2979 | .in3 (nresum_err3_tail[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2980 | .sel0 (nresum_err_tail_rd_g[0]), |
---|
2981 | .sel1 (nresum_err_tail_rd_g[1]), |
---|
2982 | .sel2 (nresum_err_tail_rd_g[2]), |
---|
2983 | .sel3 (nresum_err_tail_rd_g[3]), |
---|
2984 | .dout (nresum_err_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0]) |
---|
2985 | ); |
---|
2986 | // |
---|
2987 | // added for bug 2332 |
---|
2988 | assign asi_qrdata_mx1_sel[0] = cpu_mondo_hd_rd_g | |
---|
2989 | ~(|asi_qrdata_mx1_sel[3:1]); |
---|
2990 | assign asi_qrdata_mx1_sel[1] = cpu_mondo_ta_rd_g; |
---|
2991 | assign asi_qrdata_mx1_sel[2] = dev_mondo_hd_rd_g; |
---|
2992 | assign asi_qrdata_mx1_sel[3] = dev_mondo_ta_rd_g; |
---|
2993 | // |
---|
2994 | // selecting between the eight queues |
---|
2995 | mux4ds #(`TLU_ASI_QUE_WIDTH) mx1_asi_queue_rdata ( |
---|
2996 | .in0 (cpu_mondo_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2997 | .in1 (cpu_mondo_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2998 | .in2 (dev_mondo_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
2999 | .in3 (dev_mondo_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
3000 | .sel0 (asi_qrdata_mx1_sel[0]), |
---|
3001 | .sel1 (asi_qrdata_mx1_sel[1]), |
---|
3002 | .sel2 (asi_qrdata_mx1_sel[2]), |
---|
3003 | .sel3 (asi_qrdata_mx1_sel[3]), |
---|
3004 | .dout (asi_queue_rdata1_g[`TLU_ASI_QUE_WIDTH-1:0]) |
---|
3005 | ); |
---|
3006 | // |
---|
3007 | // added for bug 2332 |
---|
3008 | assign asi_qrdata_mx2_sel[0] = resum_err_hd_rd_g | |
---|
3009 | ~(|asi_qrdata_mx2_sel[3:1]); |
---|
3010 | assign asi_qrdata_mx2_sel[1] = resum_err_ta_rd_g; |
---|
3011 | assign asi_qrdata_mx2_sel[2] = nresum_err_hd_rd_g; |
---|
3012 | assign asi_qrdata_mx2_sel[3] = nresum_err_ta_rd_g; |
---|
3013 | |
---|
3014 | mux4ds #(`TLU_ASI_QUE_WIDTH) mx2_asi_queue_rdata ( |
---|
3015 | .in0 (resum_err_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
3016 | .in1 (resum_err_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
3017 | .in2 (nresum_err_hd_rdata[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
3018 | .in3 (nresum_err_ta_rdata[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
3019 | .sel0 (asi_qrdata_mx2_sel[0]), |
---|
3020 | .sel1 (asi_qrdata_mx2_sel[1]), |
---|
3021 | .sel2 (asi_qrdata_mx2_sel[2]), |
---|
3022 | .sel3 (asi_qrdata_mx2_sel[3]), |
---|
3023 | .dout (asi_queue_rdata2_g[`TLU_ASI_QUE_WIDTH-1:0]) |
---|
3024 | ); |
---|
3025 | // |
---|
3026 | // constructing the select for the final asi queue rdata output |
---|
3027 | assign asi_qrdata_mx_sel2 = |
---|
3028 | resum_err_hd_rd_g | resum_err_ta_rd_g | |
---|
3029 | nresum_err_hd_rd_g | nresum_err_ta_rd_g; |
---|
3030 | // |
---|
3031 | mux2ds #(`TLU_ASI_QUE_WIDTH) mx_tlu_asi_queue_rdata ( |
---|
3032 | .in0 (asi_queue_rdata2_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
3033 | .in1 (asi_queue_rdata1_g[`TLU_ASI_QUE_WIDTH-1:0]), |
---|
3034 | .sel0 (asi_qrdata_mx_sel2), |
---|
3035 | .sel1 (~asi_qrdata_mx_sel2), |
---|
3036 | .dout (tlu_asi_queue_rdata_g[`TLU_ASI_QUE_WIDTH-1:0]) |
---|
3037 | ); |
---|
3038 | // |
---|
3039 | // forming the valid signal for the asi queue rdata |
---|
3040 | assign tlu_asi_queue_rd_vld_g = |
---|
3041 | asi_qrdata_mx_sel2 | cpu_mondo_hd_rd_g | cpu_mondo_ta_rd_g | |
---|
3042 | dev_mondo_hd_rd_g | dev_mondo_ta_rd_g; |
---|
3043 | |
---|
3044 | assign tlu_ld_data_vld_g = asi_ld_addr_vld_g; |
---|
3045 | |
---|
3046 | //////////////////////////////////////////////////////////////////////// |
---|
3047 | // SCPD and HSCPD control logic |
---|
3048 | //////////////////////////////////////////////////////////////////////// |
---|
3049 | // |
---|
3050 | // privileged scratch pad access |
---|
3051 | assign asi_scpd_rw_e = |
---|
3052 | ifu_lsu_alt_space_e & |
---|
3053 | (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]==`PRI_SCPD_ASI_STATE); |
---|
3054 | |
---|
3055 | // hyprivileged scratch pad access |
---|
3056 | assign asi_hscpd_rw_e = |
---|
3057 | ifu_lsu_alt_space_e & |
---|
3058 | (tlu_asi_state_e[`TLU_ASI_STATE_WIDTH-1:0]==`HPRI_SCPD_ASI_STATE); |
---|
3059 | // |
---|
3060 | // staged the scpd/hscpd rw ctls |
---|
3061 | dffr_s #(2) dffr_asi_scpd_rw_ctls ( |
---|
3062 | .din ({asi_hscpd_rw_e, asi_scpd_rw_e}), |
---|
3063 | .q ({asi_hscpd_rw_m, asi_scpd_rw_m}), |
---|
3064 | .rst (local_rst), |
---|
3065 | .clk (clk), |
---|
3066 | .se (se), |
---|
3067 | .si (), |
---|
3068 | .so () |
---|
3069 | ); |
---|
3070 | |
---|
3071 | // address generation |
---|
3072 | // |
---|
3073 | // modified due to timing fix |
---|
3074 | /* |
---|
3075 | assign scpd_addr_va_e[`SCPD_ASI_VA_ADDR_WIDTH-1:0] = |
---|
3076 | tlu_ldst_va_e[`TLU_ASI_SCPD_VA_HI:`TLU_ASI_SCPD_VA_LO]; |
---|
3077 | |
---|
3078 | staged the shifted va address |
---|
3079 | modified due to timing fix |
---|
3080 | |
---|
3081 | dff_s #(`SCPD_ASI_VA_ADDR_WIDTH) dff_scpd_addr_va_m ( |
---|
3082 | .din (scpd_addr_va_e[`SCPD_ASI_VA_ADDR_WIDTH-1:0]), |
---|
3083 | .q (scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0]), |
---|
3084 | .clk (clk), |
---|
3085 | .se (se), |
---|
3086 | .si (), |
---|
3087 | .so () |
---|
3088 | ); |
---|
3089 | */ |
---|
3090 | |
---|
3091 | assign scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0] = |
---|
3092 | tlu_ldst_va_m[`TLU_ASI_SCPD_VA_HI:`TLU_ASI_SCPD_VA_LO]; |
---|
3093 | |
---|
3094 | dff_s #(`SCPD_ASI_VA_ADDR_WIDTH) dff_scpd_addr_va_g ( |
---|
3095 | .din (scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0]), |
---|
3096 | .q (scpd_addr_va_g[`SCPD_ASI_VA_ADDR_WIDTH-1:0]), |
---|
3097 | .clk (clk), |
---|
3098 | .se (se), |
---|
3099 | .si (), |
---|
3100 | .so () |
---|
3101 | ); |
---|
3102 | |
---|
3103 | assign tlu_scpd_rd_addr_m[`SCPD_RW_ADDR_WIDTH-1:0] = |
---|
3104 | {thrid_m[1:0], scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0]}; |
---|
3105 | |
---|
3106 | assign tlu_scpd_wr_addr_g[`SCPD_RW_ADDR_WIDTH-1:0] = |
---|
3107 | {thrid_g[1:0], scpd_addr_va_g[`SCPD_ASI_VA_ADDR_WIDTH-1:0]}; |
---|
3108 | // |
---|
3109 | // illegal range check for scratch-pd va |
---|
3110 | // modified due to timing |
---|
3111 | /* |
---|
3112 | assign scpd_ill_va_e = |
---|
3113 | (ifu_lsu_alt_space_e)? |
---|
3114 | ((asi_scpd_rw_e | asi_hscpd_rw_e) & |
---|
3115 | ((|exu_lsu_ldst_va_e[`ASI_VA_WIDTH-1:`TLU_ASI_SCPD_VA_HI+1]) | |
---|
3116 | (|exu_lsu_ldst_va_e[`TLU_ASI_SCPD_VA_LO-1:0]))) : |
---|
3117 | 1'b0; |
---|
3118 | // staged illegal va range |
---|
3119 | dffr_s dffr_scpd_ill_va_m ( |
---|
3120 | .din (scpd_ill_va_e), |
---|
3121 | .q (scpd_ill_va_m), |
---|
3122 | .rst (local_rst), |
---|
3123 | .clk (clk), |
---|
3124 | .se (se), |
---|
3125 | .si (), |
---|
3126 | .so () |
---|
3127 | ); |
---|
3128 | */ |
---|
3129 | // |
---|
3130 | assign va_not_baligned_m = (|tlu_ldst_va_m[`TLU_ASI_SCPD_VA_LO-1:0]); |
---|
3131 | assign scpd_ill_va_m = |
---|
3132 | (asi_scpd_rw_m | asi_hscpd_rw_m) & |
---|
3133 | va_not_baligned_m; |
---|
3134 | |
---|
3135 | // |
---|
3136 | dffr_s dffr_scpd_ill_va_g ( |
---|
3137 | .din (scpd_ill_va_m), |
---|
3138 | .q (scpd_ill_va_g), |
---|
3139 | .rst (local_rst), |
---|
3140 | .clk (clk), |
---|
3141 | .se (se), |
---|
3142 | .si (), |
---|
3143 | .so () |
---|
3144 | ); |
---|
3145 | // |
---|
3146 | // generating read and write valid |
---|
3147 | assign asi_scpd_rw_vld_m = |
---|
3148 | (asi_scpd_rw_m | asi_hscpd_rw_m) & |
---|
3149 | ~(hscpd_data_acc_excpt_m | va_not_baligned_m); |
---|
3150 | |
---|
3151 | dffr_s dffr_asi_scpd_rw_vld_g ( |
---|
3152 | .din (asi_scpd_rw_vld_m), |
---|
3153 | .q (asi_scpd_rw_vld_g), |
---|
3154 | .rst (local_rst), |
---|
3155 | .clk (clk), |
---|
3156 | .se (se), |
---|
3157 | .si (), |
---|
3158 | .so () |
---|
3159 | ); |
---|
3160 | |
---|
3161 | assign tlu_scpd_wr_vld_g = |
---|
3162 | asi_queue_write_g & asi_scpd_rw_vld_g; |
---|
3163 | // |
---|
3164 | // control to the memory macro for the read |
---|
3165 | // modified due to timing |
---|
3166 | assign tlu_scpd_rd_vld_m = |
---|
3167 | // asi_queue_read_m & asi_scpd_rw_vld_m; |
---|
3168 | asi_queue_read_pq_m & asi_scpd_rw_vld_m; |
---|
3169 | // |
---|
3170 | // control to the int block for the selection of read data |
---|
3171 | // replaced by queue vld |
---|
3172 | // assign tlu_scpd_rd_vld_g = |
---|
3173 | // asi_queue_read_g & asi_scpd_rw_vld_g; |
---|
3174 | |
---|
3175 | // decoding for hypervisor only scratch-pad |
---|
3176 | assign hscpd_va_rw_m = |
---|
3177 | ((scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0] == |
---|
3178 | `HSCPD_ASI_VA_ADDR_LO) | |
---|
3179 | (scpd_addr_va_m[`SCPD_ASI_VA_ADDR_WIDTH-1:0] == |
---|
3180 | `HSCPD_ASI_VA_ADDR_HI)); |
---|
3181 | |
---|
3182 | //////////////////////////////////////////////////////////////////////// |
---|
3183 | // Potential trap indicators |
---|
3184 | //////////////////////////////////////////////////////////////////////// |
---|
3185 | // possible traps are: |
---|
3186 | // 1) head ptr <> tail ptr (with the exception of nresum_err_queue) |
---|
3187 | // 2) write to tail by supervisor - data_access_exception |
---|
3188 | |
---|
3189 | // |
---|
3190 | // write to hypervisor scratch-pad using 0x20 ASI state |
---|
3191 | |
---|
3192 | assign hscpd_priv_asi_acc_m = |
---|
3193 | hscpd_va_rw_m & asi_scpd_rw_m; |
---|
3194 | |
---|
3195 | // modified due to timing - moved the inst_vld qualification to tlu_tcl |
---|
3196 | assign hscpd_data_acc_excpt_pq_m = |
---|
3197 | hscpd_priv_asi_acc_m & |
---|
3198 | (asi_queue_write_pq_m | asi_queue_read_pq_m); |
---|
3199 | /* |
---|
3200 | hscpd_priv_asi_acc_m & |
---|
3201 | // (asi_queue_write_m | asi_queue_read_m) & |
---|
3202 | (asi_queue_write_pq_m | asi_queue_read_pq_m) & |
---|
3203 | ((thread_sel_id_m[0] & ~tlu_hyper_lite[0]) | |
---|
3204 | (thread_sel_id_m[1] & ~tlu_hyper_lite[1]) | |
---|
3205 | (thread_sel_id_m[2] & ~tlu_hyper_lite[2]) | |
---|
3206 | (thread_sel_id_m[3] & ~tlu_hyper_lite[3])); |
---|
3207 | */ |
---|
3208 | // |
---|
3209 | // data_access_exception to access the hyper-privileged scratch-pad |
---|
3210 | |
---|
3211 | assign tlu_hscpd_dacc_excpt_m = hscpd_data_acc_excpt_pq_m; |
---|
3212 | // |
---|
3213 | // revised for bug 3586 |
---|
3214 | |
---|
3215 | assign hscpd_data_acc_excpt_m = |
---|
3216 | hscpd_data_acc_excpt_pq_m & |
---|
3217 | ((thread_sel_id_m[0] & ~tlu_hyper_lite[0]) | |
---|
3218 | (thread_sel_id_m[1] & ~tlu_hyper_lite[1]) | |
---|
3219 | (thread_sel_id_m[2] & ~tlu_hyper_lite[2]) | |
---|
3220 | (thread_sel_id_m[3] & ~tlu_hyper_lite[3])); |
---|
3221 | |
---|
3222 | // illegal va range indicator |
---|
3223 | assign tlu_va_ill_g = |
---|
3224 | (que_ill_va_g | scpd_ill_va_g) & asi_queue_read_g; |
---|
3225 | |
---|
3226 | // load instruction valid - scpd or asi queue |
---|
3227 | assign asi_ld_addr_vld_m = |
---|
3228 | asi_queue_read_m & (asi_queue_rw_m | |
---|
3229 | ((asi_hscpd_rw_m | asi_scpd_rw_m) & |
---|
3230 | ~hscpd_data_acc_excpt_m)); |
---|
3231 | |
---|
3232 | // staging the ld address valid |
---|
3233 | dffr_s dffr_asi_ld_addr_vld_g ( |
---|
3234 | .din (asi_ld_addr_vld_m), |
---|
3235 | .q (asi_ld_addr_vld_g), |
---|
3236 | .rst (local_rst), |
---|
3237 | .clk (clk), |
---|
3238 | .se (se), |
---|
3239 | .si (), |
---|
3240 | .so () |
---|
3241 | ); |
---|
3242 | // |
---|
3243 | // redefined va illegal checking - the following code is |
---|
3244 | // no longer necessary |
---|
3245 | // zero va range detector |
---|
3246 | /* |
---|
3247 | assign va_all_zero_e = |
---|
3248 | (~(|exu_lsu_ldst_va_e[`ASI_VA_WIDTH-1:0])) & |
---|
3249 | asi_queue_read_g; |
---|
3250 | // |
---|
3251 | // staged illegal va range |
---|
3252 | dffr_s dffr_va_all_zero_m ( |
---|
3253 | .din (va_all_zero_e), |
---|
3254 | .q (va_all_zero_m), |
---|
3255 | .rst (local_rst), |
---|
3256 | .clk (clk), |
---|
3257 | .se (se), |
---|
3258 | .si (), |
---|
3259 | .so () |
---|
3260 | ); |
---|
3261 | // |
---|
3262 | dffr_s dffr_va_all_zero_g ( |
---|
3263 | .din (va_all_zero_m), |
---|
3264 | .q (va_all_zero_g), |
---|
3265 | .rst (local_rst), |
---|
3266 | .clk (clk), |
---|
3267 | .se (se), |
---|
3268 | .si (), |
---|
3269 | .so () |
---|
3270 | ); |
---|
3271 | |
---|
3272 | assign tlu_va_all_zero_g = va_all_zero_g; |
---|
3273 | */ |
---|
3274 | |
---|
3275 | //////////////////////////////////////////////////////////////////////// |
---|
3276 | // queue traps - head ptr <> tail ptr |
---|
3277 | //////////////////////////////////////////////////////////////////////// |
---|
3278 | // note: these traps are level-sensitive |
---|
3279 | // |
---|
3280 | // thread 0 |
---|
3281 | |
---|
3282 | assign tlu_cpu_mondo_cmp[0] = |
---|
3283 | (|(cpu_mondo0_head[`TLU_ASI_QUE_WIDTH-1:0] ^ |
---|
3284 | cpu_mondo0_tail[`TLU_ASI_QUE_WIDTH-1:0])); |
---|
3285 | assign tlu_dev_mondo_cmp[0]= |
---|
3286 | (|(dev_mondo0_head[`TLU_ASI_QUE_WIDTH-1:0] ^ |
---|
3287 | dev_mondo0_tail[`TLU_ASI_QUE_WIDTH-1:0])); |
---|
3288 | assign tlu_resum_err_cmp[0] = |
---|
3289 | (|(resum_err0_head[`TLU_ASI_QUE_WIDTH-1:0] ^ |
---|
3290 | resum_err0_tail[`TLU_ASI_QUE_WIDTH-1:0])); |
---|
3291 | // thread 1 |
---|
3292 | |
---|
3293 | assign tlu_cpu_mondo_cmp[1] = |
---|
3294 | (|(cpu_mondo1_head[`TLU_ASI_QUE_WIDTH-1:0] ^ |
---|
3295 | cpu_mondo1_tail[`TLU_ASI_QUE_WIDTH-1:0])); |
---|
3296 | assign tlu_dev_mondo_cmp[1]= |
---|
3297 | (|(dev_mondo1_head[`TLU_ASI_QUE_WIDTH-1:0] ^ |
---|
3298 | dev_mondo1_tail[`TLU_ASI_QUE_WIDTH-1:0])); |
---|
3299 | assign tlu_resum_err_cmp[1] = |
---|
3300 | (|(resum_err1_head[`TLU_ASI_QUE_WIDTH-1:0] ^ |
---|
3301 | resum_err1_tail[`TLU_ASI_QUE_WIDTH-1:0])); |
---|
3302 | // |
---|
3303 | // thread 2 |
---|
3304 | |
---|
3305 | assign tlu_cpu_mondo_cmp[2] = |
---|
3306 | (|(cpu_mondo2_head[`TLU_ASI_QUE_WIDTH-1:0] ^ |
---|
3307 | cpu_mondo2_tail[`TLU_ASI_QUE_WIDTH-1:0])); |
---|
3308 | assign tlu_dev_mondo_cmp[2]= |
---|
3309 | (|(dev_mondo2_head[`TLU_ASI_QUE_WIDTH-1:0] ^ |
---|
3310 | dev_mondo2_tail[`TLU_ASI_QUE_WIDTH-1:0])); |
---|
3311 | assign tlu_resum_err_cmp[2] = |
---|
3312 | (|(resum_err2_head[`TLU_ASI_QUE_WIDTH-1:0] ^ |
---|
3313 | resum_err2_tail[`TLU_ASI_QUE_WIDTH-1:0])); |
---|
3314 | // thread 3 |
---|
3315 | |
---|
3316 | assign tlu_cpu_mondo_cmp[3] = |
---|
3317 | (|(cpu_mondo3_head[`TLU_ASI_QUE_WIDTH-1:0] ^ |
---|
3318 | cpu_mondo3_tail[`TLU_ASI_QUE_WIDTH-1:0])); |
---|
3319 | assign tlu_dev_mondo_cmp[3]= |
---|
3320 | (|(dev_mondo3_head[`TLU_ASI_QUE_WIDTH-1:0] ^ |
---|
3321 | dev_mondo3_tail[`TLU_ASI_QUE_WIDTH-1:0])); |
---|
3322 | assign tlu_resum_err_cmp[3] = |
---|
3323 | (|(resum_err3_head[`TLU_ASI_QUE_WIDTH-1:0] ^ |
---|
3324 | resum_err3_tail[`TLU_ASI_QUE_WIDTH-1:0])); |
---|
3325 | |
---|
3326 | // write to tail by supervisor |
---|
3327 | // modified due to timing - moved the inst_vld qualification to tlu_tcl |
---|
3328 | assign qtail_write_m = |
---|
3329 | (nresum_err_tail_rw_m | resum_err_tail_rw_m | |
---|
3330 | cpu_mondo_tail_rw_m | dev_mondo_tail_rw_m) & |
---|
3331 | asi_queue_write_pq_m & asi_queue_rw_m; |
---|
3332 | // asi_queue_write_m & asi_queue_rw_m; |
---|
3333 | |
---|
3334 | // |
---|
3335 | // modified for timing - qualification moved to tcl |
---|
3336 | assign tlu_qtail_dacc_excpt_m = qtail_write_m; |
---|
3337 | /* |
---|
3338 | ((thread_sel_id_m[0] & que_trap_en[0] & tlu_pstate_priv[0]) | |
---|
3339 | (thread_sel_id_m[1] & que_trap_en[1] & tlu_pstate_priv[1]) | |
---|
3340 | (thread_sel_id_m[2] & que_trap_en[2] & tlu_pstate_priv[2]) | |
---|
3341 | (thread_sel_id_m[3] & que_trap_en[3] & tlu_pstate_priv[3])) & |
---|
3342 | qtail_write_m; |
---|
3343 | */ |
---|
3344 | |
---|
3345 | endmodule |
---|