| 1 | // ========== Copyright Header Begin ========================================== |
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| 2 | // |
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| 3 | // OpenSPARC T1 Processor File: fpu_add.v |
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| 4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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| 5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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| 6 | // |
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| 7 | // The above named program is free software; you can redistribute it and/or |
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| 8 | // modify it under the terms of the GNU General Public |
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| 9 | // License version 2 as published by the Free Software Foundation. |
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| 10 | // |
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| 11 | // The above named program is distributed in the hope that it will be |
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| 12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | // General Public License for more details. |
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| 15 | // |
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| 16 | // You should have received a copy of the GNU General Public |
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| 17 | // License along with this work; if not, write to the Free Software |
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| 18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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| 19 | // |
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| 20 | // ========== Copyright Header End ============================================ |
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| 21 | /////////////////////////////////////////////////////////////////////////////// |
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| 22 | // |
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| 23 | // FPU add pipe. |
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| 24 | // |
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| 25 | /////////////////////////////////////////////////////////////////////////////// |
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| 26 | |
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| 27 | module fpu_add ( |
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| 28 | inq_op, |
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| 29 | inq_rnd_mode, |
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| 30 | inq_id, |
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| 31 | inq_fcc, |
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| 32 | inq_in1, |
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| 33 | inq_in1_50_0_neq_0, |
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| 34 | inq_in1_53_32_neq_0, |
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| 35 | inq_in1_exp_eq_0, |
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| 36 | inq_in1_exp_neq_ffs, |
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| 37 | inq_in2, |
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| 38 | inq_in2_50_0_neq_0, |
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| 39 | inq_in2_53_32_neq_0, |
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| 40 | inq_in2_exp_eq_0, |
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| 41 | inq_in2_exp_neq_ffs, |
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| 42 | inq_add, |
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| 43 | add_dest_rdy, |
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| 44 | fadd_clken_l, |
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| 45 | arst_l, |
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| 46 | grst_l, |
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| 47 | rclk, |
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| 48 | |
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| 49 | add_pipe_active, |
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| 50 | a1stg_step, |
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| 51 | a6stg_fadd_in, |
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| 52 | add_id_out_in, |
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| 53 | a6stg_fcmpop, |
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| 54 | add_exc_out, |
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| 55 | a6stg_dbl_dst, |
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| 56 | a6stg_sng_dst, |
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| 57 | a6stg_long_dst, |
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| 58 | a6stg_int_dst, |
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| 59 | add_sign_out, |
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| 60 | add_exp_out, |
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| 61 | add_frac_out, |
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| 62 | add_cc_out, |
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| 63 | add_fcc_out, |
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| 64 | |
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| 65 | se_add_exp, |
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| 66 | se_add_frac, |
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| 67 | si, |
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| 68 | so |
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| 69 | ); |
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| 70 | |
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| 71 | |
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| 72 | input [7:0] inq_op; // request opcode to op pipes |
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| 73 | input [1:0] inq_rnd_mode; // request rounding mode to op pipes |
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| 74 | input [4:0] inq_id; // request ID to the operation pipes |
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| 75 | input [1:0] inq_fcc; // request cc ID to op pipes |
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| 76 | input [63:0] inq_in1; // request operand 1 to op pipes |
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| 77 | input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0 |
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| 78 | input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0 |
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| 79 | input inq_in1_exp_eq_0; // request operand 1 exp==0 |
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| 80 | input inq_in1_exp_neq_ffs; // request operand 1 exp!=0xff's |
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| 81 | input [63:0] inq_in2; // request operand 2 to op pipes |
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| 82 | input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0 |
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| 83 | input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0 |
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| 84 | input inq_in2_exp_eq_0; // request operand 2 exp==0 |
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| 85 | input inq_in2_exp_neq_ffs; // request operand 2 exp!=0xff's |
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| 86 | input inq_add; // add pipe request |
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| 87 | input add_dest_rdy; // add result req accepted for CPX |
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| 88 | input fadd_clken_l; // fadd clock enable |
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| 89 | input arst_l; // global async. reset- asserted low |
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| 90 | input grst_l; // global sync. reset- asserted low |
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| 91 | input rclk; // global clock |
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| 92 | |
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| 93 | output add_pipe_active; // add pipe is executing a valid instr |
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| 94 | output a1stg_step; // add pipe load |
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| 95 | output a6stg_fadd_in; // add pipe output request next cycle |
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| 96 | output [9:0] add_id_out_in; // add pipe output ID next cycle |
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| 97 | output a6stg_fcmpop; // compare- add 6 stage |
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| 98 | output [4:0] add_exc_out; // add pipe result- exception flags |
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| 99 | output a6stg_dbl_dst; // float double result- add 6 stage |
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| 100 | output a6stg_sng_dst; // float single result- add 6 stage |
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| 101 | output a6stg_long_dst; // 64bit integer result- add 6 stage |
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| 102 | output a6stg_int_dst; // 32bit integer result- add 6 stage |
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| 103 | output add_sign_out; // add sign output |
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| 104 | output [10:0] add_exp_out; // add exponent output |
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| 105 | output [63:0] add_frac_out; // add fraction output |
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| 106 | output [1:0] add_cc_out; // add pipe result- condition |
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| 107 | output [1:0] add_fcc_out; // add pipe input fcc passed through |
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| 108 | |
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| 109 | input se_add_exp; // scan_enable for add_exp_dp, add_ctl |
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| 110 | input se_add_frac; // scan_enable for add_frac_dp |
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| 111 | input si; // scan in |
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| 112 | output so; // scan out |
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| 113 | |
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| 114 | |
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| 115 | /////////////////////////////////////////////////////////////////////////////// |
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| 116 | // |
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| 117 | // Outputs of fpu_add_ctl. |
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| 118 | // |
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| 119 | /////////////////////////////////////////////////////////////////////////////// |
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| 120 | |
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| 121 | wire a1stg_denorm_sng_in1; // select line to normalized fraction 1 |
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| 122 | wire a1stg_denorm_dbl_in1; // select line to normalized fraction 1 |
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| 123 | wire a1stg_denorm_sng_in2; // select line to normalized fraction 2 |
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| 124 | wire a1stg_denorm_dbl_in2; // select line to normalized fraction 2 |
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| 125 | wire a1stg_norm_sng_in1; // select line to normalized fraction 1 |
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| 126 | wire a1stg_norm_dbl_in1; // select line to normalized fraction 1 |
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| 127 | wire a1stg_norm_sng_in2; // select line to normalized fraction 2 |
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| 128 | wire a1stg_norm_dbl_in2; // select line to normalized fraction 2 |
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| 129 | wire a1stg_step; // add pipe load |
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| 130 | wire a1stg_stepa; // add pipe load- copy |
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| 131 | wire a1stg_sngop; // single precision operation- add 1 stg |
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| 132 | wire a1stg_intlngop; // integer/long input- add 1 stage |
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| 133 | wire a1stg_fsdtoix; // float to integer convert- add 1 stg |
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| 134 | wire a1stg_fstod; // fstod- add 1 stage |
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| 135 | wire a1stg_fstoi; // fstoi- add 1 stage |
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| 136 | wire a1stg_fstox; // fstox- add 1 stage |
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| 137 | wire a1stg_fdtoi; // fdtoi- add 1 stage |
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| 138 | wire a1stg_fdtox; // fdtox- add 1 stage |
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| 139 | wire a1stg_faddsubs; // add/subtract single- add 1 stg |
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| 140 | wire a1stg_faddsubd; // add/subtract double- add 1 stg |
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| 141 | wire a1stg_fdtos; // fdtos- add 1 stage |
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| 142 | wire a2stg_faddsubop; // float add or subtract- add 2 stage |
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| 143 | wire a2stg_fsdtoix_fdtos; // float to integer convert- add 2 stg |
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| 144 | wire a2stg_fitos; // fitos- add 2 stage |
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| 145 | wire a2stg_fitod; // fitod- add 2 stage |
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| 146 | wire a2stg_fxtos; // fxtos- add 2 stage |
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| 147 | wire a2stg_fxtod; // fxtod- add 2 stage |
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| 148 | wire a3stg_faddsubop; // denorm compare lead0[10] input select |
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| 149 | wire [1:0] a3stg_faddsubopa; // denorm compare lead0[10] input select |
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| 150 | wire a4stg_dblop; // double precision operation- add 4 stg |
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| 151 | wire a6stg_fadd_in; // add pipe output request next cycle |
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| 152 | wire [9:0] add_id_out_in; // add pipe output ID next cycle |
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| 153 | wire [1:0] add_fcc_out; // add pipe input fcc passed through |
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| 154 | wire a6stg_dbl_dst; // float double result- add 6 stage |
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| 155 | wire a6stg_sng_dst; // float single result- add 6 stage |
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| 156 | wire a6stg_long_dst; // 64bit integer result- add 6 stage |
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| 157 | wire a6stg_int_dst; // 32bit integer result- add 6 stage |
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| 158 | wire a6stg_fcmpop; // compare- add 6 stage |
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| 159 | wire a6stg_step; // advance the add pipe |
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| 160 | wire a3stg_sub_in; // subtract in main adder- add 3 stage |
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| 161 | wire add_sign_out; // add sign output |
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| 162 | wire [1:0] add_cc_out; // add pipe result- condition |
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| 163 | wire a4stg_in_of; // add overflow- select exp out |
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| 164 | wire [4:0] add_exc_out; // add pipe result- exception flags |
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| 165 | wire a2stg_frac1_in_frac1; // select line to a2stg_frac1 |
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| 166 | wire a2stg_frac1_in_frac2; // select line to a2stg_frac1 |
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| 167 | wire a1stg_2nan_in_inv; // 2 NaN inputs- a1 stage |
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| 168 | wire a1stg_faddsubop_inv; // add/subtract- a1 stage |
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| 169 | wire a2stg_frac1_in_qnan; // make fraction 1 a QNaN |
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| 170 | wire a2stg_frac1_in_nv; // NV- make a new QNaN |
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| 171 | wire a2stg_frac1_in_nv_dbl; // NV- make a new double prec QNaN |
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| 172 | wire a2stg_frac2_in_frac1; // select line to a2stg_frac2 |
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| 173 | wire a2stg_frac2_in_qnan; // make fraction 2 a QNaN |
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| 174 | wire [5:0] a2stg_shr_cnt_in; // right shift count input- add 1 stage |
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| 175 | wire a2stg_shr_cnt_5_inv_in; // right shift count input[5]- add 1 stg |
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| 176 | wire a2stg_shr_frac2_shr_int; // select line to a3stg_frac2 |
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| 177 | wire a2stg_shr_frac2_shr_dbl; // select line to a3stg_frac2 |
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| 178 | wire a2stg_shr_frac2_shr_sng; // select line to a3stg_frac2 |
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| 179 | wire a2stg_shr_frac2_max; // select line to a3stg_frac2 |
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| 180 | wire a2stg_sub_step; // select line to a3stg_frac2 |
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| 181 | wire a2stg_fracadd_frac2_inv_in; // sel line to main adder input 2 |
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| 182 | wire a2stg_fracadd_frac2_inv_shr1_in; // sel line to main adder in 2 |
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| 183 | wire a2stg_fracadd_frac2; // select line to main adder input 2 |
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| 184 | wire a2stg_fracadd_cin_in; // carry in to main adder- add 1 stage |
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| 185 | wire a3stg_exp_7ff; // select line to a3stg_exp |
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| 186 | wire a3stg_exp_ff; // select line to a3stg_exp |
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| 187 | wire a3stg_exp_add; // select line to a3stg_exp |
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| 188 | wire a2stg_expdec_neq_0; // exponent will be < 54 |
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| 189 | wire a3stg_exp10_0_eq0; // exponent[10:0]==0- add 3 stage |
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| 190 | wire a3stg_exp10_1_eq0; // exponent[10:1]==0- add 3 stage |
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| 191 | wire a3stg_fdtos_inv; // double to single convert- add 3 stg |
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| 192 | wire a4stg_fixtos_fxtod_inv; // int to single/double cvt- add 4 stg |
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| 193 | wire a4stg_rnd_frac_add_inv; // select line to a4stg_rnd_frac |
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| 194 | wire [9:0] a4stg_shl_cnt_in; // postnorm shift left count- add 3 stg |
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| 195 | wire a4stg_rnd_sng; // round to single precision- add 4 stg |
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| 196 | wire a4stg_rnd_dbl; // round to double precision- add 4 stg |
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| 197 | wire add_frac_out_rndadd; // select line to add_frac_out |
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| 198 | wire add_frac_out_rnd_frac; // select line to add_frac_out |
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| 199 | wire add_frac_out_shl; // select line to add_frac_out |
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| 200 | wire a4stg_to_0; // result to max finite on overflow |
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| 201 | wire add_exp_out_expinc; // select line to add_exp_out |
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| 202 | wire add_exp_out_exp; // select line to add_exp_out |
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| 203 | wire add_exp_out_exp1; // select line to add_exp_out |
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| 204 | wire add_exp_out_expadd; // select line to add_exp_out |
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| 205 | wire a4stg_to_0_inv; // result to infinity on overflow |
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| 206 | wire add_pipe_active; // add pipe is executing a valid instr |
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| 207 | |
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| 208 | |
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| 209 | /////////////////////////////////////////////////////////////////////////////// |
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| 210 | // |
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| 211 | // Outputs of fpu_add_exp_dp. |
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| 212 | // |
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| 213 | /////////////////////////////////////////////////////////////////////////////// |
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| 214 | |
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| 215 | wire a1stg_expadd3_11; // exponent adder 3 output- add 1 stage |
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| 216 | wire [11:0] a1stg_expadd1_11_0; // exponent adder 1 output- add 1 stage |
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| 217 | wire [10:0] a1stg_expadd4_inv; // exponent adder 4 output- add 1 stage |
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| 218 | wire [5:0] a1stg_expadd2_5_0; // exponent adder 2 output- add 1 stage |
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| 219 | wire [11:0] a2stg_exp; // exponent- add 2 stage |
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| 220 | wire [12:0] a2stg_expadd; // exponent adder- add 2 stage |
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| 221 | wire [10:0] a3stg_exp_10_0; // exponent adder- add 3 stage |
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| 222 | wire [11:0] a4stg_exp_11_0; // exponent adder- add 4 stage |
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| 223 | wire [10:0] add_exp_out; // add exponent output |
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| 224 | |
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| 225 | |
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| 226 | /////////////////////////////////////////////////////////////////////////////// |
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| 227 | // |
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| 228 | // Outputs of fpu_add_frac_dp. |
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| 229 | // |
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| 230 | /////////////////////////////////////////////////////////////////////////////// |
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| 231 | |
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| 232 | wire a1stg_in2_neq_in1_frac; // operand 2 fraction != oprnd 1 frac |
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| 233 | wire a1stg_in2_gt_in1_frac; // operand 2 fraction > oprnd 1 frac |
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| 234 | wire a1stg_in2_eq_in1_exp; // operand 2 exponent == oprnd 1 exp |
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| 235 | wire a2stg_frac2_63; // fraction 2 bit[63]- add 2 stage |
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| 236 | wire a2stg_frac2hi_neq_0; // fraction 2[62:32]in add 2 stage != 0 |
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| 237 | wire a2stg_frac2lo_neq_0; // fraction 2[31:11] in add 2 stage != 0 |
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| 238 | wire a3stg_fsdtoix_nx; // inexact result for flt -> ints |
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| 239 | wire a3stg_fsdtoi_nx; // inexact result for flt -> 32b ints |
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| 240 | wire a3stg_denorm; // denorm output- add 3 stage |
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| 241 | wire a3stg_denorm_inv; // result is not a denorm- add 3 stage |
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| 242 | wire [5:0] a3stg_lead0; // leading 0's count- add 3 stage |
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| 243 | wire a4stg_round; // round the result- add 4 stage |
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| 244 | wire [5:0] a4stg_shl_cnt; // subtract in main adder- add 4 stage |
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| 245 | wire a4stg_denorm_inv; // 0 the exponent |
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| 246 | wire a3stg_inc_exp_inv; // increment the exponent- add 3 stg |
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| 247 | wire a3stg_same_exp_inv; // keep the exponent- add 3 stg |
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| 248 | wire a3stg_dec_exp_inv; // decrement the exponent- add 3 stg |
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| 249 | wire a4stg_rnd_frac_40; // rounded fraction[40]- add 4 stage |
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| 250 | wire a4stg_rnd_frac_39; // rounded fraction[39]- add 4 stage |
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| 251 | wire a4stg_rnd_frac_11; // rounded fraction[11]- add 4 stage |
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| 252 | wire a4stg_rnd_frac_10; // rounded fraction[10]- add 4 stage |
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| 253 | wire a4stg_rndadd_cout; // fraction rounding adder carry out |
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| 254 | wire a4stg_frac_9_0_nx; // inexact double precision result |
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| 255 | wire a4stg_frac_dbl_nx; // inexact double precision result |
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| 256 | wire a4stg_frac_38_0_nx; // inexact single precision result |
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| 257 | wire a4stg_frac_sng_nx; // inexact single precision result |
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| 258 | wire a4stg_frac_neq_0; // fraction != 0- add 4 stage |
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| 259 | wire a4stg_shl_data_neq_0; // left shift result != 0- add 4 stage |
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| 260 | wire add_of_out_cout; // fraction rounding adder carry out |
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| 261 | wire [63:0] add_frac_out; // add fraction output |
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| 262 | |
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| 263 | |
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| 264 | /////////////////////////////////////////////////////////////////////////////// |
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| 265 | // |
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| 266 | // Instantiations. |
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| 267 | // |
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| 268 | /////////////////////////////////////////////////////////////////////////////// |
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| 269 | |
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| 270 | fpu_add_ctl fpu_add_ctl ( |
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| 271 | .inq_in1_51 (inq_in1[51]), |
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| 272 | .inq_in1_54 (inq_in1[54]), |
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| 273 | .inq_in1_63 (inq_in1[63]), |
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| 274 | .inq_in1_50_0_neq_0 (inq_in1_50_0_neq_0), |
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| 275 | .inq_in1_53_32_neq_0 (inq_in1_53_32_neq_0), |
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| 276 | .inq_in1_exp_eq_0 (inq_in1_exp_eq_0), |
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| 277 | .inq_in1_exp_neq_ffs (inq_in1_exp_neq_ffs), |
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| 278 | .inq_in2_51 (inq_in2[51]), |
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| 279 | .inq_in2_54 (inq_in2[54]), |
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| 280 | .inq_in2_63 (inq_in2[63]), |
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| 281 | .inq_in2_50_0_neq_0 (inq_in2_50_0_neq_0), |
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| 282 | .inq_in2_53_32_neq_0 (inq_in2_53_32_neq_0), |
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| 283 | .inq_in2_exp_eq_0 (inq_in2_exp_eq_0), |
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| 284 | .inq_in2_exp_neq_ffs (inq_in2_exp_neq_ffs), |
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| 285 | .inq_op (inq_op[7:0]), |
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| 286 | .inq_rnd_mode (inq_rnd_mode[1:0]), |
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| 287 | .inq_id (inq_id[4:0]), |
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| 288 | .inq_fcc (inq_fcc[1:0]), |
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| 289 | .inq_add (inq_add), |
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| 290 | .add_dest_rdy (add_dest_rdy), |
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| 291 | .a1stg_in2_neq_in1_frac (a1stg_in2_neq_in1_frac), |
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| 292 | .a1stg_in2_gt_in1_frac (a1stg_in2_gt_in1_frac), |
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| 293 | .a1stg_in2_eq_in1_exp (a1stg_in2_eq_in1_exp), |
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| 294 | .a1stg_expadd1 (a1stg_expadd1_11_0[11:0]), |
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| 295 | .a2stg_expadd (a2stg_expadd[11:0]), |
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| 296 | .a2stg_frac2hi_neq_0 (a2stg_frac2hi_neq_0), |
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| 297 | .a2stg_frac2lo_neq_0 (a2stg_frac2lo_neq_0), |
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| 298 | .a2stg_exp (a2stg_exp[11:0]), |
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| 299 | .a3stg_fsdtoix_nx (a3stg_fsdtoix_nx), |
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| 300 | .a3stg_fsdtoi_nx (a3stg_fsdtoi_nx), |
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| 301 | .a2stg_frac2_63 (a2stg_frac2_63), |
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| 302 | .a4stg_exp (a4stg_exp_11_0[11:0]), |
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| 303 | .add_of_out_cout (add_of_out_cout), |
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| 304 | .a4stg_frac_neq_0 (a4stg_frac_neq_0), |
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| 305 | .a4stg_shl_data_neq_0 (a4stg_shl_data_neq_0), |
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| 306 | .a4stg_frac_dbl_nx (a4stg_frac_dbl_nx), |
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| 307 | .a4stg_frac_sng_nx (a4stg_frac_sng_nx), |
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| 308 | .a1stg_expadd2 (a1stg_expadd2_5_0[5:0]), |
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| 309 | .a1stg_expadd4_inv (a1stg_expadd4_inv[10:0]), |
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| 310 | .a3stg_denorm (a3stg_denorm), |
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| 311 | .a3stg_denorm_inv (a3stg_denorm_inv), |
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| 312 | .a4stg_denorm_inv (a4stg_denorm_inv), |
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| 313 | .a3stg_exp (a3stg_exp_10_0[10:0]), |
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| 314 | .a4stg_round (a4stg_round), |
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| 315 | .a3stg_lead0 (a3stg_lead0[5:0]), |
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| 316 | .a4stg_rnd_frac_40 (a4stg_rnd_frac_40), |
|---|
| 317 | .a4stg_rnd_frac_39 (a4stg_rnd_frac_39), |
|---|
| 318 | .a4stg_rnd_frac_11 (a4stg_rnd_frac_11), |
|---|
| 319 | .a4stg_rnd_frac_10 (a4stg_rnd_frac_10), |
|---|
| 320 | .a4stg_frac_38_0_nx (a4stg_frac_38_0_nx), |
|---|
| 321 | .a4stg_frac_9_0_nx (a4stg_frac_9_0_nx), |
|---|
| 322 | .arst_l (arst_l), |
|---|
| 323 | .grst_l (grst_l), |
|---|
| 324 | .rclk (rclk), |
|---|
| 325 | |
|---|
| 326 | .add_pipe_active (add_pipe_active), |
|---|
| 327 | .a1stg_denorm_sng_in1 (a1stg_denorm_sng_in1), |
|---|
| 328 | .a1stg_denorm_dbl_in1 (a1stg_denorm_dbl_in1), |
|---|
| 329 | .a1stg_denorm_sng_in2 (a1stg_denorm_sng_in2), |
|---|
| 330 | .a1stg_denorm_dbl_in2 (a1stg_denorm_dbl_in2), |
|---|
| 331 | .a1stg_norm_sng_in1 (a1stg_norm_sng_in1), |
|---|
| 332 | .a1stg_norm_dbl_in1 (a1stg_norm_dbl_in1), |
|---|
| 333 | .a1stg_norm_sng_in2 (a1stg_norm_sng_in2), |
|---|
| 334 | .a1stg_norm_dbl_in2 (a1stg_norm_dbl_in2), |
|---|
| 335 | .a1stg_step (a1stg_step), |
|---|
| 336 | .a1stg_stepa (a1stg_stepa), |
|---|
| 337 | .a1stg_sngop (a1stg_sngop), |
|---|
| 338 | .a1stg_intlngop (a1stg_intlngop), |
|---|
| 339 | .a1stg_fsdtoix (a1stg_fsdtoix), |
|---|
| 340 | .a1stg_fstod (a1stg_fstod), |
|---|
| 341 | .a1stg_fstoi (a1stg_fstoi), |
|---|
| 342 | .a1stg_fstox (a1stg_fstox), |
|---|
| 343 | .a1stg_fdtoi (a1stg_fdtoi), |
|---|
| 344 | .a1stg_fdtox (a1stg_fdtox), |
|---|
| 345 | .a1stg_faddsubs (a1stg_faddsubs), |
|---|
| 346 | .a1stg_faddsubd (a1stg_faddsubd), |
|---|
| 347 | .a1stg_fdtos (a1stg_fdtos), |
|---|
| 348 | .a2stg_faddsubop (a2stg_faddsubop), |
|---|
| 349 | .a2stg_fsdtoix_fdtos (a2stg_fsdtoix_fdtos), |
|---|
| 350 | .a2stg_fitos (a2stg_fitos), |
|---|
| 351 | .a2stg_fitod (a2stg_fitod), |
|---|
| 352 | .a2stg_fxtos (a2stg_fxtos), |
|---|
| 353 | .a2stg_fxtod (a2stg_fxtod), |
|---|
| 354 | .a3stg_faddsubop (a3stg_faddsubop), |
|---|
| 355 | .a3stg_faddsubopa (a3stg_faddsubopa[1:0]), |
|---|
| 356 | .a4stg_dblop (a4stg_dblop), |
|---|
| 357 | .a6stg_fadd_in (a6stg_fadd_in), |
|---|
| 358 | .add_id_out_in (add_id_out_in[9:0]), |
|---|
| 359 | .add_fcc_out (add_fcc_out[1:0]), |
|---|
| 360 | .a6stg_dbl_dst (a6stg_dbl_dst), |
|---|
| 361 | .a6stg_sng_dst (a6stg_sng_dst), |
|---|
| 362 | .a6stg_long_dst (a6stg_long_dst), |
|---|
| 363 | .a6stg_int_dst (a6stg_int_dst), |
|---|
| 364 | .a6stg_fcmpop (a6stg_fcmpop), |
|---|
| 365 | .a6stg_step (a6stg_step), |
|---|
| 366 | .a3stg_sub_in (a3stg_sub_in), |
|---|
| 367 | .add_sign_out (add_sign_out), |
|---|
| 368 | .add_cc_out (add_cc_out[1:0]), |
|---|
| 369 | .a4stg_in_of (a4stg_in_of), |
|---|
| 370 | .add_exc_out (add_exc_out[4:0]), |
|---|
| 371 | .a2stg_frac1_in_frac1 (a2stg_frac1_in_frac1), |
|---|
| 372 | .a2stg_frac1_in_frac2 (a2stg_frac1_in_frac2), |
|---|
| 373 | .a1stg_2nan_in_inv (a1stg_2nan_in_inv), |
|---|
| 374 | .a1stg_faddsubop_inv (a1stg_faddsubop_inv), |
|---|
| 375 | .a2stg_frac1_in_qnan (a2stg_frac1_in_qnan), |
|---|
| 376 | .a2stg_frac1_in_nv (a2stg_frac1_in_nv), |
|---|
| 377 | .a2stg_frac1_in_nv_dbl (a2stg_frac1_in_nv_dbl), |
|---|
| 378 | .a2stg_frac2_in_frac1 (a2stg_frac2_in_frac1), |
|---|
| 379 | .a2stg_frac2_in_qnan (a2stg_frac2_in_qnan), |
|---|
| 380 | .a2stg_shr_cnt_in (a2stg_shr_cnt_in[5:0]), |
|---|
| 381 | .a2stg_shr_cnt_5_inv_in (a2stg_shr_cnt_5_inv_in), |
|---|
| 382 | .a2stg_shr_frac2_shr_int (a2stg_shr_frac2_shr_int), |
|---|
| 383 | .a2stg_shr_frac2_shr_dbl (a2stg_shr_frac2_shr_dbl), |
|---|
| 384 | .a2stg_shr_frac2_shr_sng (a2stg_shr_frac2_shr_sng), |
|---|
| 385 | .a2stg_shr_frac2_max (a2stg_shr_frac2_max), |
|---|
| 386 | .a2stg_sub_step (a2stg_sub_step), |
|---|
| 387 | .a2stg_fracadd_frac2_inv_in (a2stg_fracadd_frac2_inv_in), |
|---|
| 388 | .a2stg_fracadd_frac2_inv_shr1_in (a2stg_fracadd_frac2_inv_shr1_in), |
|---|
| 389 | .a2stg_fracadd_frac2 (a2stg_fracadd_frac2), |
|---|
| 390 | .a2stg_fracadd_cin_in (a2stg_fracadd_cin_in), |
|---|
| 391 | .a3stg_exp_7ff (a3stg_exp_7ff), |
|---|
| 392 | .a3stg_exp_ff (a3stg_exp_ff), |
|---|
| 393 | .a3stg_exp_add (a3stg_exp_add), |
|---|
| 394 | .a2stg_expdec_neq_0 (a2stg_expdec_neq_0), |
|---|
| 395 | .a3stg_exp10_0_eq0 (a3stg_exp10_0_eq0), |
|---|
| 396 | .a3stg_exp10_1_eq0 (a3stg_exp10_1_eq0), |
|---|
| 397 | .a3stg_fdtos_inv (a3stg_fdtos_inv), |
|---|
| 398 | .a4stg_fixtos_fxtod_inv (a4stg_fixtos_fxtod_inv), |
|---|
| 399 | .a4stg_rnd_frac_add_inv (a4stg_rnd_frac_add_inv), |
|---|
| 400 | .a4stg_shl_cnt_in (a4stg_shl_cnt_in[9:0]), |
|---|
| 401 | .a4stg_rnd_sng (a4stg_rnd_sng), |
|---|
| 402 | .a4stg_rnd_dbl (a4stg_rnd_dbl), |
|---|
| 403 | .add_frac_out_rndadd (add_frac_out_rndadd), |
|---|
| 404 | .add_frac_out_rnd_frac (add_frac_out_rnd_frac), |
|---|
| 405 | .add_frac_out_shl (add_frac_out_shl), |
|---|
| 406 | .a4stg_to_0 (a4stg_to_0), |
|---|
| 407 | .add_exp_out_expinc (add_exp_out_expinc), |
|---|
| 408 | .add_exp_out_exp (add_exp_out_exp), |
|---|
| 409 | .add_exp_out_exp1 (add_exp_out_exp1), |
|---|
| 410 | .add_exp_out_expadd (add_exp_out_expadd), |
|---|
| 411 | .a4stg_to_0_inv (a4stg_to_0_inv), |
|---|
| 412 | |
|---|
| 413 | .se (se_add_exp), |
|---|
| 414 | .si (si), |
|---|
| 415 | .so (scan_out_fpu_add_ctl) |
|---|
| 416 | ); |
|---|
| 417 | |
|---|
| 418 | |
|---|
| 419 | fpu_add_exp_dp fpu_add_exp_dp ( |
|---|
| 420 | .inq_in1 (inq_in1[62:52]), |
|---|
| 421 | .inq_in2 (inq_in2[62:52]), |
|---|
| 422 | .inq_op (inq_op[1:0]), |
|---|
| 423 | .inq_op_7 (inq_op[7]), |
|---|
| 424 | .a1stg_step (a1stg_stepa), |
|---|
| 425 | .a1stg_faddsubd (a1stg_faddsubd), |
|---|
| 426 | .a1stg_faddsubs (a1stg_faddsubs), |
|---|
| 427 | .a1stg_fsdtoix (a1stg_fsdtoix), |
|---|
| 428 | .a6stg_step (a6stg_step), |
|---|
| 429 | .a1stg_fstod (a1stg_fstod), |
|---|
| 430 | .a1stg_fdtos (a1stg_fdtos), |
|---|
| 431 | .a1stg_fstoi (a1stg_fstoi), |
|---|
| 432 | .a1stg_fstox (a1stg_fstox), |
|---|
| 433 | .a1stg_fdtoi (a1stg_fdtoi), |
|---|
| 434 | .a1stg_fdtox (a1stg_fdtox), |
|---|
| 435 | .a2stg_fsdtoix_fdtos (a2stg_fsdtoix_fdtos), |
|---|
| 436 | .a2stg_faddsubop (a2stg_faddsubop), |
|---|
| 437 | .a2stg_fitos (a2stg_fitos), |
|---|
| 438 | .a2stg_fitod (a2stg_fitod), |
|---|
| 439 | .a2stg_fxtos (a2stg_fxtos), |
|---|
| 440 | .a2stg_fxtod (a2stg_fxtod), |
|---|
| 441 | .a3stg_exp_7ff (a3stg_exp_7ff), |
|---|
| 442 | .a3stg_exp_ff (a3stg_exp_ff), |
|---|
| 443 | .a3stg_exp_add (a3stg_exp_add), |
|---|
| 444 | .a3stg_inc_exp_inv (a3stg_inc_exp_inv), |
|---|
| 445 | .a3stg_same_exp_inv (a3stg_same_exp_inv), |
|---|
| 446 | .a3stg_dec_exp_inv (a3stg_dec_exp_inv), |
|---|
| 447 | .a3stg_faddsubop (a3stg_faddsubop), |
|---|
| 448 | .a3stg_fdtos_inv (a3stg_fdtos_inv), |
|---|
| 449 | .a4stg_fixtos_fxtod_inv (a4stg_fixtos_fxtod_inv), |
|---|
| 450 | .a4stg_shl_cnt (a4stg_shl_cnt[5:0]), |
|---|
| 451 | .a4stg_denorm_inv (a4stg_denorm_inv), |
|---|
| 452 | .a4stg_rndadd_cout (a4stg_rndadd_cout), |
|---|
| 453 | .add_exp_out_expinc (add_exp_out_expinc), |
|---|
| 454 | .add_exp_out_exp (add_exp_out_exp), |
|---|
| 455 | .add_exp_out_exp1 (add_exp_out_exp1), |
|---|
| 456 | .a4stg_in_of (a4stg_in_of), |
|---|
| 457 | .add_exp_out_expadd (add_exp_out_expadd), |
|---|
| 458 | .a4stg_dblop (a4stg_dblop), |
|---|
| 459 | .a4stg_to_0_inv (a4stg_to_0_inv), |
|---|
| 460 | .fadd_clken_l (fadd_clken_l), |
|---|
| 461 | .rclk (rclk), |
|---|
| 462 | |
|---|
| 463 | .a1stg_expadd3_11 (a1stg_expadd3_11), |
|---|
| 464 | .a1stg_expadd1_11_0 (a1stg_expadd1_11_0[11:0]), |
|---|
| 465 | .a1stg_expadd4_inv (a1stg_expadd4_inv[10:0]), |
|---|
| 466 | .a1stg_expadd2_5_0 (a1stg_expadd2_5_0[5:0]), |
|---|
| 467 | .a2stg_exp (a2stg_exp[11:0]), |
|---|
| 468 | .a2stg_expadd (a2stg_expadd[12:0]), |
|---|
| 469 | .a3stg_exp_10_0 (a3stg_exp_10_0[10:0]), |
|---|
| 470 | .a4stg_exp_11_0 (a4stg_exp_11_0[11:0]), |
|---|
| 471 | .add_exp_out (add_exp_out[10:0]), |
|---|
| 472 | |
|---|
| 473 | .se (se_add_exp), |
|---|
| 474 | .si (scan_out_fpu_add_ctl), |
|---|
| 475 | .so (scan_out_fpu_add_exp_dp) |
|---|
| 476 | ); |
|---|
| 477 | |
|---|
| 478 | |
|---|
| 479 | fpu_add_frac_dp fpu_add_frac_dp ( |
|---|
| 480 | .inq_in1 (inq_in1[62:0]), |
|---|
| 481 | .inq_in2 (inq_in2[63:0]), |
|---|
| 482 | .a1stg_step (a1stg_stepa), |
|---|
| 483 | .a1stg_sngop (a1stg_sngop), |
|---|
| 484 | .a1stg_expadd3_11 (a1stg_expadd3_11), |
|---|
| 485 | .a1stg_norm_dbl_in1 (a1stg_norm_dbl_in1), |
|---|
| 486 | .a1stg_denorm_dbl_in1 (a1stg_denorm_dbl_in1), |
|---|
| 487 | .a1stg_norm_sng_in1 (a1stg_norm_sng_in1), |
|---|
| 488 | .a1stg_denorm_sng_in1 (a1stg_denorm_sng_in1), |
|---|
| 489 | .a1stg_norm_dbl_in2 (a1stg_norm_dbl_in2), |
|---|
| 490 | .a1stg_denorm_dbl_in2 (a1stg_denorm_dbl_in2), |
|---|
| 491 | .a1stg_norm_sng_in2 (a1stg_norm_sng_in2), |
|---|
| 492 | .a1stg_denorm_sng_in2 (a1stg_denorm_sng_in2), |
|---|
| 493 | .a1stg_intlngop (a1stg_intlngop), |
|---|
| 494 | .a2stg_frac1_in_frac1 (a2stg_frac1_in_frac1), |
|---|
| 495 | .a2stg_frac1_in_frac2 (a2stg_frac1_in_frac2), |
|---|
| 496 | .a1stg_2nan_in_inv (a1stg_2nan_in_inv), |
|---|
| 497 | .a1stg_faddsubop_inv (a1stg_faddsubop_inv), |
|---|
| 498 | .a2stg_frac1_in_qnan (a2stg_frac1_in_qnan), |
|---|
| 499 | .a2stg_frac1_in_nv (a2stg_frac1_in_nv), |
|---|
| 500 | .a2stg_frac1_in_nv_dbl (a2stg_frac1_in_nv_dbl), |
|---|
| 501 | .a6stg_step (a6stg_step), |
|---|
| 502 | .a2stg_frac2_in_frac1 (a2stg_frac2_in_frac1), |
|---|
| 503 | .a2stg_frac2_in_qnan (a2stg_frac2_in_qnan), |
|---|
| 504 | .a2stg_shr_cnt_in (a2stg_shr_cnt_in[5:0]), |
|---|
| 505 | .a2stg_shr_cnt_5_inv_in (a2stg_shr_cnt_5_inv_in), |
|---|
| 506 | .a2stg_shr_frac2_shr_int (a2stg_shr_frac2_shr_int), |
|---|
| 507 | .a2stg_shr_frac2_shr_dbl (a2stg_shr_frac2_shr_dbl), |
|---|
| 508 | .a2stg_shr_frac2_shr_sng (a2stg_shr_frac2_shr_sng), |
|---|
| 509 | .a2stg_shr_frac2_max (a2stg_shr_frac2_max), |
|---|
| 510 | .a2stg_expadd_11 (a2stg_expadd[12]), |
|---|
| 511 | .a2stg_sub_step (a2stg_sub_step), |
|---|
| 512 | .a2stg_fracadd_frac2_inv_in (a2stg_fracadd_frac2_inv_in), |
|---|
| 513 | .a2stg_fracadd_frac2_inv_shr1_in (a2stg_fracadd_frac2_inv_shr1_in), |
|---|
| 514 | .a2stg_fracadd_frac2 (a2stg_fracadd_frac2), |
|---|
| 515 | .a2stg_fracadd_cin_in (a2stg_fracadd_cin_in), |
|---|
| 516 | .a2stg_exp (a2stg_exp[5:0]), |
|---|
| 517 | .a2stg_expdec_neq_0 (a2stg_expdec_neq_0), |
|---|
| 518 | .a3stg_faddsubopa (a3stg_faddsubopa[1:0]), |
|---|
| 519 | .a3stg_sub_in (a3stg_sub_in), |
|---|
| 520 | .a3stg_exp10_0_eq0 (a3stg_exp10_0_eq0), |
|---|
| 521 | .a3stg_exp10_1_eq0 (a3stg_exp10_1_eq0), |
|---|
| 522 | .a3stg_exp_0 (a3stg_exp_10_0[0]), |
|---|
| 523 | .a4stg_rnd_frac_add_inv (a4stg_rnd_frac_add_inv), |
|---|
| 524 | .a3stg_fdtos_inv (a3stg_fdtos_inv), |
|---|
| 525 | .a4stg_fixtos_fxtod_inv (a4stg_fixtos_fxtod_inv), |
|---|
| 526 | .a4stg_rnd_sng (a4stg_rnd_sng), |
|---|
| 527 | .a4stg_rnd_dbl (a4stg_rnd_dbl), |
|---|
| 528 | .a4stg_shl_cnt_in (a4stg_shl_cnt_in[9:0]), |
|---|
| 529 | .add_frac_out_rndadd (add_frac_out_rndadd), |
|---|
| 530 | .add_frac_out_rnd_frac (add_frac_out_rnd_frac), |
|---|
| 531 | .a4stg_in_of (a4stg_in_of), |
|---|
| 532 | .add_frac_out_shl (add_frac_out_shl), |
|---|
| 533 | .a4stg_to_0 (a4stg_to_0), |
|---|
| 534 | .fadd_clken_l (fadd_clken_l), |
|---|
| 535 | .rclk (rclk), |
|---|
| 536 | |
|---|
| 537 | .a1stg_in2_neq_in1_frac (a1stg_in2_neq_in1_frac), |
|---|
| 538 | .a1stg_in2_gt_in1_frac (a1stg_in2_gt_in1_frac), |
|---|
| 539 | .a1stg_in2_eq_in1_exp (a1stg_in2_eq_in1_exp), |
|---|
| 540 | .a2stg_frac2_63 (a2stg_frac2_63), |
|---|
| 541 | .a2stg_frac2hi_neq_0 (a2stg_frac2hi_neq_0), |
|---|
| 542 | .a2stg_frac2lo_neq_0 (a2stg_frac2lo_neq_0), |
|---|
| 543 | .a3stg_fsdtoix_nx (a3stg_fsdtoix_nx), |
|---|
| 544 | .a3stg_fsdtoi_nx (a3stg_fsdtoi_nx), |
|---|
| 545 | .a3stg_denorm (a3stg_denorm), |
|---|
| 546 | .a3stg_denorm_inv (a3stg_denorm_inv), |
|---|
| 547 | .a3stg_lead0 (a3stg_lead0[5:0]), |
|---|
| 548 | .a4stg_round (a4stg_round), |
|---|
| 549 | .a4stg_shl_cnt (a4stg_shl_cnt[5:0]), |
|---|
| 550 | .a4stg_denorm_inv (a4stg_denorm_inv), |
|---|
| 551 | .a3stg_inc_exp_inv (a3stg_inc_exp_inv), |
|---|
| 552 | .a3stg_same_exp_inv (a3stg_same_exp_inv), |
|---|
| 553 | .a3stg_dec_exp_inv (a3stg_dec_exp_inv), |
|---|
| 554 | .a4stg_rnd_frac_40 (a4stg_rnd_frac_40), |
|---|
| 555 | .a4stg_rnd_frac_39 (a4stg_rnd_frac_39), |
|---|
| 556 | .a4stg_rnd_frac_11 (a4stg_rnd_frac_11), |
|---|
| 557 | .a4stg_rnd_frac_10 (a4stg_rnd_frac_10), |
|---|
| 558 | .a4stg_rndadd_cout (a4stg_rndadd_cout), |
|---|
| 559 | .a4stg_frac_9_0_nx (a4stg_frac_9_0_nx), |
|---|
| 560 | .a4stg_frac_dbl_nx (a4stg_frac_dbl_nx), |
|---|
| 561 | .a4stg_frac_38_0_nx (a4stg_frac_38_0_nx), |
|---|
| 562 | .a4stg_frac_sng_nx (a4stg_frac_sng_nx), |
|---|
| 563 | .a4stg_frac_neq_0 (a4stg_frac_neq_0), |
|---|
| 564 | .a4stg_shl_data_neq_0 (a4stg_shl_data_neq_0), |
|---|
| 565 | .add_of_out_cout (add_of_out_cout), |
|---|
| 566 | .add_frac_out (add_frac_out[63:0]), |
|---|
| 567 | |
|---|
| 568 | .se (se_add_frac), |
|---|
| 569 | .si (scan_out_fpu_add_exp_dp), |
|---|
| 570 | .so (so) |
|---|
| 571 | ); |
|---|
| 572 | |
|---|
| 573 | |
|---|
| 574 | endmodule |
|---|
| 575 | |
|---|
| 576 | |
|---|
