| [6] | 1 | // ========== Copyright Header Begin ========================================== |
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| 2 | // |
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| 3 | // OpenSPARC T1 Processor File: fpu_cnt_lead0_64b.v |
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| 4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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| 5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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| 6 | // |
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| 7 | // The above named program is free software; you can redistribute it and/or |
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| 8 | // modify it under the terms of the GNU General Public |
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| 9 | // License version 2 as published by the Free Software Foundation. |
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| 10 | // |
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| 11 | // The above named program is distributed in the hope that it will be |
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| 12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | // General Public License for more details. |
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| 15 | // |
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| 16 | // You should have received a copy of the GNU General Public |
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| 17 | // License along with this work; if not, write to the Free Software |
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| 18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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| 19 | // |
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| 20 | // ========== Copyright Header End ============================================ |
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| 21 | /////////////////////////////////////////////////////////////////////////////// |
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| 22 | // |
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| 23 | // 64 bit lead 0 counter. |
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| 24 | // |
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| 25 | /////////////////////////////////////////////////////////////////////////////// |
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| 26 | |
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| 27 | module fpu_cnt_lead0_64b ( |
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| 28 | din, |
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| 29 | |
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| 30 | lead0 |
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| 31 | ); |
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| 32 | |
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| 33 | |
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| 34 | input [63:0] din; // data in- count its leading 0's |
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| 35 | |
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| 36 | output [5:0] lead0; // number of leading 0's in data in |
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| 37 | |
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| 38 | |
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| 39 | wire din_63_60_eq_0; |
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| 40 | wire din_63_62_eq_0; |
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| 41 | wire lead0_63_60_0; |
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| 42 | wire din_59_56_eq_0; |
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| 43 | wire din_59_58_eq_0; |
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| 44 | wire lead0_59_56_0; |
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| 45 | wire din_55_52_eq_0; |
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| 46 | wire din_55_54_eq_0; |
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| 47 | wire lead0_55_52_0; |
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| 48 | wire din_51_48_eq_0; |
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| 49 | wire din_51_50_eq_0; |
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| 50 | wire lead0_51_48_0; |
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| 51 | wire din_47_44_eq_0; |
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| 52 | wire din_47_46_eq_0; |
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| 53 | wire lead0_47_44_0; |
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| 54 | wire din_43_40_eq_0; |
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| 55 | wire din_43_42_eq_0; |
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| 56 | wire lead0_43_40_0; |
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| 57 | wire din_39_36_eq_0; |
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| 58 | wire din_39_38_eq_0; |
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| 59 | wire lead0_39_36_0; |
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| 60 | wire din_35_32_eq_0; |
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| 61 | wire din_35_34_eq_0; |
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| 62 | wire lead0_35_32_0; |
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| 63 | wire din_31_28_eq_0; |
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| 64 | wire din_31_30_eq_0; |
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| 65 | wire lead0_31_28_0; |
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| 66 | wire din_27_24_eq_0; |
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| 67 | wire din_27_26_eq_0; |
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| 68 | wire lead0_27_24_0; |
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| 69 | wire din_23_20_eq_0; |
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| 70 | wire din_23_22_eq_0; |
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| 71 | wire lead0_23_20_0; |
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| 72 | wire din_19_16_eq_0; |
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| 73 | wire din_19_18_eq_0; |
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| 74 | wire lead0_19_16_0; |
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| 75 | wire din_15_12_eq_0; |
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| 76 | wire din_15_14_eq_0; |
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| 77 | wire lead0_15_12_0; |
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| 78 | wire din_11_8_eq_0; |
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| 79 | wire din_11_10_eq_0; |
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| 80 | wire lead0_11_8_0; |
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| 81 | wire din_7_4_eq_0; |
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| 82 | wire din_7_6_eq_0; |
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| 83 | wire lead0_7_4_0; |
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| 84 | wire din_3_0_eq_0; |
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| 85 | wire din_3_2_eq_0; |
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| 86 | wire lead0_3_0_0; |
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| 87 | wire din_63_56_eq_0; |
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| 88 | wire lead0_63_56_1; |
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| 89 | wire lead0_63_56_0; |
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| 90 | wire din_55_48_eq_0; |
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| 91 | wire lead0_55_48_1; |
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| 92 | wire lead0_55_48_0; |
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| 93 | wire din_47_40_eq_0; |
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| 94 | wire lead0_47_40_1; |
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| 95 | wire lead0_47_40_0; |
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| 96 | wire din_39_32_eq_0; |
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| 97 | wire lead0_39_32_1; |
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| 98 | wire lead0_39_32_0; |
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| 99 | wire din_31_24_eq_0; |
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| 100 | wire lead0_31_24_1; |
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| 101 | wire lead0_31_24_0; |
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| 102 | wire din_23_16_eq_0; |
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| 103 | wire lead0_23_16_1; |
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| 104 | wire lead0_23_16_0; |
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| 105 | wire din_15_8_eq_0; |
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| 106 | wire lead0_15_8_1; |
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| 107 | wire lead0_15_8_0; |
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| 108 | wire din_7_0_eq_0; |
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| 109 | wire lead0_7_0_1; |
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| 110 | wire lead0_7_0_0; |
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| 111 | wire din_63_48_eq_0; |
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| 112 | wire lead0_63_48_2; |
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| 113 | wire lead0_63_48_1; |
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| 114 | wire lead0_63_48_0; |
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| 115 | wire din_47_32_eq_0; |
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| 116 | wire lead0_47_32_2; |
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| 117 | wire lead0_47_32_1; |
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| 118 | wire lead0_47_32_0; |
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| 119 | wire din_31_16_eq_0; |
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| 120 | wire lead0_31_16_2; |
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| 121 | wire lead0_31_16_1; |
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| 122 | wire lead0_31_16_0; |
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| 123 | wire din_15_0_eq_0; |
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| 124 | wire lead0_15_0_2; |
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| 125 | wire lead0_15_0_1; |
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| 126 | wire lead0_15_0_0; |
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| 127 | wire din_63_32_eq_0; |
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| 128 | wire lead0_63_32_3; |
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| 129 | wire lead0_63_32_2; |
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| 130 | wire lead0_63_32_1; |
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| 131 | wire din_31_0_eq_0; |
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| 132 | wire lead0_31_0_3; |
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| 133 | wire lead0_31_0_2; |
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| 134 | wire lead0_31_0_1; |
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| 135 | wire lead0_31_0_0; |
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| 136 | wire lead0_6; |
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| 137 | wire lead0_5; |
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| 138 | wire lead0_4; |
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| 139 | wire lead0_3; |
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| 140 | wire lead0_2; |
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| 141 | wire lead0_1; |
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| 142 | wire lead0_0; |
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| 143 | wire [5:0] lead0; |
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| 144 | |
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| 145 | |
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| 146 | /////////////////////////////////////////////////////////////////////////////// |
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| 147 | // |
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| 148 | // Instantiations of lead 0 building blocks. |
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| 149 | // |
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| 150 | /////////////////////////////////////////////////////////////////////////////// |
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| 151 | |
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| 152 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_63_60 ( |
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| 153 | .din (din[63:60]), |
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| 154 | |
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| 155 | .din_3_0_eq_0 (din_63_60_eq_0), |
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| 156 | .din_3_2_eq_0 (din_63_62_eq_0), |
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| 157 | .lead0_4b_0 (lead0_63_60_0) |
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| 158 | ); |
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| 159 | |
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| 160 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_59_56 ( |
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| 161 | .din (din[59:56]), |
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| 162 | |
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| 163 | .din_3_0_eq_0 (din_59_56_eq_0), |
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| 164 | .din_3_2_eq_0 (din_59_58_eq_0), |
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| 165 | .lead0_4b_0 (lead0_59_56_0) |
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| 166 | ); |
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| 167 | |
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| 168 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_55_52 ( |
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| 169 | .din (din[55:52]), |
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| 170 | |
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| 171 | .din_3_0_eq_0 (din_55_52_eq_0), |
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| 172 | .din_3_2_eq_0 (din_55_54_eq_0), |
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| 173 | .lead0_4b_0 (lead0_55_52_0) |
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| 174 | ); |
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| 175 | |
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| 176 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_51_48 ( |
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| 177 | .din (din[51:48]), |
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| 178 | |
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| 179 | .din_3_0_eq_0 (din_51_48_eq_0), |
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| 180 | .din_3_2_eq_0 (din_51_50_eq_0), |
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| 181 | .lead0_4b_0 (lead0_51_48_0) |
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| 182 | ); |
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| 183 | |
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| 184 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_47_44 ( |
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| 185 | .din (din[47:44]), |
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| 186 | |
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| 187 | .din_3_0_eq_0 (din_47_44_eq_0), |
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| 188 | .din_3_2_eq_0 (din_47_46_eq_0), |
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| 189 | .lead0_4b_0 (lead0_47_44_0) |
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| 190 | ); |
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| 191 | |
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| 192 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_43_40 ( |
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| 193 | .din (din[43:40]), |
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| 194 | |
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| 195 | .din_3_0_eq_0 (din_43_40_eq_0), |
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| 196 | .din_3_2_eq_0 (din_43_42_eq_0), |
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| 197 | .lead0_4b_0 (lead0_43_40_0) |
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| 198 | ); |
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| 199 | |
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| 200 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_39_36 ( |
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| 201 | .din (din[39:36]), |
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| 202 | |
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| 203 | .din_3_0_eq_0 (din_39_36_eq_0), |
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| 204 | .din_3_2_eq_0 (din_39_38_eq_0), |
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| 205 | .lead0_4b_0 (lead0_39_36_0) |
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| 206 | ); |
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| 207 | |
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| 208 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_35_32 ( |
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| 209 | .din (din[35:32]), |
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| 210 | |
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| 211 | .din_3_0_eq_0 (din_35_32_eq_0), |
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| 212 | .din_3_2_eq_0 (din_35_34_eq_0), |
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| 213 | .lead0_4b_0 (lead0_35_32_0) |
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| 214 | ); |
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| 215 | |
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| 216 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_31_28 ( |
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| 217 | .din (din[31:28]), |
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| 218 | |
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| 219 | .din_3_0_eq_0 (din_31_28_eq_0), |
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| 220 | .din_3_2_eq_0 (din_31_30_eq_0), |
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| 221 | .lead0_4b_0 (lead0_31_28_0) |
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| 222 | ); |
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| 223 | |
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| 224 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_27_24 ( |
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| 225 | .din (din[27:24]), |
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| 226 | |
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| 227 | .din_3_0_eq_0 (din_27_24_eq_0), |
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| 228 | .din_3_2_eq_0 (din_27_26_eq_0), |
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| 229 | .lead0_4b_0 (lead0_27_24_0) |
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| 230 | ); |
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| 231 | |
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| 232 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_23_20 ( |
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| 233 | .din (din[23:20]), |
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| 234 | |
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| 235 | .din_3_0_eq_0 (din_23_20_eq_0), |
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| 236 | .din_3_2_eq_0 (din_23_22_eq_0), |
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| 237 | .lead0_4b_0 (lead0_23_20_0) |
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| 238 | ); |
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| 239 | |
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| 240 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_19_16 ( |
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| 241 | .din (din[19:16]), |
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| 242 | |
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| 243 | .din_3_0_eq_0 (din_19_16_eq_0), |
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| 244 | .din_3_2_eq_0 (din_19_18_eq_0), |
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| 245 | .lead0_4b_0 (lead0_19_16_0) |
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| 246 | ); |
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| 247 | |
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| 248 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_15_12 ( |
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| 249 | .din (din[15:12]), |
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| 250 | |
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| 251 | .din_3_0_eq_0 (din_15_12_eq_0), |
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| 252 | .din_3_2_eq_0 (din_15_14_eq_0), |
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| 253 | .lead0_4b_0 (lead0_15_12_0) |
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| 254 | ); |
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| 255 | |
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| 256 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_11_8 ( |
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| 257 | .din (din[11:8]), |
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| 258 | |
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| 259 | .din_3_0_eq_0 (din_11_8_eq_0), |
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| 260 | .din_3_2_eq_0 (din_11_10_eq_0), |
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| 261 | .lead0_4b_0 (lead0_11_8_0) |
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| 262 | ); |
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| 263 | |
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| 264 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_7_4 ( |
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| 265 | .din (din[7:4]), |
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| 266 | |
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| 267 | .din_3_0_eq_0 (din_7_4_eq_0), |
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| 268 | .din_3_2_eq_0 (din_7_6_eq_0), |
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| 269 | .lead0_4b_0 (lead0_7_4_0) |
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| 270 | ); |
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| 271 | |
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| 272 | fpu_cnt_lead0_lvl1 i_fpu_cnt_lead0_lvl1_3_0 ( |
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| 273 | .din (din[3:0]), |
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| 274 | |
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| 275 | .din_3_0_eq_0 (din_3_0_eq_0), |
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| 276 | .din_3_2_eq_0 (din_3_2_eq_0), |
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| 277 | .lead0_4b_0 (lead0_3_0_0) |
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| 278 | ); |
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| 279 | |
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| 280 | |
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| 281 | fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_63_56 ( |
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| 282 | .din_7_4_eq_0 (din_63_60_eq_0), |
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| 283 | .din_7_6_eq_0 (din_63_62_eq_0), |
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| 284 | .lead0_4b_0_hi (lead0_63_60_0), |
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| 285 | .din_3_0_eq_0 (din_59_56_eq_0), |
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| 286 | .din_3_2_eq_0 (din_59_58_eq_0), |
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| 287 | .lead0_4b_0_lo (lead0_59_56_0), |
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| 288 | |
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| 289 | .din_7_0_eq_0 (din_63_56_eq_0), |
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| 290 | .lead0_8b_1 (lead0_63_56_1), |
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| 291 | .lead0_8b_0 (lead0_63_56_0) |
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| 292 | ); |
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| 293 | |
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| 294 | fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_55_48 ( |
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| 295 | .din_7_4_eq_0 (din_55_52_eq_0), |
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| 296 | .din_7_6_eq_0 (din_55_54_eq_0), |
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| 297 | .lead0_4b_0_hi (lead0_55_52_0), |
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| 298 | .din_3_0_eq_0 (din_51_48_eq_0), |
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| 299 | .din_3_2_eq_0 (din_51_50_eq_0), |
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| 300 | .lead0_4b_0_lo (lead0_51_48_0), |
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| 301 | |
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| 302 | .din_7_0_eq_0 (din_55_48_eq_0), |
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| 303 | .lead0_8b_1 (lead0_55_48_1), |
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| 304 | .lead0_8b_0 (lead0_55_48_0) |
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| 305 | ); |
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| 306 | |
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| 307 | fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_47_40 ( |
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| 308 | .din_7_4_eq_0 (din_47_44_eq_0), |
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| 309 | .din_7_6_eq_0 (din_47_46_eq_0), |
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| 310 | .lead0_4b_0_hi (lead0_47_44_0), |
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| 311 | .din_3_0_eq_0 (din_43_40_eq_0), |
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| 312 | .din_3_2_eq_0 (din_43_42_eq_0), |
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| 313 | .lead0_4b_0_lo (lead0_43_40_0), |
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| 314 | |
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| 315 | .din_7_0_eq_0 (din_47_40_eq_0), |
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| 316 | .lead0_8b_1 (lead0_47_40_1), |
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| 317 | .lead0_8b_0 (lead0_47_40_0) |
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| 318 | ); |
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| 319 | |
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| 320 | fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_39_32 ( |
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| 321 | .din_7_4_eq_0 (din_39_36_eq_0), |
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| 322 | .din_7_6_eq_0 (din_39_38_eq_0), |
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| 323 | .lead0_4b_0_hi (lead0_39_36_0), |
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| 324 | .din_3_0_eq_0 (din_35_32_eq_0), |
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| 325 | .din_3_2_eq_0 (din_35_34_eq_0), |
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| 326 | .lead0_4b_0_lo (lead0_35_32_0), |
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| 327 | |
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| 328 | .din_7_0_eq_0 (din_39_32_eq_0), |
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| 329 | .lead0_8b_1 (lead0_39_32_1), |
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| 330 | .lead0_8b_0 (lead0_39_32_0) |
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| 331 | ); |
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| 332 | |
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| 333 | fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_31_24 ( |
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| 334 | .din_7_4_eq_0 (din_31_28_eq_0), |
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| 335 | .din_7_6_eq_0 (din_31_30_eq_0), |
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| 336 | .lead0_4b_0_hi (lead0_31_28_0), |
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| 337 | .din_3_0_eq_0 (din_27_24_eq_0), |
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| 338 | .din_3_2_eq_0 (din_27_26_eq_0), |
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| 339 | .lead0_4b_0_lo (lead0_27_24_0), |
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| 340 | |
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| 341 | .din_7_0_eq_0 (din_31_24_eq_0), |
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| 342 | .lead0_8b_1 (lead0_31_24_1), |
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| 343 | .lead0_8b_0 (lead0_31_24_0) |
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| 344 | ); |
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| 345 | |
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| 346 | fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_23_16 ( |
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| 347 | .din_7_4_eq_0 (din_23_20_eq_0), |
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| 348 | .din_7_6_eq_0 (din_23_22_eq_0), |
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| 349 | .lead0_4b_0_hi (lead0_23_20_0), |
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| 350 | .din_3_0_eq_0 (din_19_16_eq_0), |
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| 351 | .din_3_2_eq_0 (din_19_18_eq_0), |
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| 352 | .lead0_4b_0_lo (lead0_19_16_0), |
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| 353 | |
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| 354 | .din_7_0_eq_0 (din_23_16_eq_0), |
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| 355 | .lead0_8b_1 (lead0_23_16_1), |
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| 356 | .lead0_8b_0 (lead0_23_16_0) |
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| 357 | ); |
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| 358 | |
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| 359 | fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_15_8 ( |
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| 360 | .din_7_4_eq_0 (din_15_12_eq_0), |
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| 361 | .din_7_6_eq_0 (din_15_14_eq_0), |
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| 362 | .lead0_4b_0_hi (lead0_15_12_0), |
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| 363 | .din_3_0_eq_0 (din_11_8_eq_0), |
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| 364 | .din_3_2_eq_0 (din_11_10_eq_0), |
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| 365 | .lead0_4b_0_lo (lead0_11_8_0), |
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| 366 | |
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| 367 | .din_7_0_eq_0 (din_15_8_eq_0), |
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| 368 | .lead0_8b_1 (lead0_15_8_1), |
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| 369 | .lead0_8b_0 (lead0_15_8_0) |
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| 370 | ); |
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| 371 | |
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| 372 | fpu_cnt_lead0_lvl2 i_fpu_cnt_lead0_lvl2_7_0 ( |
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| 373 | .din_7_4_eq_0 (din_7_4_eq_0), |
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| 374 | .din_7_6_eq_0 (din_7_6_eq_0), |
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| 375 | .lead0_4b_0_hi (lead0_7_4_0), |
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| 376 | .din_3_0_eq_0 (din_3_0_eq_0), |
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| 377 | .din_3_2_eq_0 (din_3_2_eq_0), |
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| 378 | .lead0_4b_0_lo (lead0_3_0_0), |
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| 379 | |
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| 380 | .din_7_0_eq_0 (din_7_0_eq_0), |
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| 381 | .lead0_8b_1 (lead0_7_0_1), |
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| 382 | .lead0_8b_0 (lead0_7_0_0) |
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| 383 | ); |
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| 384 | |
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| 385 | |
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| 386 | fpu_cnt_lead0_lvl3 i_fpu_cnt_lead0_lvl3_63_48 ( |
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| 387 | .din_15_8_eq_0 (din_63_56_eq_0), |
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| 388 | .din_15_12_eq_0 (din_63_60_eq_0), |
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| 389 | .lead0_8b_1_hi (lead0_63_56_1), |
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| 390 | .lead0_8b_0_hi (lead0_63_56_0), |
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| 391 | .din_7_0_eq_0 (din_55_48_eq_0), |
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| 392 | .din_7_4_eq_0 (din_55_52_eq_0), |
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| 393 | .lead0_8b_1_lo (lead0_55_48_1), |
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| 394 | .lead0_8b_0_lo (lead0_55_48_0), |
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| 395 | |
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| 396 | .din_15_0_eq_0 (din_63_48_eq_0), |
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| 397 | .lead0_16b_2 (lead0_63_48_2), |
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| 398 | .lead0_16b_1 (lead0_63_48_1), |
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| 399 | .lead0_16b_0 (lead0_63_48_0) |
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| 400 | ); |
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| 401 | |
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| 402 | fpu_cnt_lead0_lvl3 i_fpu_cnt_lead0_lvl3_47_32 ( |
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| 403 | .din_15_8_eq_0 (din_47_40_eq_0), |
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| 404 | .din_15_12_eq_0 (din_47_44_eq_0), |
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| 405 | .lead0_8b_1_hi (lead0_47_40_1), |
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| 406 | .lead0_8b_0_hi (lead0_47_40_0), |
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| 407 | .din_7_0_eq_0 (din_39_32_eq_0), |
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| 408 | .din_7_4_eq_0 (din_39_36_eq_0), |
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| 409 | .lead0_8b_1_lo (lead0_39_32_1), |
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| 410 | .lead0_8b_0_lo (lead0_39_32_0), |
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| 411 | |
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| 412 | .din_15_0_eq_0 (din_47_32_eq_0), |
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| 413 | .lead0_16b_2 (lead0_47_32_2), |
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| 414 | .lead0_16b_1 (lead0_47_32_1), |
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| 415 | .lead0_16b_0 (lead0_47_32_0) |
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| 416 | ); |
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| 417 | |
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| 418 | fpu_cnt_lead0_lvl3 i_fpu_cnt_lead0_lvl3_31_16 ( |
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| 419 | .din_15_8_eq_0 (din_31_24_eq_0), |
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| 420 | .din_15_12_eq_0 (din_31_28_eq_0), |
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| 421 | .lead0_8b_1_hi (lead0_31_24_1), |
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| 422 | .lead0_8b_0_hi (lead0_31_24_0), |
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| 423 | .din_7_0_eq_0 (din_23_16_eq_0), |
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| 424 | .din_7_4_eq_0 (din_23_20_eq_0), |
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| 425 | .lead0_8b_1_lo (lead0_23_16_1), |
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| 426 | .lead0_8b_0_lo (lead0_23_16_0), |
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| 427 | |
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| 428 | .din_15_0_eq_0 (din_31_16_eq_0), |
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| 429 | .lead0_16b_2 (lead0_31_16_2), |
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| 430 | .lead0_16b_1 (lead0_31_16_1), |
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| 431 | .lead0_16b_0 (lead0_31_16_0) |
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| 432 | ); |
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| 433 | |
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| 434 | fpu_cnt_lead0_lvl3 i_fpu_cnt_lead0_lvl3_15_0 ( |
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| 435 | .din_15_8_eq_0 (din_15_8_eq_0), |
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| 436 | .din_15_12_eq_0 (din_15_12_eq_0), |
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| 437 | .lead0_8b_1_hi (lead0_15_8_1), |
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| 438 | .lead0_8b_0_hi (lead0_15_8_0), |
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| 439 | .din_7_0_eq_0 (din_7_0_eq_0), |
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| 440 | .din_7_4_eq_0 (din_7_4_eq_0), |
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| 441 | .lead0_8b_1_lo (lead0_7_0_1), |
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| 442 | .lead0_8b_0_lo (lead0_7_0_0), |
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| 443 | |
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| 444 | .din_15_0_eq_0 (din_15_0_eq_0), |
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| 445 | .lead0_16b_2 (lead0_15_0_2), |
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| 446 | .lead0_16b_1 (lead0_15_0_1), |
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| 447 | .lead0_16b_0 (lead0_15_0_0) |
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| 448 | ); |
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| 449 | |
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| 450 | |
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| 451 | fpu_cnt_lead0_lvl4 i_fpu_cnt_lead0_lvl4_63_32 ( |
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| 452 | .din_31_16_eq_0 (din_63_48_eq_0), |
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| 453 | .din_31_24_eq_0 (din_63_56_eq_0), |
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| 454 | .lead0_16b_2_hi (lead0_63_48_2), |
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| 455 | .lead0_16b_1_hi (lead0_63_48_1), |
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| 456 | .lead0_16b_0_hi (lead0_63_48_0), |
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| 457 | .din_15_0_eq_0 (din_47_32_eq_0), |
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| 458 | .din_15_8_eq_0 (din_47_40_eq_0), |
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| 459 | .lead0_16b_2_lo (lead0_47_32_2), |
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| 460 | .lead0_16b_1_lo (lead0_47_32_1), |
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| 461 | .lead0_16b_0_lo (lead0_47_32_0), |
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| 462 | |
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| 463 | .din_31_0_eq_0 (din_63_32_eq_0), |
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| 464 | .lead0_32b_3 (lead0_63_32_3), |
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| 465 | .lead0_32b_2 (lead0_63_32_2), |
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| 466 | .lead0_32b_1 (lead0_63_32_1), |
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| 467 | .lead0_32b_0 (lead0_63_32_0) |
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| 468 | ); |
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| 469 | |
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| 470 | fpu_cnt_lead0_lvl4 i_fpu_cnt_lead0_lvl4_31_0 ( |
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| 471 | .din_31_16_eq_0 (din_31_16_eq_0), |
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| 472 | .din_31_24_eq_0 (din_31_24_eq_0), |
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| 473 | .lead0_16b_2_hi (lead0_31_16_2), |
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| 474 | .lead0_16b_1_hi (lead0_31_16_1), |
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| 475 | .lead0_16b_0_hi (lead0_31_16_0), |
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| 476 | .din_15_0_eq_0 (din_15_0_eq_0), |
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| 477 | .din_15_8_eq_0 (din_15_8_eq_0), |
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| 478 | .lead0_16b_2_lo (lead0_15_0_2), |
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| 479 | .lead0_16b_1_lo (lead0_15_0_1), |
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| 480 | .lead0_16b_0_lo (lead0_15_0_0), |
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| 481 | |
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| 482 | .din_31_0_eq_0 (din_31_0_eq_0), |
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| 483 | .lead0_32b_3 (lead0_31_0_3), |
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| 484 | .lead0_32b_2 (lead0_31_0_2), |
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| 485 | .lead0_32b_1 (lead0_31_0_1), |
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| 486 | .lead0_32b_0 (lead0_31_0_0) |
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| 487 | ); |
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| 488 | |
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| 489 | |
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| 490 | assign lead0_6= din_63_32_eq_0 && din_31_0_eq_0; |
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| 491 | |
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| 492 | assign lead0_5= (!lead0_6) && din_63_32_eq_0; |
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| 493 | |
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| 494 | assign lead0_4= ((!din_63_32_eq_0) && din_63_48_eq_0) |
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| 495 | || (din_63_32_eq_0 && din_31_16_eq_0 && (!lead0_6)); |
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| 496 | |
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| 497 | assign lead0_3= ((!din_63_32_eq_0) && lead0_63_32_3) |
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| 498 | || (din_63_32_eq_0 && lead0_31_0_3 && (!lead0_6)); |
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| 499 | |
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| 500 | assign lead0_2= ((!din_63_32_eq_0) && lead0_63_32_2) |
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| 501 | || (din_63_32_eq_0 && lead0_31_0_2 && (!lead0_6)); |
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| 502 | |
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| 503 | assign lead0_1= ((!din_63_32_eq_0) && lead0_63_32_1) |
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| 504 | || (din_63_32_eq_0 && lead0_31_0_1 && (!lead0_6)); |
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| 505 | |
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| 506 | assign lead0_0= ((!din_63_32_eq_0) && lead0_63_32_0) |
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| 507 | || (din_63_32_eq_0 && lead0_31_0_0 && (!lead0_6)); |
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| 508 | |
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| 509 | assign lead0[5:0]= {lead0_5, lead0_4, lead0_3, lead0_2, lead0_1, |
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| 510 | lead0_0}; |
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| 511 | |
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| 512 | |
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| 513 | endmodule |
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| 514 | |
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| 515 | |
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