| [6] | 1 | // ========== Copyright Header Begin ========================================== |
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| 2 | // |
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| 3 | // OpenSPARC T1 Processor File: fpu_denorm_frac.v |
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| 4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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| 5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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| 6 | // |
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| 7 | // The above named program is free software; you can redistribute it and/or |
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| 8 | // modify it under the terms of the GNU General Public |
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| 9 | // License version 2 as published by the Free Software Foundation. |
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| 10 | // |
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| 11 | // The above named program is distributed in the hope that it will be |
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| 12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | // General Public License for more details. |
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| 15 | // |
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| 16 | // You should have received a copy of the GNU General Public |
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| 17 | // License along with this work; if not, write to the Free Software |
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| 18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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| 19 | // |
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| 20 | // ========== Copyright Header End ============================================ |
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| 21 | /////////////////////////////////////////////////////////////////////////////// |
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| 22 | // |
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| 23 | // Fraction comparison of two inputs that both have leading 0's. |
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| 24 | // |
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| 25 | /////////////////////////////////////////////////////////////////////////////// |
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| 26 | |
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| 27 | module fpu_denorm_frac ( |
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| 28 | din1, |
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| 29 | din2, |
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| 30 | |
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| 31 | din2_din1_denorm, |
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| 32 | din2_din1_denorm_inv, |
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| 33 | din2_din1_denorma, |
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| 34 | din2_din1_denorm_inva |
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| 35 | ); |
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| 36 | |
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| 37 | |
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| 38 | input [53:0] din1; // input 1- fraction |
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| 39 | input [53:0] din2; // input 2- fraction |
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| 40 | |
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| 41 | output din2_din1_denorm; // input 1 == denorm |
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| 42 | output din2_din1_denorm_inv; // input 1 != denorm |
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| 43 | output din2_din1_denorma; // input 1 == denorm- copy |
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| 44 | output din2_din1_denorm_inva; // input 1 != denorm- copy |
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| 45 | |
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| 46 | |
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| 47 | wire din2_din1_nz_53_51; |
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| 48 | wire din2_din1_denorm_53_51; |
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| 49 | wire din2_din1_nz_50_48; |
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| 50 | wire din2_din1_denorm_50_48; |
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| 51 | wire din2_din1_nz_47_45; |
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| 52 | wire din2_din1_denorm_47_45; |
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| 53 | wire din2_din1_nz_44_42; |
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| 54 | wire din2_din1_denorm_44_42; |
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| 55 | wire din2_din1_nz_41_39; |
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| 56 | wire din2_din1_denorm_41_39; |
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| 57 | wire din2_din1_nz_38_36; |
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| 58 | wire din2_din1_denorm_38_36; |
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| 59 | wire din2_din1_nz_35_33; |
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| 60 | wire din2_din1_denorm_35_33; |
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| 61 | wire din2_din1_nz_32_30; |
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| 62 | wire din2_din1_denorm_32_30; |
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| 63 | wire din2_din1_nz_29_27; |
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| 64 | wire din2_din1_denorm_29_27; |
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| 65 | wire din2_din1_nz_26_24; |
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| 66 | wire din2_din1_denorm_26_24; |
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| 67 | wire din2_din1_nz_23_21; |
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| 68 | wire din2_din1_denorm_23_21; |
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| 69 | wire din2_din1_nz_20_18; |
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| 70 | wire din2_din1_denorm_20_18; |
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| 71 | wire din2_din1_nz_17_15; |
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| 72 | wire din2_din1_denorm_17_15; |
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| 73 | wire din2_din1_nz_14_12; |
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| 74 | wire din2_din1_denorm_14_12; |
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| 75 | wire din2_din1_nz_11_9; |
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| 76 | wire din2_din1_denorm_11_9; |
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| 77 | wire din2_din1_nz_8_6; |
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| 78 | wire din2_din1_denorm_8_6; |
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| 79 | wire din2_din1_nz_5_3; |
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| 80 | wire din2_din1_denorm_5_3; |
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| 81 | wire din2_din1_nz_2_0; |
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| 82 | wire din2_din1_denorm_2_0; |
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| 83 | wire din2_din1_nz_53_45; |
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| 84 | wire din2_din1_denorm_53_45; |
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| 85 | wire din2_din1_nz_44_36; |
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| 86 | wire din2_din1_denorm_44_36; |
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| 87 | wire din2_din1_nz_35_27; |
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| 88 | wire din2_din1_denorm_35_27; |
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| 89 | wire din2_din1_nz_26_18; |
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| 90 | wire din2_din1_denorm_26_18; |
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| 91 | wire din2_din1_nz_17_9; |
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| 92 | wire din2_din1_denorm_17_9; |
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| 93 | wire din2_din1_nz_8_0; |
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| 94 | wire din2_din1_denorm_8_0; |
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| 95 | wire din2_din1_nz_53_27; |
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| 96 | wire din2_din1_denorm_53_27; |
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| 97 | wire din2_din1_nz_26_0; |
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| 98 | wire din2_din1_denorm_26_0; |
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| 99 | wire din2_din1_denorm; |
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| 100 | wire din2_din1_denorm_inv; |
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| 101 | wire din2_din1_denorma; |
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| 102 | wire din2_din1_denorm_inva; |
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| 103 | |
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| 104 | |
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| 105 | fpu_denorm_3b i_fpu_denorm_53_51 ( |
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| 106 | .din1 (din1[53:51]), |
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| 107 | .din2 (din2[53:51]), |
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| 108 | |
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| 109 | .din2_din1_nz (din2_din1_nz_53_51), |
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| 110 | .din2_din1_denorm (din2_din1_denorm_53_51) |
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| 111 | ); |
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| 112 | |
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| 113 | fpu_denorm_3b i_fpu_denorm_50_48 ( |
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| 114 | .din1 (din1[50:48]), |
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| 115 | .din2 (din2[50:48]), |
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| 116 | |
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| 117 | .din2_din1_nz (din2_din1_nz_50_48), |
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| 118 | .din2_din1_denorm (din2_din1_denorm_50_48) |
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| 119 | ); |
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| 120 | |
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| 121 | fpu_denorm_3b i_fpu_denorm_47_45 ( |
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| 122 | .din1 (din1[47:45]), |
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| 123 | .din2 (din2[47:45]), |
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| 124 | |
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| 125 | .din2_din1_nz (din2_din1_nz_47_45), |
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| 126 | .din2_din1_denorm (din2_din1_denorm_47_45) |
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| 127 | ); |
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| 128 | |
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| 129 | fpu_denorm_3b i_fpu_denorm_44_42 ( |
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| 130 | .din1 (din1[44:42]), |
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| 131 | .din2 (din2[44:42]), |
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| 132 | |
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| 133 | .din2_din1_nz (din2_din1_nz_44_42), |
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| 134 | .din2_din1_denorm (din2_din1_denorm_44_42) |
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| 135 | ); |
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| 136 | |
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| 137 | fpu_denorm_3b i_fpu_denorm_41_39 ( |
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| 138 | .din1 (din1[41:39]), |
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| 139 | .din2 (din2[41:39]), |
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| 140 | |
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| 141 | .din2_din1_nz (din2_din1_nz_41_39), |
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| 142 | .din2_din1_denorm (din2_din1_denorm_41_39) |
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| 143 | ); |
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| 144 | |
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| 145 | fpu_denorm_3b i_fpu_denorm_38_36 ( |
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| 146 | .din1 (din1[38:36]), |
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| 147 | .din2 (din2[38:36]), |
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| 148 | |
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| 149 | .din2_din1_nz (din2_din1_nz_38_36), |
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| 150 | .din2_din1_denorm (din2_din1_denorm_38_36) |
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| 151 | ); |
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| 152 | |
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| 153 | fpu_denorm_3b i_fpu_denorm_35_33 ( |
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| 154 | .din1 (din1[35:33]), |
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| 155 | .din2 (din2[35:33]), |
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| 156 | |
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| 157 | .din2_din1_nz (din2_din1_nz_35_33), |
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| 158 | .din2_din1_denorm (din2_din1_denorm_35_33) |
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| 159 | ); |
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| 160 | |
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| 161 | fpu_denorm_3b i_fpu_denorm_32_30 ( |
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| 162 | .din1 (din1[32:30]), |
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| 163 | .din2 (din2[32:30]), |
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| 164 | |
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| 165 | .din2_din1_nz (din2_din1_nz_32_30), |
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| 166 | .din2_din1_denorm (din2_din1_denorm_32_30) |
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| 167 | ); |
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| 168 | |
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| 169 | fpu_denorm_3b i_fpu_denorm_29_27 ( |
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| 170 | .din1 (din1[29:27]), |
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| 171 | .din2 (din2[29:27]), |
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| 172 | |
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| 173 | .din2_din1_nz (din2_din1_nz_29_27), |
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| 174 | .din2_din1_denorm (din2_din1_denorm_29_27) |
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| 175 | ); |
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| 176 | |
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| 177 | fpu_denorm_3b i_fpu_denorm_26_24 ( |
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| 178 | .din1 (din1[26:24]), |
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| 179 | .din2 (din2[26:24]), |
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| 180 | |
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| 181 | .din2_din1_nz (din2_din1_nz_26_24), |
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| 182 | .din2_din1_denorm (din2_din1_denorm_26_24) |
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| 183 | ); |
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| 184 | |
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| 185 | fpu_denorm_3b i_fpu_denorm_23_21 ( |
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| 186 | .din1 (din1[23:21]), |
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| 187 | .din2 (din2[23:21]), |
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| 188 | |
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| 189 | .din2_din1_nz (din2_din1_nz_23_21), |
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| 190 | .din2_din1_denorm (din2_din1_denorm_23_21) |
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| 191 | ); |
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| 192 | |
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| 193 | fpu_denorm_3b i_fpu_denorm_20_18 ( |
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| 194 | .din1 (din1[20:18]), |
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| 195 | .din2 (din2[20:18]), |
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| 196 | |
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| 197 | .din2_din1_nz (din2_din1_nz_20_18), |
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| 198 | .din2_din1_denorm (din2_din1_denorm_20_18) |
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| 199 | ); |
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| 200 | |
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| 201 | fpu_denorm_3b i_fpu_denorm_17_15 ( |
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| 202 | .din1 (din1[17:15]), |
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| 203 | .din2 (din2[17:15]), |
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| 204 | |
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| 205 | .din2_din1_nz (din2_din1_nz_17_15), |
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| 206 | .din2_din1_denorm (din2_din1_denorm_17_15) |
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| 207 | ); |
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| 208 | |
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| 209 | fpu_denorm_3b i_fpu_denorm_14_12 ( |
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| 210 | .din1 (din1[14:12]), |
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| 211 | .din2 (din2[14:12]), |
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| 212 | |
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| 213 | .din2_din1_nz (din2_din1_nz_14_12), |
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| 214 | .din2_din1_denorm (din2_din1_denorm_14_12) |
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| 215 | ); |
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| 216 | |
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| 217 | fpu_denorm_3b i_fpu_denorm_11_9 ( |
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| 218 | .din1 (din1[11:9]), |
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| 219 | .din2 (din2[11:9]), |
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| 220 | |
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| 221 | .din2_din1_nz (din2_din1_nz_11_9), |
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| 222 | .din2_din1_denorm (din2_din1_denorm_11_9) |
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| 223 | ); |
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| 224 | |
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| 225 | fpu_denorm_3b i_fpu_denorm_8_6 ( |
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| 226 | .din1 (din1[8:6]), |
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| 227 | .din2 (din2[8:6]), |
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| 228 | |
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| 229 | .din2_din1_nz (din2_din1_nz_8_6), |
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| 230 | .din2_din1_denorm (din2_din1_denorm_8_6) |
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| 231 | ); |
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| 232 | |
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| 233 | fpu_denorm_3b i_fpu_denorm_5_3 ( |
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| 234 | .din1 (din1[5:3]), |
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| 235 | .din2 (din2[5:3]), |
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| 236 | |
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| 237 | .din2_din1_nz (din2_din1_nz_5_3), |
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| 238 | .din2_din1_denorm (din2_din1_denorm_5_3) |
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| 239 | ); |
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| 240 | |
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| 241 | fpu_denorm_3b i_fpu_denorm_2_0 ( |
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| 242 | .din1 (din1[2:0]), |
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| 243 | .din2 (din2[2:0]), |
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| 244 | |
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| 245 | .din2_din1_nz (din2_din1_nz_2_0), |
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| 246 | .din2_din1_denorm (din2_din1_denorm_2_0) |
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| 247 | ); |
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| 248 | |
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| 249 | |
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| 250 | fpu_denorm_3to1 i_fpu_denorm_53_45 ( |
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| 251 | .din2_din1_nz_hi (din2_din1_nz_53_51), |
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| 252 | .din2_din1_denorm_hi (din2_din1_denorm_53_51), |
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| 253 | .din2_din1_nz_mid (din2_din1_nz_50_48), |
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| 254 | .din2_din1_denorm_mid (din2_din1_denorm_50_48), |
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| 255 | .din2_din1_nz_lo (din2_din1_nz_47_45), |
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| 256 | .din2_din1_denorm_lo (din2_din1_denorm_47_45), |
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| 257 | |
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| 258 | .din2_din1_nz (din2_din1_nz_53_45), |
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| 259 | .din2_din1_denorm (din2_din1_denorm_53_45) |
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| 260 | ); |
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| 261 | |
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| 262 | fpu_denorm_3to1 i_fpu_denorm_44_36 ( |
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| 263 | .din2_din1_nz_hi (din2_din1_nz_44_42), |
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| 264 | .din2_din1_denorm_hi (din2_din1_denorm_44_42), |
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| 265 | .din2_din1_nz_mid (din2_din1_nz_41_39), |
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| 266 | .din2_din1_denorm_mid (din2_din1_denorm_41_39), |
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| 267 | .din2_din1_nz_lo (din2_din1_nz_38_36), |
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| 268 | .din2_din1_denorm_lo (din2_din1_denorm_38_36), |
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| 269 | |
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| 270 | .din2_din1_nz (din2_din1_nz_44_36), |
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| 271 | .din2_din1_denorm (din2_din1_denorm_44_36) |
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| 272 | ); |
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| 273 | |
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| 274 | fpu_denorm_3to1 i_fpu_denorm_35_27 ( |
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| 275 | .din2_din1_nz_hi (din2_din1_nz_35_33), |
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| 276 | .din2_din1_denorm_hi (din2_din1_denorm_35_33), |
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| 277 | .din2_din1_nz_mid (din2_din1_nz_32_30), |
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| 278 | .din2_din1_denorm_mid (din2_din1_denorm_32_30), |
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| 279 | .din2_din1_nz_lo (din2_din1_nz_29_27), |
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| 280 | .din2_din1_denorm_lo (din2_din1_denorm_29_27), |
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| 281 | |
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| 282 | .din2_din1_nz (din2_din1_nz_35_27), |
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| 283 | .din2_din1_denorm (din2_din1_denorm_35_27) |
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| 284 | ); |
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| 285 | |
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| 286 | fpu_denorm_3to1 i_fpu_denorm_26_18 ( |
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| 287 | .din2_din1_nz_hi (din2_din1_nz_26_24), |
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| 288 | .din2_din1_denorm_hi (din2_din1_denorm_26_24), |
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| 289 | .din2_din1_nz_mid (din2_din1_nz_23_21), |
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| 290 | .din2_din1_denorm_mid (din2_din1_denorm_23_21), |
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| 291 | .din2_din1_nz_lo (din2_din1_nz_20_18), |
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| 292 | .din2_din1_denorm_lo (din2_din1_denorm_20_18), |
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| 293 | |
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| 294 | .din2_din1_nz (din2_din1_nz_26_18), |
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| 295 | .din2_din1_denorm (din2_din1_denorm_26_18) |
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| 296 | ); |
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| 297 | |
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| 298 | fpu_denorm_3to1 i_fpu_denorm_17_9 ( |
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| 299 | .din2_din1_nz_hi (din2_din1_nz_17_15), |
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| 300 | .din2_din1_denorm_hi (din2_din1_denorm_17_15), |
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| 301 | .din2_din1_nz_mid (din2_din1_nz_14_12), |
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| 302 | .din2_din1_denorm_mid (din2_din1_denorm_14_12), |
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| 303 | .din2_din1_nz_lo (din2_din1_nz_11_9), |
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| 304 | .din2_din1_denorm_lo (din2_din1_denorm_11_9), |
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| 305 | |
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| 306 | .din2_din1_nz (din2_din1_nz_17_9), |
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| 307 | .din2_din1_denorm (din2_din1_denorm_17_9) |
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| 308 | ); |
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| 309 | |
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| 310 | fpu_denorm_3to1 i_fpu_denorm_8_0 ( |
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| 311 | .din2_din1_nz_hi (din2_din1_nz_8_6), |
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| 312 | .din2_din1_denorm_hi (din2_din1_denorm_8_6), |
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| 313 | .din2_din1_nz_mid (din2_din1_nz_5_3), |
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| 314 | .din2_din1_denorm_mid (din2_din1_denorm_5_3), |
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| 315 | .din2_din1_nz_lo (din2_din1_nz_2_0), |
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| 316 | .din2_din1_denorm_lo (din2_din1_denorm_2_0), |
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| 317 | |
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| 318 | .din2_din1_nz (din2_din1_nz_8_0), |
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| 319 | .din2_din1_denorm (din2_din1_denorm_8_0) |
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| 320 | ); |
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| 321 | |
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| 322 | |
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| 323 | fpu_denorm_3to1 i_fpu_denorm_53_27 ( |
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| 324 | .din2_din1_nz_hi (din2_din1_nz_53_45), |
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| 325 | .din2_din1_denorm_hi (din2_din1_denorm_53_45), |
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| 326 | .din2_din1_nz_mid (din2_din1_nz_44_36), |
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| 327 | .din2_din1_denorm_mid (din2_din1_denorm_44_36), |
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| 328 | .din2_din1_nz_lo (din2_din1_nz_35_27), |
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| 329 | .din2_din1_denorm_lo (din2_din1_denorm_35_27), |
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| 330 | |
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| 331 | .din2_din1_nz (din2_din1_nz_53_27), |
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| 332 | .din2_din1_denorm (din2_din1_denorm_53_27) |
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| 333 | ); |
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| 334 | |
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| 335 | fpu_denorm_3to1 i_fpu_denorm_26_0 ( |
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| 336 | .din2_din1_nz_hi (din2_din1_nz_26_18), |
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| 337 | .din2_din1_denorm_hi (din2_din1_denorm_26_18), |
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| 338 | .din2_din1_nz_mid (din2_din1_nz_17_9), |
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| 339 | .din2_din1_denorm_mid (din2_din1_denorm_17_9), |
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| 340 | .din2_din1_nz_lo (din2_din1_nz_8_0), |
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| 341 | .din2_din1_denorm_lo (din2_din1_denorm_8_0), |
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| 342 | |
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| 343 | .din2_din1_nz (din2_din1_nz_26_0), |
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| 344 | .din2_din1_denorm (din2_din1_denorm_26_0) |
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| 345 | ); |
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| 346 | |
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| 347 | |
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| 348 | assign din2_din1_denorm= (din2_din1_nz_53_27 && din2_din1_denorm_53_27) |
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| 349 | || ((!din2_din1_nz_53_27) && (!din2_din1_nz_26_0)) |
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| 350 | || ((!din2_din1_nz_53_27) && din2_din1_denorm_26_0); |
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| 351 | |
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| 352 | assign din2_din1_denorm_inv= (!din2_din1_denorm); |
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| 353 | |
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| 354 | assign din2_din1_denorma= din2_din1_denorm; |
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| 355 | |
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| 356 | assign din2_din1_denorm_inva= din2_din1_denorm_inv; |
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| 357 | |
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| 358 | |
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| 359 | endmodule |
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| 360 | |
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| 361 | |
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