| 1 | // ========== Copyright Header Begin ========================================== |
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| 2 | // |
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| 3 | // OpenSPARC T1 Processor File: fpu_div.v |
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| 4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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| 5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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| 6 | // |
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| 7 | // The above named program is free software; you can redistribute it and/or |
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| 8 | // modify it under the terms of the GNU General Public |
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| 9 | // License version 2 as published by the Free Software Foundation. |
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| 10 | // |
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| 11 | // The above named program is distributed in the hope that it will be |
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| 12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | // General Public License for more details. |
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| 15 | // |
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| 16 | // You should have received a copy of the GNU General Public |
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| 17 | // License along with this work; if not, write to the Free Software |
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| 18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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| 19 | // |
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| 20 | // ========== Copyright Header End ============================================ |
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| 21 | /////////////////////////////////////////////////////////////////////////////// |
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| 22 | // |
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| 23 | // FPU divide pipe. |
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| 24 | // |
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| 25 | /////////////////////////////////////////////////////////////////////////////// |
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| 26 | |
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| 27 | |
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| 28 | module fpu_div ( |
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| 29 | inq_op, |
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| 30 | inq_rnd_mode, |
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| 31 | inq_id, |
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| 32 | inq_in1, |
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| 33 | inq_in1_53_0_neq_0, |
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| 34 | inq_in1_50_0_neq_0, |
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| 35 | inq_in1_53_32_neq_0, |
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| 36 | inq_in1_exp_eq_0, |
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| 37 | inq_in1_exp_neq_ffs, |
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| 38 | inq_in2, |
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| 39 | inq_in2_53_0_neq_0, |
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| 40 | inq_in2_50_0_neq_0, |
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| 41 | inq_in2_53_32_neq_0, |
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| 42 | inq_in2_exp_eq_0, |
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| 43 | inq_in2_exp_neq_ffs, |
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| 44 | inq_div, |
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| 45 | div_dest_rdy, |
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| 46 | fdiv_clken_l, |
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| 47 | fdiv_clken_l_div_exp_buf1, |
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| 48 | arst_l, |
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| 49 | grst_l, |
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| 50 | rclk, |
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| 51 | |
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| 52 | div_pipe_active, |
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| 53 | d1stg_step, |
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| 54 | d8stg_fdiv_in, |
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| 55 | div_id_out_in, |
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| 56 | div_exc_out, |
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| 57 | d8stg_fdivd, |
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| 58 | d8stg_fdivs, |
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| 59 | div_sign_out, |
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| 60 | div_exp_outa, |
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| 61 | div_frac_outa, |
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| 62 | |
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| 63 | se, |
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| 64 | si, |
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| 65 | so |
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| 66 | ); |
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| 67 | |
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| 68 | |
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| 69 | input [7:0] inq_op; // request opcode to op pipes |
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| 70 | input [1:0] inq_rnd_mode; // request rounding mode to op pipes |
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| 71 | input [4:0] inq_id; // request ID to the operation pipes |
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| 72 | input [63:0] inq_in1; // request operand 1 to op pipes |
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| 73 | input inq_in1_53_0_neq_0; // request operand 1[53:0]!=0 |
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| 74 | input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0 |
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| 75 | input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0 |
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| 76 | input inq_in1_exp_eq_0; // request operand 1 exp==0 |
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| 77 | input inq_in1_exp_neq_ffs; // request operand 1 exp!=0xff's |
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| 78 | input [63:0] inq_in2; // request operand 2 to op pipes |
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| 79 | input inq_in2_53_0_neq_0; // request operand 2[53:0]!=0 |
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| 80 | input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0 |
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| 81 | input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0 |
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| 82 | input inq_in2_exp_eq_0; // request operand 2 exp==0 |
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| 83 | input inq_in2_exp_neq_ffs; // request operand 2 exp!=0xff's |
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| 84 | input inq_div; // divide pipe request |
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| 85 | input div_dest_rdy; // divide result req accepted for CPX |
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| 86 | input fdiv_clken_l; // fdiv clock enable for div_frac_dp |
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| 87 | input fdiv_clken_l_div_exp_buf1; // fdiv clock enable for div_exp_dp |
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| 88 | input arst_l; // global async. reset- asserted low |
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| 89 | input grst_l; // global sync. reset- asserted low |
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| 90 | input rclk; // global clock |
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| 91 | |
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| 92 | output div_pipe_active; // div pipe is executing a valid instr |
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| 93 | output d1stg_step; // divide pipe load |
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| 94 | output d8stg_fdiv_in; // div pipe output request next cycle |
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| 95 | output [9:0] div_id_out_in; // div pipe output ID next cycle |
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| 96 | output [4:0] div_exc_out; // divide pipe result- exception flags |
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| 97 | output d8stg_fdivd; // divide double- divide stage 8 |
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| 98 | output d8stg_fdivs; // divide single- divide stage 8 |
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| 99 | output div_sign_out; // divide sign output |
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| 100 | output [10:0] div_exp_outa; // divide exponent output |
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| 101 | output [51:0] div_frac_outa; // divide fraction output |
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| 102 | |
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| 103 | input se; // scan_enable |
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| 104 | input si; // scan in |
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| 105 | output so; // scan out |
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| 106 | |
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| 107 | |
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| 108 | /////////////////////////////////////////////////////////////////////////////// |
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| 109 | // |
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| 110 | // Outputs of fpu_div_ctl. |
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| 111 | // |
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| 112 | /////////////////////////////////////////////////////////////////////////////// |
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| 113 | |
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| 114 | wire d1stg_snan_sng_in1; // operand 1 is single signalling NaN |
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| 115 | wire d1stg_snan_dbl_in1; // operand 1 is double signalling NaN |
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| 116 | wire d1stg_snan_sng_in2; // operand 2 is single signalling NaN |
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| 117 | wire d1stg_snan_dbl_in2; // operand 2 is double signalling NaN |
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| 118 | wire d1stg_step; // divide pipe load |
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| 119 | wire d1stg_dblop; // double precision operation- d1 stg |
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| 120 | wire d234stg_fdiv; // select line to div_expadd1 |
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| 121 | wire d3stg_fdiv; // divide operation- divide stage 3 |
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| 122 | wire d4stg_fdiv; // divide operation- divide stage 4 |
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| 123 | wire d5stg_fdiva; // divide operation- divide stage 5 |
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| 124 | wire d5stg_fdivb; // divide operation- divide stage 5 |
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| 125 | wire d5stg_fdivs; // divide single- divide stage 5 |
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| 126 | wire d5stg_fdivd; // divide double- divide stage 5 |
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| 127 | wire d6stg_fdiv; // divide operation- divide stage 6 |
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| 128 | wire d6stg_fdivs; // divide single- divide stage 6 |
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| 129 | wire d6stg_fdivd; // divide double- divide stage 6 |
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| 130 | wire d7stg_fdiv; // divide operation- divide stage 7 |
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| 131 | wire d7stg_fdivd; // divide double- divide stage 7 |
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| 132 | wire d8stg_fdiv_in; // div pipe output request next cycle |
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| 133 | wire d8stg_fdivs; // divide single- divide stage 8 |
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| 134 | wire d8stg_fdivd; // divide double- divide stage 8 |
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| 135 | wire [9:0] div_id_out_in; // div pipe output ID next cycle |
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| 136 | wire div_sign_out; // divide sign output |
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| 137 | wire [4:0] div_exc_out; // divide pipe result- exception flags |
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| 138 | wire div_norm_frac_in1_dbl_norm; // select line to div_norm |
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| 139 | wire div_norm_frac_in1_dbl_dnrm; // select line to div_norm |
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| 140 | wire div_norm_frac_in1_sng_norm; // select line to div_norm |
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| 141 | wire div_norm_frac_in1_sng_dnrm; // select line to div_norm |
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| 142 | wire div_norm_frac_in2_dbl_norm; // select line to div_norm |
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| 143 | wire div_norm_frac_in2_dbl_dnrm; // select line to div_norm |
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| 144 | wire div_norm_frac_in2_sng_norm; // select line to div_norm |
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| 145 | wire div_norm_frac_in2_sng_dnrm; // select line to div_norm |
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| 146 | wire div_norm_inf; // select line to div_norm |
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| 147 | wire div_norm_qnan; // select line to div_norm |
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| 148 | wire div_norm_zero; // select line to div_norm |
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| 149 | wire div_frac_add_in2_load; // load enable to div_frac_add_in2 |
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| 150 | wire d6stg_frac_out_shl1; // select line to d6stg_frac |
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| 151 | wire d6stg_frac_out_nosh; // select line to d6stg_frac |
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| 152 | wire div_frac_add_in1_add; // select line to div_frac_add_in1 |
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| 153 | wire div_frac_add_in1_load; // load enable to div_frac_add_in1 |
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| 154 | wire d7stg_rndup_inv; // no rounding increment |
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| 155 | wire d7stg_to_0; // result to max finite on overflow |
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| 156 | wire d7stg_to_0_inv; // result to infinity on overflow |
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| 157 | wire div_frac_out_add_in1; // select line to div_frac_out |
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| 158 | wire div_frac_out_add; // select line to div_frac_out |
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| 159 | wire div_frac_out_shl1_dbl; // select line to div_frac_out |
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| 160 | wire div_frac_out_shl1_sng; // select line to div_frac_out |
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| 161 | wire div_frac_out_of; // select line to div_frac_out |
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| 162 | wire div_frac_out_load; // load enable to div_frac_out |
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| 163 | wire div_expadd1_in1_dbl; // select line to div_expadd1 |
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| 164 | wire div_expadd1_in1_sng; // select line to div_expadd1 |
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| 165 | wire div_expadd1_in2_exp_in2_dbl; // select line to div_expadd1 |
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| 166 | wire div_expadd1_in2_exp_in2_sng; //select line to div_expadd1 |
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| 167 | wire div_exp1_expadd1; // select line to div_exp1 |
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| 168 | wire div_exp1_0835; // select line to div_exp1 |
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| 169 | wire div_exp1_0118; // select line to div_exp1 |
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| 170 | wire div_exp1_zero; // select line to div_exp1 |
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| 171 | wire div_exp1_load; // load enable to div_exp1 |
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| 172 | wire div_expadd2_in1_exp_out; // select line to div_expadd2 |
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| 173 | wire div_expadd2_no_decr_inv; // no exponent decrement |
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| 174 | wire div_expadd2_cin; // carry in to 2nd exponent adder |
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| 175 | wire div_exp_out_expadd22_inv; // select line to div_exp_out |
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| 176 | wire div_exp_out_expadd2; // select line to div_exp_out |
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| 177 | wire div_exp_out_of; // overflow to exponent output |
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| 178 | wire div_exp_out_exp_out; // select line to div_exp_out |
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| 179 | wire div_exp_out_load; // load enable to div_exp_out |
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| 180 | wire div_pipe_active; // div pipe is executing a valid instr |
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| 181 | |
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| 182 | |
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| 183 | /////////////////////////////////////////////////////////////////////////////// |
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| 184 | // |
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| 185 | // Outputs of fpu_div_exp_dp. |
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| 186 | // |
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| 187 | /////////////////////////////////////////////////////////////////////////////// |
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| 188 | |
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| 189 | wire [12:0] div_exp1; // divide exponent- intermediate value |
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| 190 | wire [12:12] div_expadd2; // divide exponent- 2nd adder output |
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| 191 | wire [12:0] div_exp_out; // divide exponent output- fpu_div |
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| 192 | wire [10:0] div_exp_outa; // divide exponent output |
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| 193 | |
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| 194 | |
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| 195 | /////////////////////////////////////////////////////////////////////////////// |
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| 196 | // |
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| 197 | // Outputs of fpu_div_frac_dp. |
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| 198 | // |
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| 199 | /////////////////////////////////////////////////////////////////////////////// |
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| 200 | |
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| 201 | wire [5:0] div_shl_cnt; // divide left shift amount |
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| 202 | wire d6stg_frac_0; // divide fraction[0]- intermediate val |
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| 203 | wire d6stg_frac_1; // divide fraction[1]- intermediate val |
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| 204 | wire d6stg_frac_2; // divide fraction[2]- intermediate val |
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| 205 | wire d6stg_frac_29; // divide fraction[29]- intermediate val |
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| 206 | wire d6stg_frac_30; // divide fraction[30]- intermediate val |
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| 207 | wire d6stg_frac_31; // divide fraction[31]- intermediate val |
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| 208 | wire div_frac_add_in1_neq_0; // div_frac_add_in1 != 0 |
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| 209 | wire div_frac_add_52_inv; // div_frac_add bit[52] inverted |
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| 210 | wire div_frac_add_52_inva; // div_frac_add bit[52] inverted copy |
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| 211 | wire [54:53] div_frac_out; // divide fraction output- fpu_div |
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| 212 | wire [51:0] div_frac_outa; // divide fraction output |
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| 213 | |
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| 214 | |
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| 215 | /////////////////////////////////////////////////////////////////////////////// |
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| 216 | // |
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| 217 | // Instantiations. |
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| 218 | // |
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| 219 | /////////////////////////////////////////////////////////////////////////////// |
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| 220 | |
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| 221 | fpu_div_ctl fpu_div_ctl ( |
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| 222 | .inq_in1_51 (inq_in1[51]), |
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| 223 | .inq_in1_54 (inq_in1[54]), |
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| 224 | .inq_in1_53_0_neq_0 (inq_in1_53_0_neq_0), |
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| 225 | .inq_in1_50_0_neq_0 (inq_in1_50_0_neq_0), |
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| 226 | .inq_in1_53_32_neq_0 (inq_in1_53_32_neq_0), |
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| 227 | .inq_in1_exp_eq_0 (inq_in1_exp_eq_0), |
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| 228 | .inq_in1_exp_neq_ffs (inq_in1_exp_neq_ffs), |
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| 229 | .inq_in2_51 (inq_in2[51]), |
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| 230 | .inq_in2_54 (inq_in2[54]), |
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| 231 | .inq_in2_53_0_neq_0 (inq_in2_53_0_neq_0), |
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| 232 | .inq_in2_50_0_neq_0 (inq_in2_50_0_neq_0), |
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| 233 | .inq_in2_53_32_neq_0 (inq_in2_53_32_neq_0), |
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| 234 | .inq_in2_exp_eq_0 (inq_in2_exp_eq_0), |
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| 235 | .inq_in2_exp_neq_ffs (inq_in2_exp_neq_ffs), |
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| 236 | .inq_op (inq_op[7:0]), |
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| 237 | .div_exp1 (div_exp1[12:0]), |
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| 238 | .div_dest_rdy (div_dest_rdy), |
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| 239 | .inq_rnd_mode (inq_rnd_mode[1:0]), |
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| 240 | .inq_id (inq_id[4:0]), |
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| 241 | .inq_in1_63 (inq_in1[63]), |
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| 242 | .inq_in2_63 (inq_in2[63]), |
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| 243 | .inq_div (inq_div), |
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| 244 | .div_exp_out (div_exp_out[12:0]), |
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| 245 | .div_frac_add_52_inva (div_frac_add_52_inva), |
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| 246 | .div_frac_add_in1_neq_0 (div_frac_add_in1_neq_0), |
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| 247 | .div_frac_out_54 (div_frac_out[54]), |
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| 248 | .d6stg_frac_0 (d6stg_frac_0), |
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| 249 | .d6stg_frac_1 (d6stg_frac_1), |
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| 250 | .d6stg_frac_2 (d6stg_frac_2), |
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| 251 | .d6stg_frac_29 (d6stg_frac_29), |
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| 252 | .d6stg_frac_30 (d6stg_frac_30), |
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| 253 | .d6stg_frac_31 (d6stg_frac_31), |
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| 254 | .div_frac_out_53 (div_frac_out[53]), |
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| 255 | .div_expadd2_12 (div_expadd2[12]), |
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| 256 | .arst_l (arst_l), |
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| 257 | .grst_l (grst_l), |
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| 258 | .rclk (rclk), |
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| 259 | |
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| 260 | .div_pipe_active (div_pipe_active), |
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| 261 | .d1stg_snan_sng_in1 (d1stg_snan_sng_in1), |
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| 262 | .d1stg_snan_dbl_in1 (d1stg_snan_dbl_in1), |
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| 263 | .d1stg_snan_sng_in2 (d1stg_snan_sng_in2), |
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| 264 | .d1stg_snan_dbl_in2 (d1stg_snan_dbl_in2), |
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| 265 | .d1stg_step (d1stg_step), |
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| 266 | .d1stg_dblop (d1stg_dblop), |
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| 267 | .d234stg_fdiv (d234stg_fdiv), |
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| 268 | .d3stg_fdiv (d3stg_fdiv), |
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| 269 | .d4stg_fdiv (d4stg_fdiv), |
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| 270 | .d5stg_fdiva (d5stg_fdiva), |
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| 271 | .d5stg_fdivb (d5stg_fdivb), |
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| 272 | .d5stg_fdivs (d5stg_fdivs), |
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| 273 | .d5stg_fdivd (d5stg_fdivd), |
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| 274 | .d6stg_fdiv (d6stg_fdiv), |
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| 275 | .d6stg_fdivs (d6stg_fdivs), |
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| 276 | .d6stg_fdivd (d6stg_fdivd), |
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| 277 | .d7stg_fdiv (d7stg_fdiv), |
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| 278 | .d7stg_fdivd (d7stg_fdivd), |
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| 279 | .d8stg_fdiv_in (d8stg_fdiv_in), |
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| 280 | .d8stg_fdivs (d8stg_fdivs), |
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| 281 | .d8stg_fdivd (d8stg_fdivd), |
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| 282 | .div_id_out_in (div_id_out_in[9:0]), |
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| 283 | .div_sign_out (div_sign_out), |
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| 284 | .div_exc_out (div_exc_out[4:0]), |
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| 285 | .div_norm_frac_in1_dbl_norm (div_norm_frac_in1_dbl_norm), |
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| 286 | .div_norm_frac_in1_dbl_dnrm (div_norm_frac_in1_dbl_dnrm), |
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| 287 | .div_norm_frac_in1_sng_norm (div_norm_frac_in1_sng_norm), |
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| 288 | .div_norm_frac_in1_sng_dnrm (div_norm_frac_in1_sng_dnrm), |
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| 289 | .div_norm_frac_in2_dbl_norm (div_norm_frac_in2_dbl_norm), |
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| 290 | .div_norm_frac_in2_dbl_dnrm (div_norm_frac_in2_dbl_dnrm), |
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| 291 | .div_norm_frac_in2_sng_norm (div_norm_frac_in2_sng_norm), |
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| 292 | .div_norm_frac_in2_sng_dnrm (div_norm_frac_in2_sng_dnrm), |
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| 293 | .div_norm_inf (div_norm_inf), |
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| 294 | .div_norm_qnan (div_norm_qnan), |
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| 295 | .div_norm_zero (div_norm_zero), |
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| 296 | .div_frac_add_in2_load (div_frac_add_in2_load), |
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| 297 | .d6stg_frac_out_shl1 (d6stg_frac_out_shl1), |
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| 298 | .d6stg_frac_out_nosh (d6stg_frac_out_nosh), |
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| 299 | .div_frac_add_in1_add (div_frac_add_in1_add), |
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| 300 | .div_frac_add_in1_load (div_frac_add_in1_load), |
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| 301 | .d7stg_rndup_inv (d7stg_rndup_inv), |
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| 302 | .d7stg_to_0 (d7stg_to_0), |
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| 303 | .d7stg_to_0_inv (d7stg_to_0_inv), |
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| 304 | .div_frac_out_add_in1 (div_frac_out_add_in1), |
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| 305 | .div_frac_out_add (div_frac_out_add), |
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| 306 | .div_frac_out_shl1_dbl (div_frac_out_shl1_dbl), |
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| 307 | .div_frac_out_shl1_sng (div_frac_out_shl1_sng), |
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| 308 | .div_frac_out_of (div_frac_out_of), |
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| 309 | .div_frac_out_load (div_frac_out_load), |
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| 310 | .div_expadd1_in1_dbl (div_expadd1_in1_dbl), |
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| 311 | .div_expadd1_in1_sng (div_expadd1_in1_sng), |
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| 312 | .div_expadd1_in2_exp_in2_dbl (div_expadd1_in2_exp_in2_dbl), |
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| 313 | .div_expadd1_in2_exp_in2_sng (div_expadd1_in2_exp_in2_sng), |
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| 314 | .div_exp1_expadd1 (div_exp1_expadd1), |
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| 315 | .div_exp1_0835 (div_exp1_0835), |
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| 316 | .div_exp1_0118 (div_exp1_0118), |
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| 317 | .div_exp1_zero (div_exp1_zero), |
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| 318 | .div_exp1_load (div_exp1_load), |
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| 319 | .div_expadd2_in1_exp_out (div_expadd2_in1_exp_out), |
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| 320 | .div_expadd2_no_decr_inv (div_expadd2_no_decr_inv), |
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| 321 | .div_expadd2_cin (div_expadd2_cin), |
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| 322 | .div_exp_out_expadd22_inv (div_exp_out_expadd22_inv), |
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| 323 | .div_exp_out_expadd2 (div_exp_out_expadd2), |
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| 324 | .div_exp_out_of (div_exp_out_of), |
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| 325 | .div_exp_out_exp_out (div_exp_out_exp_out), |
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| 326 | .div_exp_out_load (div_exp_out_load), |
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| 327 | |
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| 328 | .se (se), |
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| 329 | .si (si), |
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| 330 | .so (scan_out_fpu_div_ctl) |
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| 331 | ); |
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| 332 | |
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| 333 | |
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| 334 | fpu_div_exp_dp fpu_div_exp_dp ( |
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| 335 | .inq_in1 (inq_in1[62:52]), |
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| 336 | .inq_in2 (inq_in2[62:52]), |
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| 337 | .d1stg_step (d1stg_step), |
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| 338 | .d234stg_fdiv (d234stg_fdiv), |
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| 339 | .div_expadd1_in1_dbl (div_expadd1_in1_dbl), |
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| 340 | .div_expadd1_in1_sng (div_expadd1_in1_sng), |
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| 341 | .div_expadd1_in2_exp_in2_dbl (div_expadd1_in2_exp_in2_dbl), |
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| 342 | .div_expadd1_in2_exp_in2_sng (div_expadd1_in2_exp_in2_sng), |
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| 343 | .d3stg_fdiv (d3stg_fdiv), |
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| 344 | .d4stg_fdiv (d4stg_fdiv), |
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| 345 | .div_shl_cnt (div_shl_cnt[5:0]), |
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| 346 | .div_exp1_expadd1 (div_exp1_expadd1), |
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| 347 | .div_exp1_0835 (div_exp1_0835), |
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| 348 | .div_exp1_0118 (div_exp1_0118), |
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| 349 | .div_exp1_zero (div_exp1_zero), |
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| 350 | .div_exp1_load (div_exp1_load), |
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| 351 | .div_expadd2_in1_exp_out (div_expadd2_in1_exp_out), |
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| 352 | .d5stg_fdiva (d5stg_fdiva), |
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| 353 | .d5stg_fdivd (d5stg_fdivd), |
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| 354 | .d5stg_fdivs (d5stg_fdivs), |
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| 355 | .d6stg_fdiv (d6stg_fdiv), |
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| 356 | .d7stg_fdiv (d7stg_fdiv), |
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| 357 | .div_expadd2_no_decr_inv (div_expadd2_no_decr_inv), |
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| 358 | .div_expadd2_cin (div_expadd2_cin), |
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| 359 | .div_exp_out_expadd2 (div_exp_out_expadd2), |
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| 360 | .div_exp_out_expadd22_inv (div_exp_out_expadd22_inv), |
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| 361 | .div_exp_out_of (div_exp_out_of), |
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| 362 | .d7stg_to_0_inv (d7stg_to_0_inv), |
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| 363 | .d7stg_fdivd (d7stg_fdivd), |
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| 364 | .div_exp_out_exp_out (div_exp_out_exp_out), |
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| 365 | .d7stg_rndup_inv (d7stg_rndup_inv), |
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| 366 | .div_frac_add_52_inv (div_frac_add_52_inv), |
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| 367 | .div_exp_out_load (div_exp_out_load), |
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| 368 | .fdiv_clken_l (fdiv_clken_l_div_exp_buf1), |
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| 369 | .rclk (rclk), |
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| 370 | |
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| 371 | .div_exp1 (div_exp1[12:0]), |
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| 372 | .div_expadd2_12 (div_expadd2[12]), |
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| 373 | .div_exp_out (div_exp_out[12:0]), |
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| 374 | .div_exp_outa (div_exp_outa[10:0]), |
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| 375 | |
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| 376 | .se (se), |
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| 377 | .si (scan_out_fpu_div_ctl), |
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| 378 | .so (scan_out_fpu_div_exp_dp) |
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| 379 | ); |
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| 380 | |
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| 381 | |
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| 382 | fpu_div_frac_dp fpu_div_frac_dp ( |
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| 383 | .inq_in1 (inq_in1[54:0]), |
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| 384 | .inq_in2 (inq_in2[54:0]), |
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| 385 | .d1stg_step (d1stg_step), |
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| 386 | .div_norm_frac_in1_dbl_norm (div_norm_frac_in1_dbl_norm), |
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| 387 | .div_norm_frac_in1_dbl_dnrm (div_norm_frac_in1_dbl_dnrm), |
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| 388 | .div_norm_frac_in1_sng_norm (div_norm_frac_in1_sng_norm), |
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| 389 | .div_norm_frac_in1_sng_dnrm (div_norm_frac_in1_sng_dnrm), |
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| 390 | .div_norm_frac_in2_dbl_norm (div_norm_frac_in2_dbl_norm), |
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| 391 | .div_norm_frac_in2_dbl_dnrm (div_norm_frac_in2_dbl_dnrm), |
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| 392 | .div_norm_frac_in2_sng_norm (div_norm_frac_in2_sng_norm), |
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| 393 | .div_norm_frac_in2_sng_dnrm (div_norm_frac_in2_sng_dnrm), |
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| 394 | .div_norm_inf (div_norm_inf), |
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| 395 | .div_norm_qnan (div_norm_qnan), |
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| 396 | .d1stg_dblop (d1stg_dblop), |
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| 397 | .div_norm_zero (div_norm_zero), |
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| 398 | .d1stg_snan_dbl_in1 (d1stg_snan_dbl_in1), |
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| 399 | .d1stg_snan_sng_in1 (d1stg_snan_sng_in1), |
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| 400 | .d1stg_snan_dbl_in2 (d1stg_snan_dbl_in2), |
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| 401 | .d1stg_snan_sng_in2 (d1stg_snan_sng_in2), |
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| 402 | .d3stg_fdiv (d3stg_fdiv), |
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| 403 | .d6stg_fdiv (d6stg_fdiv), |
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| 404 | .d6stg_fdivd (d6stg_fdivd), |
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| 405 | .d6stg_fdivs (d6stg_fdivs), |
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| 406 | .div_frac_add_in2_load (div_frac_add_in2_load), |
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| 407 | .d6stg_frac_out_shl1 (d6stg_frac_out_shl1), |
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| 408 | .d6stg_frac_out_nosh (d6stg_frac_out_nosh), |
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| 409 | .d4stg_fdiv (d4stg_fdiv), |
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| 410 | .div_frac_add_in1_add (div_frac_add_in1_add), |
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| 411 | .div_frac_add_in1_load (div_frac_add_in1_load), |
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| 412 | .d5stg_fdivb (d5stg_fdivb), |
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| 413 | .div_frac_out_add_in1 (div_frac_out_add_in1), |
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| 414 | .div_frac_out_add (div_frac_out_add), |
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| 415 | .div_frac_out_shl1_dbl (div_frac_out_shl1_dbl), |
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| 416 | .div_frac_out_shl1_sng (div_frac_out_shl1_sng), |
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| 417 | .div_frac_out_of (div_frac_out_of), |
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| 418 | .d7stg_to_0 (d7stg_to_0), |
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| 419 | .div_frac_out_load (div_frac_out_load), |
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| 420 | .fdiv_clken_l (fdiv_clken_l), |
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| 421 | .rclk (rclk), |
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| 422 | |
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| 423 | .div_shl_cnt (div_shl_cnt[5:0]), |
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| 424 | .d6stg_frac_0 (d6stg_frac_0), |
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| 425 | .d6stg_frac_1 (d6stg_frac_1), |
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| 426 | .d6stg_frac_2 (d6stg_frac_2), |
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| 427 | .d6stg_frac_29 (d6stg_frac_29), |
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| 428 | .d6stg_frac_30 (d6stg_frac_30), |
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| 429 | .d6stg_frac_31 (d6stg_frac_31), |
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| 430 | .div_frac_add_in1_neq_0 (div_frac_add_in1_neq_0), |
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| 431 | .div_frac_add_52_inv (div_frac_add_52_inv), |
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| 432 | .div_frac_add_52_inva (div_frac_add_52_inva), |
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| 433 | .div_frac_out_54_53 (div_frac_out[54:53]), |
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| 434 | .div_frac_outa (div_frac_outa[51:0]), |
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| 435 | |
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| 436 | .se (se), |
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| 437 | .si (scan_out_fpu_div_exp_dp), |
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| 438 | .so (so) |
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| 439 | ); |
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| 440 | |
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| 441 | |
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| 442 | endmodule |
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| 443 | |
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| 444 | |
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