[6] | 1 | // ========== Copyright Header Begin ========================================== |
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| 2 | // |
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| 3 | // OpenSPARC T1 Processor File: fpu_div_exp_dp.v |
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| 4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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| 5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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| 6 | // |
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| 7 | // The above named program is free software; you can redistribute it and/or |
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| 8 | // modify it under the terms of the GNU General Public |
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| 9 | // License version 2 as published by the Free Software Foundation. |
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| 10 | // |
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| 11 | // The above named program is distributed in the hope that it will be |
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| 12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | // General Public License for more details. |
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| 15 | // |
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| 16 | // You should have received a copy of the GNU General Public |
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| 17 | // License along with this work; if not, write to the Free Software |
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| 18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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| 19 | // |
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| 20 | // ========== Copyright Header End ============================================ |
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| 21 | /////////////////////////////////////////////////////////////////////////////// |
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| 22 | // |
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| 23 | // Divide pipeline exponent datapath. |
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| 24 | // |
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| 25 | /////////////////////////////////////////////////////////////////////////////// |
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| 26 | |
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| 27 | module fpu_div_exp_dp ( |
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| 28 | inq_in1, |
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| 29 | inq_in2, |
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| 30 | d1stg_step, |
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| 31 | d234stg_fdiv, |
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| 32 | div_expadd1_in1_dbl, |
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| 33 | div_expadd1_in1_sng, |
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| 34 | div_expadd1_in2_exp_in2_dbl, |
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| 35 | div_expadd1_in2_exp_in2_sng, |
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| 36 | d3stg_fdiv, |
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| 37 | d4stg_fdiv, |
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| 38 | div_shl_cnt, |
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| 39 | div_exp1_expadd1, |
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| 40 | div_exp1_0835, |
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| 41 | div_exp1_0118, |
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| 42 | div_exp1_zero, |
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| 43 | div_exp1_load, |
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| 44 | div_expadd2_in1_exp_out, |
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| 45 | d5stg_fdiva, |
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| 46 | d5stg_fdivd, |
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| 47 | d5stg_fdivs, |
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| 48 | d6stg_fdiv, |
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| 49 | d7stg_fdiv, |
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| 50 | div_expadd2_no_decr_inv, |
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| 51 | div_expadd2_cin, |
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| 52 | div_exp_out_expadd2, |
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| 53 | div_exp_out_expadd22_inv, |
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| 54 | div_exp_out_of, |
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| 55 | d7stg_to_0_inv, |
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| 56 | d7stg_fdivd, |
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| 57 | div_exp_out_exp_out, |
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| 58 | d7stg_rndup_inv, |
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| 59 | div_frac_add_52_inv, |
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| 60 | div_exp_out_load, |
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| 61 | fdiv_clken_l, |
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| 62 | rclk, |
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| 63 | |
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| 64 | div_exp1, |
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| 65 | div_expadd2_12, |
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| 66 | div_exp_out, |
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| 67 | div_exp_outa, |
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| 68 | |
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| 69 | se, |
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| 70 | si, |
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| 71 | so |
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| 72 | ); |
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| 73 | |
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| 74 | |
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| 75 | input [62:52] inq_in1; // request operand 1 to op pipes |
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| 76 | input [62:52] inq_in2; // request operand 2 to op pipes |
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| 77 | input d1stg_step; // divide pipe load |
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| 78 | input d234stg_fdiv; // select line to div_expadd1 |
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| 79 | input div_expadd1_in1_dbl; // select line to div_expadd1 |
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| 80 | input div_expadd1_in1_sng; // select line to div_expadd1 |
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| 81 | input div_expadd1_in2_exp_in2_dbl; // select line to div_expadd1 |
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| 82 | input div_expadd1_in2_exp_in2_sng; //select line to div_expadd1 |
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| 83 | input d3stg_fdiv; // divide operation- divide stage 3 |
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| 84 | input d4stg_fdiv; // divide operation- divide stage 4 |
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| 85 | input [5:0] div_shl_cnt; // divide left shift amount |
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| 86 | input div_exp1_expadd1; // select line to div_exp1 |
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| 87 | input div_exp1_0835; // select line to div_exp1 |
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| 88 | input div_exp1_0118; // select line to div_exp1 |
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| 89 | input div_exp1_zero; // select line to div_exp1 |
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| 90 | input div_exp1_load; // load enable to div_exp1 |
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| 91 | input div_expadd2_in1_exp_out; // select line to div_expadd2 |
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| 92 | input d5stg_fdiva; // divide operation- divide stage 5 |
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| 93 | input d5stg_fdivd; // divide double- divide stage 5 |
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| 94 | input d5stg_fdivs; // divide single- divide stage 5 |
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| 95 | input d6stg_fdiv; // divide operation- divide stage 6 |
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| 96 | input d7stg_fdiv; // divide operation- divide stage 7 |
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| 97 | input div_expadd2_no_decr_inv; // no exponent decrement |
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| 98 | input div_expadd2_cin; // carry in to 2nd exponent adder |
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| 99 | input div_exp_out_expadd2; // select line to div_exp_out |
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| 100 | input div_exp_out_expadd22_inv; // select line to div_exp_out |
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| 101 | input div_exp_out_of; // overflow to exponent output |
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| 102 | input d7stg_to_0_inv; // result to infinity on overflow |
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| 103 | input d7stg_fdivd; // divide double- divide stage 7 |
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| 104 | input div_exp_out_exp_out; // select line to div_exp_out |
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| 105 | input d7stg_rndup_inv; // no rounding increment |
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| 106 | input div_frac_add_52_inv; // div_frac_add bit[52] inverted |
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| 107 | input div_exp_out_load; // load enable to div_exp_out |
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| 108 | input fdiv_clken_l; // div pipe clk enable - asserted low |
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| 109 | input rclk; // global clock |
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| 110 | |
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| 111 | output [12:0] div_exp1; // divide exponent- intermediate value |
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| 112 | output div_expadd2_12; // divide exponent- 2nd adder output |
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| 113 | output [12:0] div_exp_out; // divide exponent output |
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| 114 | output [10:0] div_exp_outa; // divide exponent output- buffered copy |
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| 115 | |
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| 116 | input se; // scan_enable |
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| 117 | input si; // scan in |
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| 118 | output so; // scan out |
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| 119 | |
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| 120 | |
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| 121 | wire [10:0] div_exp_in1; |
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| 122 | wire [10:0] div_exp_in2; |
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| 123 | wire [12:0] div_expadd1_in1; |
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| 124 | wire [12:0] div_expadd1_in2; |
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| 125 | wire [12:0] div_expadd1; |
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| 126 | wire [12:0] div_exp1_in; |
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| 127 | wire [12:0] div_exp1; |
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| 128 | wire [12:0] div_expadd2_in1; |
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| 129 | wire [12:0] div_expadd2_in2; |
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| 130 | wire [12:0] div_expadd2; |
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| 131 | wire div_expadd2_12; |
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| 132 | wire [12:0] div_exp_out_in; |
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| 133 | wire [12:0] div_exp_out; |
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| 134 | wire [10:0] div_exp_outa; |
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| 135 | |
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| 136 | |
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| 137 | wire se_l; |
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| 138 | |
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| 139 | assign se_l = ~se; |
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| 140 | |
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| 141 | clken_buf ckbuf_div_exp_dp ( |
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| 142 | .clk(clk), |
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| 143 | .rclk(rclk), |
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| 144 | .enb_l(fdiv_clken_l), |
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| 145 | .tmb_l(se_l) |
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| 146 | ); |
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| 147 | |
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| 148 | /////////////////////////////////////////////////////////////////////////////// |
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| 149 | // |
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| 150 | // Divide exponent inputs. |
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| 151 | // |
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| 152 | /////////////////////////////////////////////////////////////////////////////// |
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| 153 | |
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| 154 | dffe_s #(11) i_div_exp_in1 ( |
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| 155 | .din (inq_in1[62:52]), |
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| 156 | .en (d1stg_step), |
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| 157 | .clk (clk), |
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| 158 | |
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| 159 | .q (div_exp_in1[10:0]), |
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| 160 | |
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| 161 | .se (se), |
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| 162 | .si (), |
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| 163 | .so () |
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| 164 | ); |
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| 165 | |
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| 166 | dffe_s #(11) i_div_exp_in2 ( |
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| 167 | .din (inq_in2[62:52]), |
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| 168 | .en (d1stg_step), |
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| 169 | .clk (clk), |
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| 170 | |
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| 171 | .q (div_exp_in2[10:0]), |
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| 172 | |
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| 173 | .se (se), |
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| 174 | .si (), |
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| 175 | .so () |
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| 176 | ); |
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| 177 | |
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| 178 | |
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| 179 | /////////////////////////////////////////////////////////////////////////////// |
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| 180 | // |
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| 181 | // Divide exponent adder in the front end of the divide pipe. |
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| 182 | // |
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| 183 | /////////////////////////////////////////////////////////////////////////////// |
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| 184 | |
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| 185 | assign div_expadd1_in1[12:0]= ({13{d234stg_fdiv}} |
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| 186 | & div_exp1[12:0]) |
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| 187 | | ({13{div_expadd1_in1_dbl}} |
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| 188 | & {2'b0, div_exp_in1[10:0]}) |
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| 189 | | ({13{div_expadd1_in1_sng}} |
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| 190 | & {5'b0, div_exp_in1[10:3]}); |
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| 191 | |
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| 192 | assign div_expadd1_in2[12:0]= ({13{div_expadd1_in1_dbl}} |
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| 193 | & 13'h0436) |
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| 194 | | ({13{div_expadd1_in1_sng}} |
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| 195 | & 13'h0099) |
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| 196 | | ({13{div_expadd1_in2_exp_in2_dbl}} |
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| 197 | & (~{2'b0, div_exp_in2[10:0]})) |
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| 198 | | ({13{div_expadd1_in2_exp_in2_sng}} |
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| 199 | & (~{5'b0, div_exp_in2[10:3]})) |
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| 200 | | ({13{d3stg_fdiv}} |
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| 201 | & (~{7'b0, div_shl_cnt[5:0]})) |
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| 202 | | ({13{d4stg_fdiv}} |
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| 203 | & {7'b0, div_shl_cnt[5:0]}); |
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| 204 | |
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| 205 | assign div_expadd1[12:0]= (div_expadd1_in1[12:0] |
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| 206 | + div_expadd1_in2[12:0]); |
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| 207 | |
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| 208 | assign div_exp1_in[12:0]= ({13{div_exp1_expadd1}} |
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| 209 | & div_expadd1[12:0]) |
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| 210 | | ({13{div_exp1_0835}} |
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| 211 | & 13'h0835) |
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| 212 | | ({13{div_exp1_0118}} |
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| 213 | & 13'h0118) |
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| 214 | | ({13{div_exp1_zero}} |
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| 215 | & 13'h0000); |
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| 216 | |
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| 217 | dffe_s #(13) i_div_exp1 ( |
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| 218 | .din (div_exp1_in[12:0]), |
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| 219 | .en (div_exp1_load), |
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| 220 | .clk (clk), |
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| 221 | |
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| 222 | .q (div_exp1[12:0]), |
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| 223 | |
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| 224 | .se (se), |
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| 225 | .si (), |
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| 226 | .so () |
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| 227 | ); |
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| 228 | |
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| 229 | |
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| 230 | /////////////////////////////////////////////////////////////////////////////// |
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| 231 | // |
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| 232 | // Divide exponent adder in the back end of the divide pipe. |
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| 233 | // |
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| 234 | /////////////////////////////////////////////////////////////////////////////// |
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| 235 | |
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| 236 | assign div_expadd2_in1[12:0]= ({13{div_expadd2_in1_exp_out}} |
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| 237 | & div_exp_out[12:0]) |
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| 238 | | ({13{d5stg_fdiva}} |
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| 239 | & div_exp1[12:0]); |
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| 240 | |
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| 241 | assign div_expadd2_in2[12:0]= ({13{d5stg_fdiva}} |
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| 242 | & {7'h7f, d5stg_fdivs, 1'b0, d5stg_fdivd, |
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| 243 | d5stg_fdivs, 1'b1, d5stg_fdivs}) |
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| 244 | | ({13{d6stg_fdiv}} |
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| 245 | & {13{div_expadd2_no_decr_inv}}) |
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| 246 | | ({13{d7stg_fdiv}} |
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| 247 | & 13'h0000); |
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| 248 | |
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| 249 | assign div_expadd2[12:0]= (div_expadd2_in1[12:0] |
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| 250 | + div_expadd2_in2[12:0] |
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| 251 | + {12'b0, div_expadd2_cin}); |
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| 252 | assign div_expadd2_12 = div_expadd2[12]; |
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| 253 | |
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| 254 | assign div_exp_out_in[12:0]= ({13{(div_exp_out_expadd2 |
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| 255 | && (!(div_frac_add_52_inv |
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| 256 | && div_exp_out_expadd22_inv)))}} |
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| 257 | & div_expadd2[12:0]) |
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| 258 | | ({13{div_exp_out_of}} |
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| 259 | & {2'b00, {3{d7stg_fdivd}}, 7'h7f, d7stg_to_0_inv}) |
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| 260 | | ({13{(div_exp_out_exp_out |
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| 261 | && (div_frac_add_52_inv || d7stg_rndup_inv))}} |
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| 262 | & div_exp_out[12:0]); |
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| 263 | |
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| 264 | dffe_s #(13) i_div_exp_out ( |
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| 265 | .din (div_exp_out_in[12:0]), |
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| 266 | .en (div_exp_out_load), |
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| 267 | .clk (clk), |
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| 268 | |
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| 269 | .q (div_exp_out[12:0]), |
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| 270 | |
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| 271 | .se (se), |
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| 272 | .si (), |
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| 273 | .so () |
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| 274 | ); |
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| 275 | |
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| 276 | assign div_exp_outa[10:0]= div_exp_out[10:0]; |
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| 277 | |
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| 278 | |
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| 279 | endmodule |
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| 280 | |
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| 281 | |
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