1 | // ========== Copyright Header Begin ========================================== |
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2 | // |
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3 | // OpenSPARC T1 Processor File: fpu_in2_gt_in1_2b.v |
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4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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6 | // |
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7 | // The above named program is free software; you can redistribute it and/or |
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8 | // modify it under the terms of the GNU General Public |
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9 | // License version 2 as published by the Free Software Foundation. |
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10 | // |
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11 | // The above named program is distributed in the hope that it will be |
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12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | // General Public License for more details. |
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15 | // |
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16 | // You should have received a copy of the GNU General Public |
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17 | // License along with this work; if not, write to the Free Software |
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18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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19 | // |
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20 | // ========== Copyright Header End ============================================ |
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21 | /////////////////////////////////////////////////////////////////////////////// |
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22 | // |
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23 | // Two bit comparison of two inputs that can have any value. |
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24 | // |
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25 | /////////////////////////////////////////////////////////////////////////////// |
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26 | |
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27 | module fpu_in2_gt_in1_2b ( |
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28 | din1, |
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29 | din2, |
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30 | |
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31 | din2_neq_din1, |
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32 | din2_gt_din1 |
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33 | ); |
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34 | |
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35 | |
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36 | input [1:0] din1; // input 1- 3 bits |
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37 | input [1:0] din2; // input 2- 3 bits |
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38 | |
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39 | output din2_neq_din1; // input 2 doesn't equal input 1 |
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40 | output din2_gt_din1; // input 2 is greater than input 1 |
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41 | |
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42 | |
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43 | wire [1:0] din2_eq_din1; |
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44 | wire din2_neq_din1; |
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45 | wire din2_gt_din1; |
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46 | |
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47 | |
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48 | assign din2_eq_din1[1:0]= (~(din1 ^ din2)); |
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49 | |
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50 | assign din2_neq_din1= (!(&din2_eq_din1)); |
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51 | |
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52 | assign din2_gt_din1= ((!din1[1]) && din2[1]) |
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53 | || (din2_eq_din1[1] && (!din1[0]) && din2[0]); |
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54 | |
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55 | |
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56 | endmodule |
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57 | |
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58 | |
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