[6] | 1 | // ========== Copyright Header Begin ========================================== |
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| 2 | // |
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| 3 | // OpenSPARC T1 Processor File: fpu_mul.v |
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| 4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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| 5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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| 6 | // |
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| 7 | // The above named program is free software; you can redistribute it and/or |
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| 8 | // modify it under the terms of the GNU General Public |
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| 9 | // License version 2 as published by the Free Software Foundation. |
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| 10 | // |
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| 11 | // The above named program is distributed in the hope that it will be |
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| 12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 14 | // General Public License for more details. |
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| 15 | // |
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| 16 | // You should have received a copy of the GNU General Public |
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| 17 | // License along with this work; if not, write to the Free Software |
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| 18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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| 19 | // |
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| 20 | // ========== Copyright Header End ============================================ |
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| 21 | /////////////////////////////////////////////////////////////////////////////// |
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| 22 | // |
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| 23 | // FPU multiply pipe. |
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| 24 | // |
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| 25 | /////////////////////////////////////////////////////////////////////////////// |
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| 26 | |
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| 27 | |
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| 28 | module fpu_mul ( |
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| 29 | inq_op, |
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| 30 | inq_rnd_mode, |
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| 31 | inq_id, |
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| 32 | inq_in1, |
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| 33 | inq_in1_53_0_neq_0, |
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| 34 | inq_in1_50_0_neq_0, |
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| 35 | inq_in1_53_32_neq_0, |
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| 36 | inq_in1_exp_eq_0, |
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| 37 | inq_in1_exp_neq_ffs, |
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| 38 | inq_in2, |
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| 39 | inq_in2_53_0_neq_0, |
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| 40 | inq_in2_50_0_neq_0, |
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| 41 | inq_in2_53_32_neq_0, |
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| 42 | inq_in2_exp_eq_0, |
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| 43 | inq_in2_exp_neq_ffs, |
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| 44 | inq_mul, |
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| 45 | mul_dest_rdy, |
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| 46 | mul_dest_rdya, |
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| 47 | fmul_clken_l, |
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| 48 | fmul_clken_l_buf1, |
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| 49 | arst_l, |
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| 50 | grst_l, |
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| 51 | rclk, |
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| 52 | |
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| 53 | mul_pipe_active, |
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| 54 | m1stg_step, |
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| 55 | m6stg_fmul_in, |
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| 56 | m6stg_id_in, |
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| 57 | mul_exc_out, |
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| 58 | m6stg_fmul_dbl_dst, |
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| 59 | m6stg_fmuls, |
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| 60 | mul_sign_out, |
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| 61 | mul_exp_out, |
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| 62 | mul_frac_out, |
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| 63 | |
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| 64 | se_mul, |
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| 65 | se_mul64, |
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| 66 | si, |
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| 67 | so |
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| 68 | ); |
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| 69 | |
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| 70 | |
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| 71 | input [7:0] inq_op; // request opcode to op pipes |
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| 72 | input [1:0] inq_rnd_mode; // request rounding mode to op pipes |
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| 73 | input [4:0] inq_id; // request ID to the operation pipes |
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| 74 | input [63:0] inq_in1; // request operand 1 to op pipes |
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| 75 | input inq_in1_53_0_neq_0; // request operand 1[53:0]!=0 |
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| 76 | input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0 |
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| 77 | input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0 |
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| 78 | input inq_in1_exp_eq_0; // request operand 1 exp==0 |
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| 79 | input inq_in1_exp_neq_ffs; // request operand 1 exp!=0xff's |
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| 80 | input [63:0] inq_in2; // request operand 2 to op pipes |
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| 81 | input inq_in2_53_0_neq_0; // request operand 2[53:0]!=0 |
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| 82 | input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0 |
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| 83 | input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0 |
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| 84 | input inq_in2_exp_eq_0; // request operand 2 exp==0 |
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| 85 | input inq_in2_exp_neq_ffs; // request operand 2 exp!=0xff's |
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| 86 | input inq_mul; // multiply pipe request |
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| 87 | input mul_dest_rdy; // multiply result req accepted for CPX |
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| 88 | input mul_dest_rdya; // multiply result req accepted for CPX |
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| 89 | input fmul_clken_l; // fmul clock enable for mul_frac_dp |
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| 90 | input fmul_clken_l_buf1; // fmul clock enable for mul_exp_dp |
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| 91 | input arst_l; // global asynch. reset- asserted low |
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| 92 | input grst_l; // global synch. reset- asserted low |
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| 93 | input rclk; // global clock |
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| 94 | |
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| 95 | output mul_pipe_active; // mul pipe is executing a valid instr |
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| 96 | output m1stg_step; // multiply pipe load |
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| 97 | output m6stg_fmul_in; // mul pipe output request next cycle |
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| 98 | output [9:0] m6stg_id_in; // mul pipe output ID next cycle |
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| 99 | output [4:0] mul_exc_out; // multiply pipe result- exception flags |
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| 100 | output m6stg_fmul_dbl_dst; // double precision multiply result |
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| 101 | output m6stg_fmuls; // fmuls- multiply 6 stage |
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| 102 | output mul_sign_out; // multiply sign output |
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| 103 | output [10:0] mul_exp_out; // multiply exponent output |
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| 104 | output [51:0] mul_frac_out; // multiply fraction output |
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| 105 | |
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| 106 | input se_mul; // scan_enable for mul_frac_dp, mul_ctl, mul_exp_dp |
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| 107 | input se_mul64; // scan_enable for mul64 |
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| 108 | input si; // scan in |
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| 109 | output so; // scan out |
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| 110 | |
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| 111 | |
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| 112 | /////////////////////////////////////////////////////////////////////////////// |
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| 113 | // |
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| 114 | // Outputs of fpu_mul_ctl. |
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| 115 | // |
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| 116 | /////////////////////////////////////////////////////////////////////////////// |
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| 117 | |
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| 118 | wire m1stg_snan_sng_in1; // operand 1 is single signalling NaN |
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| 119 | wire m1stg_snan_dbl_in1; // operand 1 is double signalling NaN |
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| 120 | wire m1stg_snan_sng_in2; // operand 2 is single signalling NaN |
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| 121 | wire m1stg_snan_dbl_in2; // operand 2 is double signalling NaN |
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| 122 | wire m1stg_step; // multiply pipe load |
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| 123 | wire m1stg_sngop; // single precision operation- mul 1 stg |
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| 124 | wire m1stg_dblop; // double precision operation- mul 1 stg |
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| 125 | wire m1stg_dblop_inv; // single or int operation- mul 1 stg |
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| 126 | wire m1stg_fmul; // multiply operation- mul 1 stage |
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| 127 | wire m1stg_fsmuld; // fsmuld- multiply 1 stage |
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| 128 | wire m2stg_fmuls; // fmuls- multiply 2 stage |
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| 129 | wire m2stg_fmuld; // fmuld- multiply 2 stage |
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| 130 | wire m2stg_fsmuld; // fsmuld- multiply 2 stage |
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| 131 | wire m5stg_fmuls; // fmuls- multiply 5 stage |
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| 132 | wire m5stg_fmuld; // fmuld- multiply 5 stage |
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| 133 | wire m5stg_fmulda; // fmuld- multiply 5 stage copy |
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| 134 | wire m6stg_fmul_in; // mul pipe output request next cycle |
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| 135 | wire [9:0] m6stg_id_in; // mul pipe output ID next cycle |
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| 136 | wire m6stg_fmul_dbl_dst; // double precision multiply result |
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| 137 | wire m6stg_fmuls; // fmuls- multiply 6 stage |
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| 138 | wire m6stg_step; // advance the multiply pipe |
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| 139 | wire mul_sign_out; // multiply sign output |
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| 140 | wire m5stg_in_of; // multiply overflow- select exp out |
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| 141 | wire [4:0] mul_exc_out; // multiply pipe result- exception flags |
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| 142 | wire m2stg_frac1_dbl_norm; // select line to m2stg_frac1 |
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| 143 | wire m2stg_frac1_dbl_dnrm; // select line to m2stg_frac1 |
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| 144 | wire m2stg_frac1_sng_norm; // select line to m2stg_frac1 |
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| 145 | wire m2stg_frac1_sng_dnrm; // select line to m2stg_frac1 |
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| 146 | wire m2stg_frac1_inf; // select line to m2stg_frac1 |
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| 147 | wire m2stg_frac2_dbl_norm; // select line to m2stg_frac2 |
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| 148 | wire m2stg_frac2_dbl_dnrm; // select line to m2stg_frac2 |
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| 149 | wire m2stg_frac2_sng_norm; // select line to m2stg_frac2 |
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| 150 | wire m2stg_frac2_sng_dnrm; // select line to m2stg_frac2 |
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| 151 | wire m2stg_frac2_inf; // select line to m2stg_frac2 |
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| 152 | wire m1stg_inf_zero_in; // 1 operand is infinity; other is 0 |
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| 153 | wire m1stg_inf_zero_in_dbl; // 1 opnd is infinity; other is 0- dbl |
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| 154 | wire m2stg_exp_expadd; // select line to m2stg_exp |
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| 155 | wire m2stg_exp_0bff; // select line to m2stg_exp |
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| 156 | wire m2stg_exp_017f; // select line to m2stg_exp |
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| 157 | wire m2stg_exp_04ff; // select line to m2stg_exp |
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| 158 | wire m2stg_exp_zero; // select line to m2stg_exp |
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| 159 | wire [6:0] m3bstg_ld0_inv; // leading 0's in multiply operands |
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| 160 | wire [5:0] m4stg_sh_cnt_in; // multiply normalization shift count |
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| 161 | wire m4stg_inc_exp_54; // select line to m5stg_exp |
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| 162 | wire m4stg_inc_exp_55; // select line to m5stg_exp |
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| 163 | wire m4stg_inc_exp_105; // select line to m5stg_exp |
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| 164 | wire m4stg_left_shift_step; // select line to m5stg_frac |
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| 165 | wire m4stg_right_shift_step; // select line to m5stg_frac |
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| 166 | wire m5stg_to_0; // result to max finite on overflow |
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| 167 | wire m5stg_to_0_inv; // result to infinity on overflow |
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| 168 | wire mul_frac_out_fracadd; // select line to mul_frac_out |
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| 169 | wire mul_frac_out_frac; // select line to mul_frac_out |
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| 170 | wire mul_exp_out_exp_plus1; // select line to mul_exp_out |
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| 171 | wire mul_exp_out_exp; // select line to mul_exp_out |
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| 172 | wire mul_pipe_active; // mul pipe is executing a valid instr |
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| 173 | |
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| 174 | // 3/14/03: output of dffrl_async is an input to mul64 |
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| 175 | wire mul_rst_l; // reset (active low) signal for mul64 |
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| 176 | |
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| 177 | |
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| 178 | /////////////////////////////////////////////////////////////////////////////// |
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| 179 | // |
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| 180 | // Outputs of fpu_mul_exp_dp. |
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| 181 | // |
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| 182 | /////////////////////////////////////////////////////////////////////////////// |
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| 183 | |
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| 184 | wire [12:0] m3stg_exp; // exponent input- multiply 3 stage |
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| 185 | wire m3stg_expadd_eq_0; // mul stage 3 exponent adder sum == 0 |
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| 186 | wire m3stg_expadd_lte_0_inv; // mul stage 3 exponent adder sum <= 0 |
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| 187 | wire [12:0] m4stg_exp; // exponent input- multiply 4 stage |
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| 188 | wire [12:0] m5stg_exp; // exponent input- multiply 5 stage |
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| 189 | wire [10:0] mul_exp_out; // multiply exponent output |
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| 190 | |
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| 191 | |
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| 192 | /////////////////////////////////////////////////////////////////////////////// |
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| 193 | // |
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| 194 | // Outputs of fpu_mul_frac_dp. |
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| 195 | // |
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| 196 | /////////////////////////////////////////////////////////////////////////////// |
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| 197 | |
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| 198 | wire [52:0] m2stg_frac1_array_in; // multiply array input 1 |
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| 199 | wire [52:0] m2stg_frac2_array_in; // multiply array input 2 |
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| 200 | wire [5:0] m1stg_ld0_1; // denorm operand 1 leading 0's |
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| 201 | wire [5:0] m1stg_ld0_2; // denorm operand 2 leading 0's |
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| 202 | wire m4stg_frac_105; // multiply stage 4a fraction input[105] |
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| 203 | wire [6:0] m3stg_ld0_inv; // leading 0's in multiply operands |
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| 204 | wire m4stg_shl_54; // multiply shift left output bit[54] |
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| 205 | wire m4stg_shl_55; // multiply shift left output bit[55] |
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| 206 | wire [32:0] m5stg_frac_32_0; // multiply stage 5 fraction input |
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| 207 | wire m5stg_frac_dbl_nx; // double precision inexact result |
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| 208 | wire m5stg_frac_sng_nx; // single precision inexact result |
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| 209 | wire m5stg_frac_neq_0; // fraction input to mul 5 stage != 0 |
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| 210 | wire m5stg_fracadd_cout; // fraction rounding adder carry out |
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| 211 | wire [51:0] mul_frac_out; // multiply fraction output |
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| 212 | |
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| 213 | |
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| 214 | /////////////////////////////////////////////////////////////////////////////// |
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| 215 | // |
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| 216 | // Outputs of mul64 |
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| 217 | // |
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| 218 | /////////////////////////////////////////////////////////////////////////////// |
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| 219 | |
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| 220 | wire [105:0] m4stg_frac; // multiply array output |
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| 221 | wire [29:0] m4stg_frac_unused; // unused upper 30 bits (135:106) of the mul64 output |
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| 222 | |
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| 223 | |
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| 224 | /////////////////////////////////////////////////////////////////////////////// |
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| 225 | // |
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| 226 | // Instantiations. |
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| 227 | // |
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| 228 | /////////////////////////////////////////////////////////////////////////////// |
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| 229 | |
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| 230 | fpu_mul_ctl fpu_mul_ctl ( |
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| 231 | .inq_in1_51 (inq_in1[51]), |
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| 232 | .inq_in1_54 (inq_in1[54]), |
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| 233 | .inq_in1_53_0_neq_0 (inq_in1_53_0_neq_0), |
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| 234 | .inq_in1_50_0_neq_0 (inq_in1_50_0_neq_0), |
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| 235 | .inq_in1_53_32_neq_0 (inq_in1_53_32_neq_0), |
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| 236 | .inq_in1_exp_eq_0 (inq_in1_exp_eq_0), |
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| 237 | .inq_in1_exp_neq_ffs (inq_in1_exp_neq_ffs), |
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| 238 | .inq_in2_51 (inq_in2[51]), |
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| 239 | .inq_in2_54 (inq_in2[54]), |
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| 240 | .inq_in2_53_0_neq_0 (inq_in2_53_0_neq_0), |
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| 241 | .inq_in2_50_0_neq_0 (inq_in2_50_0_neq_0), |
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| 242 | .inq_in2_53_32_neq_0 (inq_in2_53_32_neq_0), |
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| 243 | .inq_in2_exp_eq_0 (inq_in2_exp_eq_0), |
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| 244 | .inq_in2_exp_neq_ffs (inq_in2_exp_neq_ffs), |
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| 245 | .inq_op (inq_op[7:0]), |
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| 246 | .inq_mul (inq_mul), |
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| 247 | .inq_rnd_mode (inq_rnd_mode[1:0]), |
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| 248 | .inq_id (inq_id[4:0]), |
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| 249 | .inq_in1_63 (inq_in1[63]), |
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| 250 | .inq_in2_63 (inq_in2[63]), |
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| 251 | .mul_dest_rdy (mul_dest_rdy), |
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| 252 | .mul_dest_rdya (mul_dest_rdya), |
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| 253 | .m5stg_exp (m5stg_exp[12:0]), |
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| 254 | .m5stg_fracadd_cout (m5stg_fracadd_cout), |
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| 255 | .m5stg_frac_neq_0 (m5stg_frac_neq_0), |
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| 256 | .m5stg_frac_dbl_nx (m5stg_frac_dbl_nx), |
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| 257 | .m5stg_frac_sng_nx (m5stg_frac_sng_nx), |
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| 258 | .m1stg_ld0_1 (m1stg_ld0_1[5:0]), |
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| 259 | .m1stg_ld0_2 (m1stg_ld0_2[5:0]), |
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| 260 | .m3stg_exp (m3stg_exp[12:0]), |
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| 261 | .m3stg_expadd_eq_0 (m3stg_expadd_eq_0), |
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| 262 | .m3stg_expadd_lte_0_inv (m3stg_expadd_lte_0_inv), |
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| 263 | .m3stg_ld0_inv (m3stg_ld0_inv[5:0]), |
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| 264 | .m4stg_exp (m4stg_exp[12:0]), |
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| 265 | .m4stg_frac_105 (m4stg_frac_105), |
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| 266 | .m5stg_frac (m5stg_frac_32_0[32:0]), |
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| 267 | .arst_l (arst_l), |
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| 268 | .grst_l (grst_l), |
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| 269 | .mula_rst_l (mul_rst_l), |
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| 270 | .rclk (rclk), |
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| 271 | |
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| 272 | .mul_pipe_active (mul_pipe_active), |
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| 273 | .m1stg_snan_sng_in1 (m1stg_snan_sng_in1), |
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| 274 | .m1stg_snan_dbl_in1 (m1stg_snan_dbl_in1), |
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| 275 | .m1stg_snan_sng_in2 (m1stg_snan_sng_in2), |
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| 276 | .m1stg_snan_dbl_in2 (m1stg_snan_dbl_in2), |
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| 277 | .m1stg_step (m1stg_step), |
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| 278 | .m1stg_sngop (m1stg_sngop), |
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| 279 | .m1stg_dblop (m1stg_dblop), |
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| 280 | .m1stg_dblop_inv (m1stg_dblop_inv), |
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| 281 | .m1stg_fmul (m1stg_fmul), |
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| 282 | .m1stg_fsmuld (m1stg_fsmuld), |
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| 283 | .m2stg_fmuls (m2stg_fmuls), |
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| 284 | .m2stg_fmuld (m2stg_fmuld), |
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| 285 | .m2stg_fsmuld (m2stg_fsmuld), |
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| 286 | .m5stg_fmuls (m5stg_fmuls), |
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| 287 | .m5stg_fmuld (m5stg_fmuld), |
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| 288 | .m5stg_fmulda (m5stg_fmulda), |
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| 289 | .m6stg_fmul_in (m6stg_fmul_in), |
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| 290 | .m6stg_id_in (m6stg_id_in[9:0]), |
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| 291 | .m6stg_fmul_dbl_dst (m6stg_fmul_dbl_dst), |
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| 292 | .m6stg_fmuls (m6stg_fmuls), |
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| 293 | .m6stg_step (m6stg_step), |
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| 294 | .mul_sign_out (mul_sign_out), |
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| 295 | .m5stg_in_of (m5stg_in_of), |
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| 296 | .mul_exc_out (mul_exc_out[4:0]), |
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| 297 | .m2stg_frac1_dbl_norm (m2stg_frac1_dbl_norm), |
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| 298 | .m2stg_frac1_dbl_dnrm (m2stg_frac1_dbl_dnrm), |
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| 299 | .m2stg_frac1_sng_norm (m2stg_frac1_sng_norm), |
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| 300 | .m2stg_frac1_sng_dnrm (m2stg_frac1_sng_dnrm), |
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| 301 | .m2stg_frac1_inf (m2stg_frac1_inf), |
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| 302 | .m2stg_frac2_dbl_norm (m2stg_frac2_dbl_norm), |
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| 303 | .m2stg_frac2_dbl_dnrm (m2stg_frac2_dbl_dnrm), |
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| 304 | .m2stg_frac2_sng_norm (m2stg_frac2_sng_norm), |
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| 305 | .m2stg_frac2_sng_dnrm (m2stg_frac2_sng_dnrm), |
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| 306 | .m2stg_frac2_inf (m2stg_frac2_inf), |
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| 307 | .m1stg_inf_zero_in (m1stg_inf_zero_in), |
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| 308 | .m1stg_inf_zero_in_dbl (m1stg_inf_zero_in_dbl), |
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| 309 | .m2stg_exp_expadd (m2stg_exp_expadd), |
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| 310 | .m2stg_exp_0bff (m2stg_exp_0bff), |
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| 311 | .m2stg_exp_017f (m2stg_exp_017f), |
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| 312 | .m2stg_exp_04ff (m2stg_exp_04ff), |
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| 313 | .m2stg_exp_zero (m2stg_exp_zero), |
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| 314 | .m3bstg_ld0_inv (m3bstg_ld0_inv[6:0]), |
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| 315 | .m4stg_sh_cnt_in (m4stg_sh_cnt_in[5:0]), |
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| 316 | .m4stg_inc_exp_54 (m4stg_inc_exp_54), |
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| 317 | .m4stg_inc_exp_55 (m4stg_inc_exp_55), |
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| 318 | .m4stg_inc_exp_105 (m4stg_inc_exp_105), |
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| 319 | .m4stg_left_shift_step (m4stg_left_shift_step), |
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| 320 | .m4stg_right_shift_step (m4stg_right_shift_step), |
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| 321 | .m5stg_to_0 (m5stg_to_0), |
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| 322 | .m5stg_to_0_inv (m5stg_to_0_inv), |
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| 323 | .mul_frac_out_fracadd (mul_frac_out_fracadd), |
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| 324 | .mul_frac_out_frac (mul_frac_out_frac), |
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| 325 | .mul_exp_out_exp_plus1 (mul_exp_out_exp_plus1), |
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| 326 | .mul_exp_out_exp (mul_exp_out_exp), |
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| 327 | |
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| 328 | .se (se_mul), |
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| 329 | .si (si), |
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| 330 | .so (scan_out_fpu_mul_ctl) |
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| 331 | ); |
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| 332 | |
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| 333 | |
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| 334 | fpu_mul_exp_dp fpu_mul_exp_dp ( |
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| 335 | .inq_in1 (inq_in1[62:52]), |
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| 336 | .inq_in2 (inq_in2[62:52]), |
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| 337 | .m6stg_step (m6stg_step), |
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| 338 | .m1stg_dblop (m1stg_dblop), |
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| 339 | .m1stg_sngop (m1stg_sngop), |
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| 340 | .m2stg_exp_expadd (m2stg_exp_expadd), |
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| 341 | .m2stg_exp_0bff (m2stg_exp_0bff), |
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| 342 | .m2stg_exp_017f (m2stg_exp_017f), |
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| 343 | .m2stg_exp_04ff (m2stg_exp_04ff), |
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| 344 | .m2stg_exp_zero (m2stg_exp_zero), |
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| 345 | .m1stg_fsmuld (m1stg_fsmuld), |
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| 346 | .m2stg_fmuld (m2stg_fmuld), |
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| 347 | .m2stg_fmuls (m2stg_fmuls), |
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| 348 | .m2stg_fsmuld (m2stg_fsmuld), |
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| 349 | .m3stg_ld0_inv (m3stg_ld0_inv[6:0]), |
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| 350 | .m4stg_inc_exp_54 (m4stg_inc_exp_54), |
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| 351 | .m4stg_inc_exp_55 (m4stg_inc_exp_55), |
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| 352 | .m4stg_inc_exp_105 (m4stg_inc_exp_105), |
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| 353 | .m5stg_fracadd_cout (m5stg_fracadd_cout), |
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| 354 | .mul_exp_out_exp_plus1 (mul_exp_out_exp_plus1), |
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| 355 | .mul_exp_out_exp (mul_exp_out_exp), |
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| 356 | .m5stg_in_of (m5stg_in_of), |
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| 357 | .m5stg_fmuld (m5stg_fmuld), |
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| 358 | .m5stg_to_0_inv (m5stg_to_0_inv), |
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| 359 | .m4stg_shl_54 (m4stg_shl_54), |
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| 360 | .m4stg_shl_55 (m4stg_shl_55), |
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| 361 | .fmul_clken_l (fmul_clken_l_buf1), |
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| 362 | .rclk (rclk), |
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| 363 | |
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| 364 | .m3stg_exp (m3stg_exp[12:0]), |
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| 365 | .m3stg_expadd_eq_0 (m3stg_expadd_eq_0), |
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| 366 | .m3stg_expadd_lte_0_inv (m3stg_expadd_lte_0_inv), |
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| 367 | .m4stg_exp (m4stg_exp[12:0]), |
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| 368 | .m5stg_exp (m5stg_exp[12:0]), |
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| 369 | .mul_exp_out (mul_exp_out[10:0]), |
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| 370 | |
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| 371 | .se (se_mul), |
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| 372 | .si (scan_out_fpu_mul_ctl), |
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| 373 | .so (scan_out_fpu_mul_exp_dp) |
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| 374 | ); |
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| 375 | |
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| 376 | |
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| 377 | fpu_mul_frac_dp fpu_mul_frac_dp ( |
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| 378 | .inq_in1 (inq_in1[54:0]), |
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| 379 | .inq_in2 (inq_in2[54:0]), |
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| 380 | .m6stg_step (m6stg_step), |
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| 381 | .m2stg_frac1_dbl_norm (m2stg_frac1_dbl_norm), |
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| 382 | .m2stg_frac1_dbl_dnrm (m2stg_frac1_dbl_dnrm), |
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| 383 | .m2stg_frac1_sng_norm (m2stg_frac1_sng_norm), |
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| 384 | .m2stg_frac1_sng_dnrm (m2stg_frac1_sng_dnrm), |
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| 385 | .m2stg_frac1_inf (m2stg_frac1_inf), |
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| 386 | .m1stg_snan_dbl_in1 (m1stg_snan_dbl_in1), |
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| 387 | .m1stg_snan_sng_in1 (m1stg_snan_sng_in1), |
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| 388 | .m2stg_frac2_dbl_norm (m2stg_frac2_dbl_norm), |
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| 389 | .m2stg_frac2_dbl_dnrm (m2stg_frac2_dbl_dnrm), |
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| 390 | .m2stg_frac2_sng_norm (m2stg_frac2_sng_norm), |
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| 391 | .m2stg_frac2_sng_dnrm (m2stg_frac2_sng_dnrm), |
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| 392 | .m2stg_frac2_inf (m2stg_frac2_inf), |
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| 393 | .m1stg_snan_dbl_in2 (m1stg_snan_dbl_in2), |
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| 394 | .m1stg_snan_sng_in2 (m1stg_snan_sng_in2), |
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| 395 | .m1stg_inf_zero_in (m1stg_inf_zero_in), |
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| 396 | .m1stg_inf_zero_in_dbl (m1stg_inf_zero_in_dbl), |
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| 397 | .m1stg_dblop (m1stg_dblop), |
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| 398 | .m1stg_dblop_inv (m1stg_dblop_inv), |
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| 399 | .m4stg_frac (m4stg_frac), |
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| 400 | .m4stg_sh_cnt_in (m4stg_sh_cnt_in[5:0]), |
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| 401 | .m3bstg_ld0_inv (m3bstg_ld0_inv[6:0]), |
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| 402 | .m4stg_left_shift_step (m4stg_left_shift_step), |
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| 403 | .m4stg_right_shift_step (m4stg_right_shift_step), |
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| 404 | .m5stg_fmuls (m5stg_fmuls), |
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| 405 | .m5stg_fmulda (m5stg_fmulda), |
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| 406 | .mul_frac_out_fracadd (mul_frac_out_fracadd), |
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| 407 | .mul_frac_out_frac (mul_frac_out_frac), |
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| 408 | .m5stg_in_of (m5stg_in_of), |
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| 409 | .m5stg_to_0 (m5stg_to_0), |
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| 410 | .fmul_clken_l (fmul_clken_l), |
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| 411 | .rclk (rclk), |
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| 412 | |
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| 413 | .m2stg_frac1_array_in (m2stg_frac1_array_in), |
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| 414 | .m2stg_frac2_array_in (m2stg_frac2_array_in), |
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| 415 | .m1stg_ld0_1 (m1stg_ld0_1), |
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| 416 | .m1stg_ld0_2 (m1stg_ld0_2), |
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| 417 | .m4stg_frac_105 (m4stg_frac_105), |
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| 418 | .m3stg_ld0_inv (m3stg_ld0_inv[6:0]), |
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| 419 | .m4stg_shl_54 (m4stg_shl_54), |
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| 420 | .m4stg_shl_55 (m4stg_shl_55), |
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| 421 | .m5stg_frac_32_0 (m5stg_frac_32_0[32:0]), |
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| 422 | .m5stg_frac_dbl_nx (m5stg_frac_dbl_nx), |
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| 423 | .m5stg_frac_sng_nx (m5stg_frac_sng_nx), |
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| 424 | .m5stg_frac_neq_0 (m5stg_frac_neq_0), |
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| 425 | .m5stg_fracadd_cout (m5stg_fracadd_cout), |
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| 426 | .mul_frac_out (mul_frac_out[51:0]), |
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| 427 | |
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| 428 | .se (se_mul), |
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| 429 | .si (scan_out_fpu_mul_exp_dp), |
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| 430 | .so (scan_out_fpu_mul_frac_dp) |
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| 431 | ); |
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| 432 | |
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| 433 | |
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| 434 | // 3/14/03: Promoted mul64 to unit level. Got rid of fpu_mul_array. Same representation for RTL and gates. Also, now agreed that mul64 will not have dffrl_async inside, so the staged signal mul_rst_l is sent from fpu_mul_ctl. mul64 port step has been renamed to mul_step to avoid conflicts with DEF keyword STEP in some backend flows (WARP). |
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| 435 | mul64 i_m4stg_frac ( |
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| 436 | .rs1_l ({1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, |
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| 437 | 1'b1, 1'b1, 1'b1, m2stg_frac1_array_in[52:0]}), |
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| 438 | .rs2 ({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 439 | 1'b0, 1'b0, 1'b0, m2stg_frac2_array_in[52:0]}), |
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| 440 | .valid(m1stg_fmul), |
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| 441 | .areg ({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 442 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 443 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 444 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 445 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 446 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 447 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 448 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 449 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 450 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 451 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 452 | 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, |
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| 453 | 1'b0}), |
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| 454 | .accreg ({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}), |
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| 455 | .x2 (1'b0), |
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| 456 | .rclk (rclk), |
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| 457 | .si (scan_out_fpu_mul_frac_dp), |
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| 458 | .se (se_mul64), |
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| 459 | .mul_rst_l (mul_rst_l), |
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| 460 | .mul_step (m6stg_step), |
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| 461 | .so (so), |
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| 462 | .out ({m4stg_frac_unused[29:0], m4stg_frac[105:0]}) |
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| 463 | ); |
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| 464 | |
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| 465 | endmodule |
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| 466 | |
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| 467 | |
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