1 | // ========== Copyright Header Begin ========================================== |
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2 | // |
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3 | // OpenSPARC T1 Processor File: cluster_header.v |
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4 | // Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved. |
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5 | // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES. |
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6 | // |
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7 | // The above named program is free software; you can redistribute it and/or |
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8 | // modify it under the terms of the GNU General Public |
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9 | // License version 2 as published by the Free Software Foundation. |
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10 | // |
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11 | // The above named program is distributed in the hope that it will be |
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12 | // useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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14 | // General Public License for more details. |
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15 | // |
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16 | // You should have received a copy of the GNU General Public |
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17 | // License along with this work; if not, write to the Free Software |
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18 | // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA. |
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19 | // |
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20 | // ========== Copyright Header End ============================================ |
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21 | // The cluster header is instatiated as a hard macro. |
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22 | // This model is for simulation only. |
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23 | `include "sys.h" |
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24 | |
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25 | module cluster_header (/*AUTOARG*/ |
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26 | // Outputs |
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27 | dbginit_l, cluster_grst_l, rclk, so, |
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28 | // Inputs |
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29 | gclk, cluster_cken, arst_l, grst_l, adbginit_l, gdbginit_l, si, |
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30 | se |
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31 | ); |
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32 | |
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33 | input gclk; |
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34 | input cluster_cken; |
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35 | input arst_l; |
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36 | input grst_l; |
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37 | input adbginit_l; |
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38 | input gdbginit_l; |
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39 | output dbginit_l; |
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40 | output cluster_grst_l; |
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41 | output rclk; |
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42 | |
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43 | input si; // scan ports for reset flop repeaters |
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44 | input se; |
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45 | output so; |
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46 | |
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47 | `ifdef FPGA_SYN |
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48 | // assign #10 rclk = gclk; |
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49 | // assign #10 dbginit_l = gdbginit_l; |
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50 | // assign #10 cluster_grst_l = grst_l; |
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51 | // assign so = 1'b0; |
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52 | |
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53 | reg dbginit_l; |
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54 | reg cluster_grst_l; |
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55 | |
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56 | assign #10 rclk = gclk; |
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57 | |
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58 | always @(negedge rclk) begin |
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59 | dbginit_l <= gdbginit_l; |
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60 | cluster_grst_l <= grst_l; |
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61 | end |
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62 | |
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63 | `else |
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64 | |
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65 | wire pre_sync_enable; |
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66 | wire sync_enable; |
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67 | wire cluster_grst_l; |
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68 | wire dbginit_l; |
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69 | wire rst_sync_so; |
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70 | |
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71 | bw_u1_syncff_4x sync_cluster_master ( // no scan hook-up |
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72 | .so(), |
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73 | .q (pre_sync_enable), |
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74 | .ck (gclk), |
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75 | .d (cluster_cken), |
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76 | .sd(1'b0), |
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77 | .se(1'b0) |
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78 | ); |
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79 | |
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80 | |
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81 | bw_u1_scanl_2x sync_cluster_slave ( // use scan lock-up latch |
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82 | .so (sync_enable), |
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83 | .ck (gclk), |
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84 | .sd (pre_sync_enable) |
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85 | ); |
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86 | |
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87 | // NOTE! Pound delay in the below statement is meant to provide 10 ps |
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88 | // delay between gclk and rclk to allow the synchronizer for rst, dbginit, |
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89 | // and sync pulses to be modelled accurately. gclk and rclk need to have |
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90 | // at least one simulator timestep separation to allow the flop->flop |
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91 | // synchronizer to work correctly. |
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92 | assign #10 rclk = gclk & sync_enable; |
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93 | |
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94 | synchronizer_asr rst_repeater ( |
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95 | .sync_out(cluster_grst_l), |
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96 | .so(rst_sync_so), |
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97 | .async_in(grst_l), |
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98 | .gclk(gclk), |
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99 | .rclk(rclk), |
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100 | .arst_l(arst_l), |
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101 | .si(si), |
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102 | .se(se) |
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103 | ); |
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104 | |
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105 | synchronizer_asr dbginit_repeater ( |
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106 | .sync_out(dbginit_l), |
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107 | .so(so), |
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108 | .async_in(gdbginit_l), |
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109 | .gclk(gclk), |
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110 | .rclk(rclk), |
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111 | .arst_l(adbginit_l), |
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112 | .si(rst_sync_so), |
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113 | .se(se) |
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114 | ); |
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115 | `endif |
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116 | |
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117 | endmodule // cluster_header |
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